2 * Copyright 2005-2009 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU Lesser General
5 * Public License. You may obtain a copy of the GNU Lesser General
6 * Public License Version 2.1 or later at the following locations:
8 * http://www.opensource.org/licenses/lgpl-license.html
9 * http://www.gnu.org/copyleft/lgpl.html
15 #include <linux/types.h>
16 #include <linux/videodev2.h>
17 #include <linux/bitmap.h>
19 #include <media/v4l2-mediabus.h>
29 #define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
32 * Bitfield of Display Interface signal polarities.
34 struct ipu_di_signal_cfg {
35 unsigned datamask_en:1;
36 unsigned interlaced:1;
37 unsigned odd_field_first:1;
39 unsigned clkidle_en:1;
40 unsigned data_pol:1; /* true = inverted */
41 unsigned clk_pol:1; /* true = rising edge */
42 unsigned enable_pol:1;
43 unsigned Hsync_pol:1; /* true = active high */
56 unsigned long pixelclock;
57 #define IPU_DI_CLKMODE_SYNC (1 << 0)
58 #define IPU_DI_CLKMODE_EXT (1 << 1)
59 unsigned long clkflags;
66 * Enumeration of CSI destinations
69 IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
70 IPU_CSI_DEST_IC, /* to Image Converter */
71 IPU_CSI_DEST_VDIC, /* to VDIC */
75 * Enumeration of IPU rotation modes
77 enum ipu_rotate_mode {
80 IPU_ROTATE_HORIZ_FLIP,
83 IPU_ROTATE_90_RIGHT_VFLIP,
84 IPU_ROTATE_90_RIGHT_HFLIP,
88 enum ipu_color_space {
91 IPUV3_COLORSPACE_UNKNOWN,
96 enum ipu_channel_irq {
99 IPU_IRQ_NFB4EOF = 128,
104 * Enumeration of IDMAC channels
106 #define IPUV3_CHANNEL_CSI0 0
107 #define IPUV3_CHANNEL_CSI1 1
108 #define IPUV3_CHANNEL_CSI2 2
109 #define IPUV3_CHANNEL_CSI3 3
110 #define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
111 #define IPUV3_CHANNEL_MEM_IC_PP 11
112 #define IPUV3_CHANNEL_MEM_IC_PRP_VF 12
113 #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14
114 #define IPUV3_CHANNEL_G_MEM_IC_PP 15
115 #define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20
116 #define IPUV3_CHANNEL_IC_PRP_VF_MEM 21
117 #define IPUV3_CHANNEL_IC_PP_MEM 22
118 #define IPUV3_CHANNEL_MEM_BG_SYNC 23
119 #define IPUV3_CHANNEL_MEM_BG_ASYNC 24
120 #define IPUV3_CHANNEL_MEM_FG_SYNC 27
121 #define IPUV3_CHANNEL_MEM_DC_SYNC 28
122 #define IPUV3_CHANNEL_MEM_FG_ASYNC 29
123 #define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31
124 #define IPUV3_CHANNEL_MEM_DC_ASYNC 41
125 #define IPUV3_CHANNEL_MEM_ROT_ENC 45
126 #define IPUV3_CHANNEL_MEM_ROT_VF 46
127 #define IPUV3_CHANNEL_MEM_ROT_PP 47
128 #define IPUV3_CHANNEL_ROT_ENC_MEM 48
129 #define IPUV3_CHANNEL_ROT_VF_MEM 49
130 #define IPUV3_CHANNEL_ROT_PP_MEM 50
131 #define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51
133 int ipu_map_irq(struct ipu_soc *ipu, int irq);
134 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
135 enum ipu_channel_irq irq);
137 #define IPU_IRQ_DP_SF_START (448 + 2)
138 #define IPU_IRQ_DP_SF_END (448 + 3)
139 #define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
140 #define IPU_IRQ_DC_FC_0 (448 + 8)
141 #define IPU_IRQ_DC_FC_1 (448 + 9)
142 #define IPU_IRQ_DC_FC_2 (448 + 10)
143 #define IPU_IRQ_DC_FC_3 (448 + 11)
144 #define IPU_IRQ_DC_FC_4 (448 + 12)
145 #define IPU_IRQ_DC_FC_6 (448 + 13)
146 #define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
147 #define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
150 * IPU Common functions
152 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
153 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
156 * IPU Image DMA Controller (idmac) functions
158 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
159 void ipu_idmac_put(struct ipuv3_channel *);
161 int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
162 int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
163 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
164 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
165 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
167 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
169 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
170 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
171 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
172 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
175 * IPU Channel Parameter Memory (cpmem) functions
178 struct fb_bitfield red;
179 struct fb_bitfield green;
180 struct fb_bitfield blue;
181 struct fb_bitfield transp;
186 struct v4l2_pix_format pix;
187 struct v4l2_rect rect;
192 void ipu_cpmem_zero(struct ipuv3_channel *ch);
193 void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
194 void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
195 void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
196 void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
197 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
198 void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
199 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
200 void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
201 void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
202 enum ipu_rotate_mode rot);
203 int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
204 const struct ipu_rgb *rgb);
205 int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
206 void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
207 void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
208 u32 pixel_format, int stride,
209 int u_offset, int v_offset);
210 void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
211 u32 pixel_format, int stride, int height);
212 int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
213 int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
216 * IPU Display Controller (dc) functions
220 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
221 void ipu_dc_put(struct ipu_dc *dc);
222 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
223 u32 pixel_fmt, u32 width);
224 void ipu_dc_enable(struct ipu_soc *ipu);
225 void ipu_dc_enable_channel(struct ipu_dc *dc);
226 void ipu_dc_disable_channel(struct ipu_dc *dc);
227 void ipu_dc_disable(struct ipu_soc *ipu);
230 * IPU Display Interface (di) functions
232 struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
233 void ipu_di_put(struct ipu_di *);
234 int ipu_di_disable(struct ipu_di *);
235 int ipu_di_enable(struct ipu_di *);
236 int ipu_di_get_num(struct ipu_di *);
237 int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
240 * IPU Display Multi FIFO Controller (dmfc) functions
243 int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
244 void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
245 int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
246 unsigned long bandwidth_mbs, int burstsize);
247 void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc);
248 int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width);
249 struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
250 void ipu_dmfc_put(struct dmfc_channel *dmfc);
253 * IPU Display Processor (dp) functions
255 #define IPU_DP_FLOW_SYNC_BG 0
256 #define IPU_DP_FLOW_SYNC_FG 1
257 #define IPU_DP_FLOW_ASYNC0_BG 2
258 #define IPU_DP_FLOW_ASYNC0_FG 3
259 #define IPU_DP_FLOW_ASYNC1_BG 4
260 #define IPU_DP_FLOW_ASYNC1_FG 5
262 struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
263 void ipu_dp_put(struct ipu_dp *);
264 int ipu_dp_enable(struct ipu_soc *ipu);
265 int ipu_dp_enable_channel(struct ipu_dp *dp);
266 void ipu_dp_disable_channel(struct ipu_dp *dp);
267 void ipu_dp_disable(struct ipu_soc *ipu);
268 int ipu_dp_setup_channel(struct ipu_dp *dp,
269 enum ipu_color_space in, enum ipu_color_space out);
270 int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
271 int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
275 * IPU CMOS Sensor Interface (csi) functions
278 int ipu_csi_init_interface(struct ipu_csi *csi,
279 struct v4l2_mbus_config *mbus_cfg,
280 struct v4l2_mbus_framefmt *mbus_fmt);
281 bool ipu_csi_is_interlaced(struct ipu_csi *csi);
282 void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w);
283 void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w);
284 void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
285 u32 r_value, u32 g_value, u32 b_value,
287 int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
288 struct v4l2_mbus_framefmt *mbus_fmt);
289 int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
290 u32 max_ratio, u32 id);
291 int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
292 int ipu_csi_enable(struct ipu_csi *csi);
293 int ipu_csi_disable(struct ipu_csi *csi);
294 struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id);
295 void ipu_csi_put(struct ipu_csi *csi);
296 void ipu_csi_dump(struct ipu_csi *csi);
299 * IPU Image Converter (ic) functions
304 IC_TASK_POST_PROCESSOR,
309 int ipu_ic_task_init(struct ipu_ic *ic,
310 int in_width, int in_height,
311 int out_width, int out_height,
312 enum ipu_color_space in_cs,
313 enum ipu_color_space out_cs);
314 int ipu_ic_task_graphics_init(struct ipu_ic *ic,
315 enum ipu_color_space in_g_cs,
316 bool galpha_en, u32 galpha,
317 bool colorkey_en, u32 colorkey);
318 void ipu_ic_task_enable(struct ipu_ic *ic);
319 void ipu_ic_task_disable(struct ipu_ic *ic);
320 int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
321 u32 width, u32 height, int burst_size,
322 enum ipu_rotate_mode rot);
323 int ipu_ic_enable(struct ipu_ic *ic);
324 int ipu_ic_disable(struct ipu_ic *ic);
325 struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
326 void ipu_ic_put(struct ipu_ic *ic);
327 void ipu_ic_dump(struct ipu_ic *ic);
330 * IPU Sensor Multiple FIFO Controller (SMFC) functions
332 struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno);
333 void ipu_smfc_put(struct ipu_smfc *smfc);
334 int ipu_smfc_enable(struct ipu_smfc *smfc);
335 int ipu_smfc_disable(struct ipu_smfc *smfc);
336 int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
337 int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
338 int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
340 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
341 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
342 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code);
343 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat);
344 bool ipu_pixelformat_is_planar(u32 pixelformat);
345 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
346 bool hflip, bool vflip);
347 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
348 bool hflip, bool vflip);
350 struct ipu_client_platformdata {
359 #endif /* __DRM_IPU_H__ */