1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand has floating-point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisVec - The specified operand has a vector type.
40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>;
42 // SDTCisSameAs - The two specified operands have identical types.
43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
44 int OtherOperandNum = OtherOp;
47 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
48 // smaller than the 'Other' operand.
49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
50 int OtherOperandNum = OtherOp;
53 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
54 int BigOperandNum = BigOp;
57 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
58 /// type as the element type of OtherOp, which is a vector type.
59 class SDTCisEltOfVec<int ThisOp, int OtherOp>
60 : SDTypeConstraint<ThisOp> {
61 int OtherOpNum = OtherOp;
64 /// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type
65 /// with length less that of OtherOp, which is a vector type.
66 class SDTCisSubVecOfVec<int ThisOp, int OtherOp>
67 : SDTypeConstraint<ThisOp> {
68 int OtherOpNum = OtherOp;
71 //===----------------------------------------------------------------------===//
72 // Selection DAG Type Profile definitions.
74 // These use the constraints defined above to describe the type requirements of
75 // the various nodes. These are not hard coded into tblgen, allowing targets to
76 // add their own if needed.
79 // SDTypeProfile - This profile describes the type requirements of a Selection
81 class SDTypeProfile<int numresults, int numoperands,
82 list<SDTypeConstraint> constraints> {
83 int NumResults = numresults;
84 int NumOperands = numoperands;
85 list<SDTypeConstraint> Constraints = constraints;
89 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
90 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
91 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
92 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
93 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
94 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert.
96 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
97 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
99 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
100 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
102 def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem
103 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0>
106 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
107 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
109 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
110 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
112 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
113 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
115 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
116 SDTCisSameAs<0, 1>, SDTCisInt<0>
118 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
119 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
121 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
122 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
124 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
125 SDTCisSameAs<0, 1>, SDTCisFP<0>
127 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
128 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
130 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
131 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
133 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
134 SDTCisFP<0>, SDTCisInt<1>
136 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
137 SDTCisInt<0>, SDTCisFP<1>
139 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
140 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
141 SDTCisVTSmallerThanOp<2, 1>
144 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
145 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
148 def SDTSelect : SDTypeProfile<1, 3, [ // select
149 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
152 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
153 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
157 def SDTBr : SDTypeProfile<0, 1, [ // br
161 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
162 SDTCisInt<0>, SDTCisVT<1, OtherVT>
165 def SDTBrind : SDTypeProfile<0, 1, [ // brind
169 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
171 def SDTLoad : SDTypeProfile<1, 1, [ // load
175 def SDTStore : SDTypeProfile<0, 2, [ // store
179 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
180 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
183 def SDTVecShuffle : SDTypeProfile<1, 2, [
184 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
186 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
187 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
189 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
190 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
193 def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract
194 SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
196 def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert
197 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
200 def SDTPrefetch : SDTypeProfile<0, 3, [ // prefetch
201 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
204 def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barier
205 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
208 def SDTAtomic3 : SDTypeProfile<1, 3, [
209 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
211 def SDTAtomic2 : SDTypeProfile<1, 2, [
212 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
215 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
216 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
219 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
220 SDTypeProfile<0, 1, constraints>;
221 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
222 SDTypeProfile<0, 2, constraints>;
224 //===----------------------------------------------------------------------===//
225 // Selection DAG Node Properties.
227 // Note: These are hard coded into tblgen.
229 class SDNodeProperty;
230 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
231 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
232 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
233 def SDNPOutGlue : SDNodeProperty; // Write a flag result
234 def SDNPInGlue : SDNodeProperty; // Read a flag operand
235 def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand
236 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
237 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
238 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
239 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
240 def SDNPVariadic : SDNodeProperty; // Node has variable arguments.
241 def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match
242 def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent
244 //===----------------------------------------------------------------------===//
245 // Selection DAG Pattern Operations
246 class SDPatternOperator;
248 //===----------------------------------------------------------------------===//
249 // Selection DAG Node definitions.
251 class SDNode<string opcode, SDTypeProfile typeprof,
252 list<SDNodeProperty> props = [], string sdclass = "SDNode">
253 : SDPatternOperator {
254 string Opcode = opcode;
255 string SDClass = sdclass;
256 list<SDNodeProperty> Properties = props;
257 SDTypeProfile TypeProfile = typeprof;
260 // Special TableGen-recognized dag nodes
266 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
267 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
268 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
269 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
270 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
271 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
272 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
273 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
274 "GlobalAddressSDNode">;
275 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
276 "GlobalAddressSDNode">;
277 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
278 "GlobalAddressSDNode">;
279 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
280 "GlobalAddressSDNode">;
281 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
282 "ConstantPoolSDNode">;
283 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
284 "ConstantPoolSDNode">;
285 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
287 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
289 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
291 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
293 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
294 "ExternalSymbolSDNode">;
295 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
296 "ExternalSymbolSDNode">;
297 def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [],
298 "BlockAddressSDNode">;
299 def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [],
300 "BlockAddressSDNode">;
302 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
303 [SDNPCommutative, SDNPAssociative]>;
304 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
305 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
306 [SDNPCommutative, SDNPAssociative]>;
307 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
308 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
309 def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
310 def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
311 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
312 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
313 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
314 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
315 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>;
316 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>;
317 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
318 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
319 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
320 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
321 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
322 def and : SDNode<"ISD::AND" , SDTIntBinOp,
323 [SDNPCommutative, SDNPAssociative]>;
324 def or : SDNode<"ISD::OR" , SDTIntBinOp,
325 [SDNPCommutative, SDNPAssociative]>;
326 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
327 [SDNPCommutative, SDNPAssociative]>;
328 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
329 [SDNPCommutative, SDNPOutGlue]>;
330 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
331 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>;
332 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
334 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
335 [SDNPOutGlue, SDNPInGlue]>;
337 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
338 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
339 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
340 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
341 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
342 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
343 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
344 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
345 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
346 def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>;
347 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
348 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
351 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
352 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
353 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
354 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
355 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
356 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
357 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
358 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
359 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
360 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
361 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
362 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
363 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
364 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
365 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
366 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
367 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
368 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
370 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
371 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
372 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
374 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
375 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
376 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
377 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
378 def f16_to_f32 : SDNode<"ISD::FP16_TO_FP32", SDTIntToFPOp>;
379 def f32_to_f16 : SDNode<"ISD::FP32_TO_FP16", SDTFPToIntOp>;
381 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
382 def select : SDNode<"ISD::SELECT" , SDTSelect>;
383 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
384 def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>;
386 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
387 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
388 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
389 def trap : SDNode<"ISD::TRAP" , SDTNone,
390 [SDNPHasChain, SDNPSideEffect]>;
392 def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch,
393 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
396 def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier,
397 [SDNPHasChain, SDNPSideEffect]>;
399 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3,
400 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
401 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2,
402 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
403 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2,
404 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
405 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2,
406 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
407 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2,
408 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
409 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2,
410 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
411 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2,
412 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
413 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2,
414 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
415 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2,
416 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
417 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2,
418 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
419 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2,
420 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
421 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2,
422 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
424 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
425 // and truncst (see below).
426 def ld : SDNode<"ISD::LOAD" , SDTLoad,
427 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
428 def st : SDNode<"ISD::STORE" , SDTStore,
429 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
430 def ist : SDNode<"ISD::STORE" , SDTIStore,
431 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
433 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
434 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
435 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
437 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
438 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
439 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
440 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
442 // This operator does not do subvector type checking. The ARM
443 // backend, at least, needs it.
444 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
445 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>,
448 // This operator does subvector type checking.
449 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
450 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
452 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
453 // these internally. Don't reference these directly.
454 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
455 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
457 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
458 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
460 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
461 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
463 // Do not use cvt directly. Use cvt forms below
464 def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>;
466 //===----------------------------------------------------------------------===//
467 // Selection DAG Condition Codes
469 class CondCode; // ISD::CondCode enums
470 def SETOEQ : CondCode; def SETOGT : CondCode;
471 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
472 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
473 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
474 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
476 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
477 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
480 //===----------------------------------------------------------------------===//
481 // Selection DAG Node Transformation Functions.
483 // This mechanism allows targets to manipulate nodes in the output DAG once a
484 // match has been formed. This is typically used to manipulate immediate
487 class SDNodeXForm<SDNode opc, code xformFunction> {
489 code XFormFunction = xformFunction;
492 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
494 //===----------------------------------------------------------------------===//
495 // PatPred Subclasses.
497 // These allow specifying different sorts of predicates that control whether a
502 class CodePatPred<code predicate> : PatPred {
503 code PredicateCode = predicate;
507 //===----------------------------------------------------------------------===//
508 // Selection DAG Pattern Fragments.
510 // Pattern fragments are reusable chunks of dags that match specific things.
511 // They can take arguments and have C++ predicates that control whether they
512 // match. They are intended to make the patterns for common instructions more
513 // compact and readable.
516 /// PatFrag - Represents a pattern fragment. This can match something on the
517 /// DAG, from a single node to multiple nested other fragments.
519 class PatFrag<dag ops, dag frag, code pred = [{}],
520 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator {
523 code PredicateCode = pred;
524 code ImmediateCode = [{}];
525 SDNodeXForm OperandTransform = xform;
528 // PatLeaf's are pattern fragments that have no operands. This is just a helper
529 // to define immediates and other common things concisely.
530 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
531 : PatFrag<(ops), frag, pred, xform>;
534 // ImmLeaf is a pattern fragment with a constraint on the immediate. The
535 // constraint is a function that is run on the immediate (always with the value
536 // sign extended out to an int64_t) as Imm. For example:
538 // def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>;
540 // this is a more convenient form to match 'imm' nodes in than PatLeaf and also
541 // is preferred over using PatLeaf because it allows the code generator to
542 // reason more about the constraint.
544 // If FastIsel should ignore all instructions that have an operand of this type,
545 // the FastIselShouldIgnore flag can be set. This is an optimization to reduce
546 // the code size of the generated fast instruction selector.
547 class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
548 : PatFrag<(ops), (vt imm), [{}], xform> {
549 let ImmediateCode = pred;
550 bit FastIselShouldIgnore = 0;
556 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
557 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
559 def immAllOnesV: PatLeaf<(build_vector), [{
560 return ISD::isBuildVectorAllOnes(N);
562 def immAllZerosV: PatLeaf<(build_vector), [{
563 return ISD::isBuildVectorAllZeros(N);
568 // Other helper fragments.
569 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>;
570 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
571 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
574 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
575 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
577 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
578 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
581 // extending load fragments.
582 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
583 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
585 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
586 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
588 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
589 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
592 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
593 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
595 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
596 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
598 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
599 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
601 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
602 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
604 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
605 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
607 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
608 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
611 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
612 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
614 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
615 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
617 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
618 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
620 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
621 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
624 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
625 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
627 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
628 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
630 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
631 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
633 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
634 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
638 def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
639 (st node:$val, node:$ptr), [{
640 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
642 def store : PatFrag<(ops node:$val, node:$ptr),
643 (unindexedstore node:$val, node:$ptr), [{
644 return !cast<StoreSDNode>(N)->isTruncatingStore();
647 // truncstore fragments.
648 def truncstore : PatFrag<(ops node:$val, node:$ptr),
649 (unindexedstore node:$val, node:$ptr), [{
650 return cast<StoreSDNode>(N)->isTruncatingStore();
652 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
653 (truncstore node:$val, node:$ptr), [{
654 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
656 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
657 (truncstore node:$val, node:$ptr), [{
658 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
660 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
661 (truncstore node:$val, node:$ptr), [{
662 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
664 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
665 (truncstore node:$val, node:$ptr), [{
666 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
668 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
669 (truncstore node:$val, node:$ptr), [{
670 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
673 // indexed store fragments.
674 def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
675 (ist node:$val, node:$base, node:$offset), [{
676 return !cast<StoreSDNode>(N)->isTruncatingStore();
679 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
680 (istore node:$val, node:$base, node:$offset), [{
681 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
682 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
685 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
686 (ist node:$val, node:$base, node:$offset), [{
687 return cast<StoreSDNode>(N)->isTruncatingStore();
689 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
690 (itruncstore node:$val, node:$base, node:$offset), [{
691 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
692 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
694 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
695 (pre_truncst node:$val, node:$base, node:$offset), [{
696 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
698 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
699 (pre_truncst node:$val, node:$base, node:$offset), [{
700 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
702 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
703 (pre_truncst node:$val, node:$base, node:$offset), [{
704 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
706 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
707 (pre_truncst node:$val, node:$base, node:$offset), [{
708 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
710 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
711 (pre_truncst node:$val, node:$base, node:$offset), [{
712 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
715 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
716 (istore node:$val, node:$ptr, node:$offset), [{
717 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
718 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
721 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
722 (itruncstore node:$val, node:$base, node:$offset), [{
723 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
724 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
726 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
727 (post_truncst node:$val, node:$base, node:$offset), [{
728 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
730 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
731 (post_truncst node:$val, node:$base, node:$offset), [{
732 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
734 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
735 (post_truncst node:$val, node:$base, node:$offset), [{
736 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
738 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
739 (post_truncst node:$val, node:$base, node:$offset), [{
740 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
742 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
743 (post_truncst node:$val, node:$base, node:$offset), [{
744 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
747 // setcc convenience fragments.
748 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
749 (setcc node:$lhs, node:$rhs, SETOEQ)>;
750 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
751 (setcc node:$lhs, node:$rhs, SETOGT)>;
752 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
753 (setcc node:$lhs, node:$rhs, SETOGE)>;
754 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
755 (setcc node:$lhs, node:$rhs, SETOLT)>;
756 def setole : PatFrag<(ops node:$lhs, node:$rhs),
757 (setcc node:$lhs, node:$rhs, SETOLE)>;
758 def setone : PatFrag<(ops node:$lhs, node:$rhs),
759 (setcc node:$lhs, node:$rhs, SETONE)>;
760 def seto : PatFrag<(ops node:$lhs, node:$rhs),
761 (setcc node:$lhs, node:$rhs, SETO)>;
762 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
763 (setcc node:$lhs, node:$rhs, SETUO)>;
764 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
765 (setcc node:$lhs, node:$rhs, SETUEQ)>;
766 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
767 (setcc node:$lhs, node:$rhs, SETUGT)>;
768 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
769 (setcc node:$lhs, node:$rhs, SETUGE)>;
770 def setult : PatFrag<(ops node:$lhs, node:$rhs),
771 (setcc node:$lhs, node:$rhs, SETULT)>;
772 def setule : PatFrag<(ops node:$lhs, node:$rhs),
773 (setcc node:$lhs, node:$rhs, SETULE)>;
774 def setune : PatFrag<(ops node:$lhs, node:$rhs),
775 (setcc node:$lhs, node:$rhs, SETUNE)>;
776 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
777 (setcc node:$lhs, node:$rhs, SETEQ)>;
778 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
779 (setcc node:$lhs, node:$rhs, SETGT)>;
780 def setge : PatFrag<(ops node:$lhs, node:$rhs),
781 (setcc node:$lhs, node:$rhs, SETGE)>;
782 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
783 (setcc node:$lhs, node:$rhs, SETLT)>;
784 def setle : PatFrag<(ops node:$lhs, node:$rhs),
785 (setcc node:$lhs, node:$rhs, SETLE)>;
786 def setne : PatFrag<(ops node:$lhs, node:$rhs),
787 (setcc node:$lhs, node:$rhs, SETNE)>;
789 def atomic_cmp_swap_8 :
790 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
791 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
792 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
794 def atomic_cmp_swap_16 :
795 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
796 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
797 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
799 def atomic_cmp_swap_32 :
800 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
801 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
802 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
804 def atomic_cmp_swap_64 :
805 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
806 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
807 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
810 multiclass binary_atomic_op<SDNode atomic_op> {
811 def _8 : PatFrag<(ops node:$ptr, node:$val),
812 (atomic_op node:$ptr, node:$val), [{
813 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
815 def _16 : PatFrag<(ops node:$ptr, node:$val),
816 (atomic_op node:$ptr, node:$val), [{
817 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
819 def _32 : PatFrag<(ops node:$ptr, node:$val),
820 (atomic_op node:$ptr, node:$val), [{
821 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
823 def _64 : PatFrag<(ops node:$ptr, node:$val),
824 (atomic_op node:$ptr, node:$val), [{
825 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
829 defm atomic_load_add : binary_atomic_op<atomic_load_add>;
830 defm atomic_swap : binary_atomic_op<atomic_swap>;
831 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>;
832 defm atomic_load_and : binary_atomic_op<atomic_load_and>;
833 defm atomic_load_or : binary_atomic_op<atomic_load_or>;
834 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>;
835 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>;
836 defm atomic_load_min : binary_atomic_op<atomic_load_min>;
837 defm atomic_load_max : binary_atomic_op<atomic_load_max>;
838 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>;
839 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>;
841 //===----------------------------------------------------------------------===//
842 // Selection DAG CONVERT_RNDSAT patterns
844 def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
845 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
846 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
849 def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
850 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
851 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
854 def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
855 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
856 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
859 def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
860 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
861 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
864 def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
865 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
866 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
869 def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
870 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
871 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
874 def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
875 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
876 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
879 def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
880 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
881 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
884 def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
885 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
886 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
889 //===----------------------------------------------------------------------===//
890 // Selection DAG Pattern Support.
892 // Patterns are what are actually matched against by the target-flavored
893 // instruction selection DAG. Instructions defined by the target implicitly
894 // define patterns in most cases, but patterns can also be explicitly added when
895 // an operation is defined by a sequence of instructions (e.g. loading a large
896 // immediate value on RISC targets that do not support immediates as large as
900 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
901 dag PatternToMatch = patternToMatch;
902 list<dag> ResultInstrs = resultInstrs;
903 list<Predicate> Predicates = []; // See class Instruction in Target.td.
904 int AddedComplexity = 0; // See class Instruction in Target.td.
907 // Pat - A simple (but common) form of a pattern, which produces a simple result
908 // not needing a full list.
909 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
911 //===----------------------------------------------------------------------===//
912 // Complex pattern definitions.
915 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
916 // in C++. NumOperands is the number of operands returned by the select function;
917 // SelectFunc is the name of the function used to pattern match the max. pattern;
918 // RootNodes are the list of possible root nodes of the sub-dags to match.
919 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
921 class ComplexPattern<ValueType ty, int numops, string fn,
922 list<SDNode> roots = [], list<SDNodeProperty> props = []> {
924 int NumOperands = numops;
925 string SelectFunc = fn;
926 list<SDNode> RootNodes = roots;
927 list<SDNodeProperty> Properties = props;