1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineValueType.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/CommandLine.h"
31 class MachineFunction;
33 template<class T> class SmallVectorImpl;
38 /// A bitmask representing the covering of a register with sub-registers.
40 /// This is typically used to track liveness at sub-register granularity.
41 /// Lane masks for sub-register indices are similar to register units for
42 /// physical registers. The individual bits in a lane mask can't be assigned
43 /// any specific meaning. They can be used to check if two sub-register
46 /// Iff the target has a register such that:
48 /// getSubReg(Reg, A) overlaps getSubReg(Reg, B)
52 /// (getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B)) != 0
53 typedef unsigned LaneBitmask;
55 class TargetRegisterClass {
57 typedef const MCPhysReg* iterator;
58 typedef const MCPhysReg* const_iterator;
59 typedef const MVT::SimpleValueType* vt_iterator;
60 typedef const TargetRegisterClass* const * sc_iterator;
62 // Instance variables filled by tablegen, do not use!
63 const MCRegisterClass *MC;
64 const vt_iterator VTs;
65 const uint32_t *SubClassMask;
66 const uint16_t *SuperRegIndices;
67 const LaneBitmask LaneMask;
68 /// Classes with a higher priority value are assigned first by register
69 /// allocators using a greedy heuristic. The value is in the range [0,63].
70 const uint8_t AllocationPriority;
71 /// Whether the class supports two (or more) disjunct subregister indices.
72 const bool HasDisjunctSubRegs;
73 const sc_iterator SuperClasses;
74 ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
76 /// Return the register class ID number.
77 unsigned getID() const { return MC->getID(); }
79 /// begin/end - Return all of the registers in this class.
81 iterator begin() const { return MC->begin(); }
82 iterator end() const { return MC->end(); }
84 /// Return the number of registers in this class.
85 unsigned getNumRegs() const { return MC->getNumRegs(); }
87 /// Return the specified register in the class.
88 unsigned getRegister(unsigned i) const {
89 return MC->getRegister(i);
92 /// Return true if the specified register is included in this register class.
93 /// This does not include virtual registers.
94 bool contains(unsigned Reg) const {
95 return MC->contains(Reg);
98 /// Return true if both registers are in this class.
99 bool contains(unsigned Reg1, unsigned Reg2) const {
100 return MC->contains(Reg1, Reg2);
103 /// Return the size of the register in bytes, which is also the size
104 /// of a stack slot allocated to hold a spilled copy of this register.
105 unsigned getSize() const { return MC->getSize(); }
107 /// Return the minimum required alignment for a register of this class.
108 unsigned getAlignment() const { return MC->getAlignment(); }
110 /// Return the cost of copying a value between two registers in this class.
111 /// A negative number means the register class is very expensive
112 /// to copy e.g. status flag register classes.
113 int getCopyCost() const { return MC->getCopyCost(); }
115 /// Return true if this register class may be used to create virtual
117 bool isAllocatable() const { return MC->isAllocatable(); }
119 /// Return true if this TargetRegisterClass has the ValueType vt.
120 bool hasType(MVT vt) const {
121 for(int i = 0; VTs[i] != MVT::Other; ++i)
122 if (MVT(VTs[i]) == vt)
127 /// vt_begin / vt_end - Loop over all of the value types that can be
128 /// represented by values in this register class.
129 vt_iterator vt_begin() const {
133 vt_iterator vt_end() const {
135 while (*I != MVT::Other) ++I;
139 /// Return true if the specified TargetRegisterClass
140 /// is a proper sub-class of this TargetRegisterClass.
141 bool hasSubClass(const TargetRegisterClass *RC) const {
142 return RC != this && hasSubClassEq(RC);
145 /// Returns true if RC is a sub-class of or equal to this class.
146 bool hasSubClassEq(const TargetRegisterClass *RC) const {
147 unsigned ID = RC->getID();
148 return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
151 /// Return true if the specified TargetRegisterClass is a
152 /// proper super-class of this TargetRegisterClass.
153 bool hasSuperClass(const TargetRegisterClass *RC) const {
154 return RC->hasSubClass(this);
157 /// Returns true if RC is a super-class of or equal to this class.
158 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
159 return RC->hasSubClassEq(this);
162 /// Returns a bit vector of subclasses, including this one.
163 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
165 const uint32_t *getSubClassMask() const {
169 /// Returns a 0-terminated list of sub-register indices that project some
170 /// super-register class into this register class. The list has an entry for
171 /// each Idx such that:
173 /// There exists SuperRC where:
174 /// For all Reg in SuperRC:
175 /// this->contains(Reg:Idx)
177 const uint16_t *getSuperRegIndices() const {
178 return SuperRegIndices;
181 /// Returns a NULL-terminated list of super-classes. The
182 /// classes are ordered by ID which is also a topological ordering from large
183 /// to small classes. The list does NOT include the current class.
184 sc_iterator getSuperClasses() const {
188 /// Return true if this TargetRegisterClass is a subset
189 /// class of at least one other TargetRegisterClass.
190 bool isASubClass() const {
191 return SuperClasses[0] != nullptr;
194 /// Returns the preferred order for allocating registers from this register
195 /// class in MF. The raw order comes directly from the .td file and may
196 /// include reserved registers that are not allocatable.
197 /// Register allocators should also make sure to allocate
198 /// callee-saved registers only after all the volatiles are used. The
199 /// RegisterClassInfo class provides filtered allocation orders with
200 /// callee-saved registers moved to the end.
202 /// The MachineFunction argument can be used to tune the allocatable
203 /// registers based on the characteristics of the function, subtarget, or
206 /// By default, this method returns all registers in the class.
208 ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
209 return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
212 /// Returns the combination of all lane masks of register in this class.
213 /// The lane masks of the registers are the combination of all lane masks
214 /// of their subregisters.
215 LaneBitmask getLaneMask() const {
220 /// Extra information, not in MCRegisterDesc, about registers.
221 /// These are used by codegen, not by MC.
222 struct TargetRegisterInfoDesc {
223 unsigned CostPerUse; // Extra cost of instructions using register.
224 bool inAllocatableClass; // Register belongs to an allocatable regclass.
227 /// Each TargetRegisterClass has a per register weight, and weight
228 /// limit which must be less than the limits of its pressure sets.
229 struct RegClassWeight {
231 unsigned WeightLimit;
234 /// TargetRegisterInfo base class - We assume that the target defines a static
235 /// array of TargetRegisterDesc objects that represent all of the machine
236 /// registers that the target has. As such, we simply have to track a pointer
237 /// to this array so that we can turn register number into a register
240 class TargetRegisterInfo : public MCRegisterInfo {
242 typedef const TargetRegisterClass * const * regclass_iterator;
244 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
245 const char *const *SubRegIndexNames; // Names of subreg indexes.
246 // Pointer to array of lane masks, one per sub-reg index.
247 const LaneBitmask *SubRegIndexLaneMasks;
249 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
250 unsigned CoveringLanes;
253 TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
254 regclass_iterator RegClassBegin,
255 regclass_iterator RegClassEnd,
256 const char *const *SRINames,
257 const LaneBitmask *SRILaneMasks,
258 unsigned CoveringLanes);
259 virtual ~TargetRegisterInfo();
262 // Register numbers can represent physical registers, virtual registers, and
263 // sometimes stack slots. The unsigned values are divided into these ranges:
265 // 0 Not a register, can be used as a sentinel.
266 // [1;2^30) Physical registers assigned by TableGen.
267 // [2^30;2^31) Stack slots. (Rarely used.)
268 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
270 // Further sentinels can be allocated from the small negative integers.
271 // DenseMapInfo<unsigned> uses -1u and -2u.
273 /// isStackSlot - Sometimes it is useful the be able to store a non-negative
274 /// frame index in a variable that normally holds a register. isStackSlot()
275 /// returns true if Reg is in the range used for stack slots.
277 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
278 /// slots, so if a variable may contains a stack slot, always check
279 /// isStackSlot() first.
281 static bool isStackSlot(unsigned Reg) {
282 return int(Reg) >= (1 << 30);
285 /// Compute the frame index from a register value representing a stack slot.
286 static int stackSlot2Index(unsigned Reg) {
287 assert(isStackSlot(Reg) && "Not a stack slot");
288 return int(Reg - (1u << 30));
291 /// Convert a non-negative frame index to a stack slot register value.
292 static unsigned index2StackSlot(int FI) {
293 assert(FI >= 0 && "Cannot hold a negative frame index.");
294 return FI + (1u << 30);
297 /// Return true if the specified register number is in
298 /// the physical register namespace.
299 static bool isPhysicalRegister(unsigned Reg) {
300 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
304 /// Return true if the specified register number is in
305 /// the virtual register namespace.
306 static bool isVirtualRegister(unsigned Reg) {
307 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
311 /// Convert a virtual register number to a 0-based index.
312 /// The first virtual register in a function will get the index 0.
313 static unsigned virtReg2Index(unsigned Reg) {
314 assert(isVirtualRegister(Reg) && "Not a virtual register");
315 return Reg & ~(1u << 31);
318 /// Convert a 0-based index to a virtual register number.
319 /// This is the inverse operation of VirtReg2IndexFunctor below.
320 static unsigned index2VirtReg(unsigned Index) {
321 return Index | (1u << 31);
324 /// Returns the Register Class of a physical register of the given type,
325 /// picking the most sub register class of the right type that contains this
327 const TargetRegisterClass *
328 getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const;
330 /// Return the maximal subclass of the given register class that is
331 /// allocatable or NULL.
332 const TargetRegisterClass *
333 getAllocatableClass(const TargetRegisterClass *RC) const;
335 /// Returns a bitset indexed by register number indicating if a register is
336 /// allocatable or not. If a register class is specified, returns the subset
338 BitVector getAllocatableSet(const MachineFunction &MF,
339 const TargetRegisterClass *RC = nullptr) const;
341 /// Return the additional cost of using this register instead
342 /// of other registers in its class.
343 unsigned getCostPerUse(unsigned RegNo) const {
344 return InfoDesc[RegNo].CostPerUse;
347 /// Return true if the register is in the allocation of any register class.
348 bool isInAllocatableClass(unsigned RegNo) const {
349 return InfoDesc[RegNo].inAllocatableClass;
352 /// Return the human-readable symbolic target-specific
353 /// name for the specified SubRegIndex.
354 const char *getSubRegIndexName(unsigned SubIdx) const {
355 assert(SubIdx && SubIdx < getNumSubRegIndices() &&
356 "This is not a subregister index");
357 return SubRegIndexNames[SubIdx-1];
360 /// Return a bitmask representing the parts of a register that are covered by
361 /// SubIdx \see LaneBitmask.
363 /// SubIdx == 0 is allowed, it has the lane mask ~0u.
364 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
365 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
366 return SubRegIndexLaneMasks[SubIdx];
369 /// The lane masks returned by getSubRegIndexLaneMask() above can only be
370 /// used to determine if sub-registers overlap - they can't be used to
371 /// determine if a set of sub-registers completely cover another
374 /// The X86 general purpose registers have two lanes corresponding to the
375 /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
376 /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
377 /// sub_32bit sub-register.
379 /// On the other hand, the ARM NEON lanes fully cover their registers: The
380 /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
381 /// This is related to the CoveredBySubRegs property on register definitions.
383 /// This function returns a bit mask of lanes that completely cover their
384 /// sub-registers. More precisely, given:
386 /// Covering = getCoveringLanes();
387 /// MaskA = getSubRegIndexLaneMask(SubA);
388 /// MaskB = getSubRegIndexLaneMask(SubB);
390 /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
392 LaneBitmask getCoveringLanes() const { return CoveringLanes; }
394 /// Returns true if the two registers are equal or alias each other.
395 /// The registers may be virtual registers.
396 bool regsOverlap(unsigned regA, unsigned regB) const {
397 if (regA == regB) return true;
398 if (isVirtualRegister(regA) || isVirtualRegister(regB))
401 // Regunits are numerically ordered. Find a common unit.
402 MCRegUnitIterator RUA(regA, this);
403 MCRegUnitIterator RUB(regB, this);
405 if (*RUA == *RUB) return true;
406 if (*RUA < *RUB) ++RUA;
408 } while (RUA.isValid() && RUB.isValid());
412 /// Returns true if Reg contains RegUnit.
413 bool hasRegUnit(unsigned Reg, unsigned RegUnit) const {
414 for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
415 if (*Units == RegUnit)
420 /// Return a null-terminated list of all of the callee-saved registers on
421 /// this target. The register should be in the order of desired callee-save
422 /// stack frame offset. The first register is closest to the incoming stack
423 /// pointer if stack grows down, and vice versa.
425 virtual const MCPhysReg*
426 getCalleeSavedRegs(const MachineFunction *MF) const = 0;
428 /// Return a mask of call-preserved registers for the given calling convention
429 /// on the current function. The mask should include all call-preserved
430 /// aliases. This is used by the register allocator to determine which
431 /// registers can be live across a call.
433 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
434 /// A set bit indicates that all bits of the corresponding register are
435 /// preserved across the function call. The bit mask is expected to be
436 /// sub-register complete, i.e. if A is preserved, so are all its
439 /// Bits are numbered from the LSB, so the bit for physical register Reg can
440 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
442 /// A NULL pointer means that no register mask will be used, and call
443 /// instructions should use implicit-def operands to indicate call clobbered
446 virtual const uint32_t *getCallPreservedMask(const MachineFunction &MF,
447 CallingConv::ID) const {
448 // The default mask clobbers everything. All targets should override.
452 /// Return a register mask that clobbers everything.
453 virtual const uint32_t *getNoPreservedMask() const {
454 llvm_unreachable("target does not provide no presered mask");
457 /// Return all the call-preserved register masks defined for this target.
458 virtual ArrayRef<const uint32_t *> getRegMasks() const = 0;
459 virtual ArrayRef<const char *> getRegMaskNames() const = 0;
461 /// Returns a bitset indexed by physical register number indicating if a
462 /// register is a special register that has particular uses and should be
463 /// considered unavailable at all times, e.g. SP, RA. This is
464 /// used by register scavenger to determine what registers are free.
465 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
467 /// Prior to adding the live-out mask to a stackmap or patchpoint
468 /// instruction, provide the target the opportunity to adjust it (mainly to
469 /// remove pseudo-registers that should be ignored).
470 virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const { }
472 /// Return a super-register of the specified register
473 /// Reg so its sub-register of index SubIdx is Reg.
474 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
475 const TargetRegisterClass *RC) const {
476 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
479 /// Return a subclass of the specified register
480 /// class A so that each register in it has a sub-register of the
481 /// specified sub-register index which is in the specified register class B.
483 /// TableGen will synthesize missing A sub-classes.
484 virtual const TargetRegisterClass *
485 getMatchingSuperRegClass(const TargetRegisterClass *A,
486 const TargetRegisterClass *B, unsigned Idx) const;
488 // For a copy-like instruction that defines a register of class DefRC with
489 // subreg index DefSubReg, reading from another source with class SrcRC and
490 // subregister SrcSubReg return true if this is a preferrable copy
491 // instruction or an earlier use should be used.
492 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
494 const TargetRegisterClass *SrcRC,
495 unsigned SrcSubReg) const;
497 /// Returns the largest legal sub-class of RC that
498 /// supports the sub-register index Idx.
499 /// If no such sub-class exists, return NULL.
500 /// If all registers in RC already have an Idx sub-register, return RC.
502 /// TableGen generates a version of this function that is good enough in most
503 /// cases. Targets can override if they have constraints that TableGen
504 /// doesn't understand. For example, the x86 sub_8bit sub-register index is
505 /// supported by the full GR32 register class in 64-bit mode, but only by the
506 /// GR32_ABCD regiister class in 32-bit mode.
508 /// TableGen will synthesize missing RC sub-classes.
509 virtual const TargetRegisterClass *
510 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
511 assert(Idx == 0 && "Target has no sub-registers");
515 /// Return the subregister index you get from composing
516 /// two subregister indices.
518 /// The special null sub-register index composes as the identity.
520 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
521 /// returns c. Note that composeSubRegIndices does not tell you about illegal
522 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
523 /// b, composeSubRegIndices doesn't tell you.
525 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
526 /// ssub_0:S0 - ssub_3:S3 subregs.
527 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
529 unsigned composeSubRegIndices(unsigned a, unsigned b) const {
532 return composeSubRegIndicesImpl(a, b);
535 /// Transforms a LaneMask computed for one subregister to the lanemask that
536 /// would have been computed when composing the subsubregisters with IdxA
537 /// first. @sa composeSubRegIndices()
538 LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA,
539 LaneBitmask Mask) const {
542 return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
545 /// Debugging helper: dump register in human readable form to dbgs() stream.
546 static void dumpReg(unsigned Reg, unsigned SubRegIndex = 0,
547 const TargetRegisterInfo* TRI = nullptr);
550 /// Overridden by TableGen in targets that have sub-registers.
551 virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
552 llvm_unreachable("Target has no sub-registers");
555 /// Overridden by TableGen in targets that have sub-registers.
557 composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const {
558 llvm_unreachable("Target has no sub-registers");
562 /// Find a common super-register class if it exists.
564 /// Find a register class, SuperRC and two sub-register indices, PreA and
567 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
569 /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
571 /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
573 /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
574 /// requirements, and there is no register class with a smaller spill size
575 /// that satisfies the requirements.
577 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
579 /// Either of the PreA and PreB sub-register indices may be returned as 0. In
580 /// that case, the returned register class will be a sub-class of the
581 /// corresponding argument register class.
583 /// The function returns NULL if no register class can be found.
585 const TargetRegisterClass*
586 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
587 const TargetRegisterClass *RCB, unsigned SubB,
588 unsigned &PreA, unsigned &PreB) const;
590 //===--------------------------------------------------------------------===//
591 // Register Class Information
594 /// Register class iterators
596 regclass_iterator regclass_begin() const { return RegClassBegin; }
597 regclass_iterator regclass_end() const { return RegClassEnd; }
599 unsigned getNumRegClasses() const {
600 return (unsigned)(regclass_end()-regclass_begin());
603 /// Returns the register class associated with the enumeration value.
604 /// See class MCOperandInfo.
605 const TargetRegisterClass *getRegClass(unsigned i) const {
606 assert(i < getNumRegClasses() && "Register Class ID out of range");
607 return RegClassBegin[i];
610 /// Returns the name of the register class.
611 const char *getRegClassName(const TargetRegisterClass *Class) const {
612 return MCRegisterInfo::getRegClassName(Class->MC);
615 /// Find the largest common subclass of A and B.
616 /// Return NULL if there is no common subclass.
617 const TargetRegisterClass *
618 getCommonSubClass(const TargetRegisterClass *A,
619 const TargetRegisterClass *B) const;
621 /// Returns a TargetRegisterClass used for pointer values.
622 /// If a target supports multiple different pointer register classes,
623 /// kind specifies which one is indicated.
624 virtual const TargetRegisterClass *
625 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
626 llvm_unreachable("Target didn't implement getPointerRegClass!");
629 /// Returns a legal register class to copy a register in the specified class
630 /// to or from. If it is possible to copy the register directly without using
631 /// a cross register class copy, return the specified RC. Returns NULL if it
632 /// is not possible to copy between two registers of the specified class.
633 virtual const TargetRegisterClass *
634 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
638 /// Returns the largest super class of RC that is legal to use in the current
639 /// sub-target and has the same spill size.
640 /// The returned register class can be used to create virtual registers which
641 /// means that all its registers can be copied and spilled.
642 virtual const TargetRegisterClass *
643 getLargestLegalSuperClass(const TargetRegisterClass *RC,
644 const MachineFunction &) const {
645 /// The default implementation is very conservative and doesn't allow the
646 /// register allocator to inflate register classes.
650 /// Return the register pressure "high water mark" for the specific register
651 /// class. The scheduler is in high register pressure mode (for the specific
652 /// register class) if it goes over the limit.
654 /// Note: this is the old register pressure model that relies on a manually
655 /// specified representative register class per value type.
656 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
657 MachineFunction &MF) const {
661 /// Get the weight in units of pressure for this register class.
662 virtual const RegClassWeight &getRegClassWeight(
663 const TargetRegisterClass *RC) const = 0;
665 /// Get the weight in units of pressure for this register unit.
666 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
668 /// Get the number of dimensions of register pressure.
669 virtual unsigned getNumRegPressureSets() const = 0;
671 /// Get the name of this register unit pressure set.
672 virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
674 /// Get the register unit pressure limit for this dimension.
675 /// This limit must be adjusted dynamically for reserved registers.
676 virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
677 unsigned Idx) const = 0;
679 /// Get the dimensions of register pressure impacted by this register class.
680 /// Returns a -1 terminated array of pressure set IDs.
681 virtual const int *getRegClassPressureSets(
682 const TargetRegisterClass *RC) const = 0;
684 /// Get the dimensions of register pressure impacted by this register unit.
685 /// Returns a -1 terminated array of pressure set IDs.
686 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
688 /// Get a list of 'hint' registers that the register allocator should try
689 /// first when allocating a physical register for the virtual register
690 /// VirtReg. These registers are effectively moved to the front of the
691 /// allocation order.
693 /// The Order argument is the allocation order for VirtReg's register class
694 /// as returned from RegisterClassInfo::getOrder(). The hint registers must
695 /// come from Order, and they must not be reserved.
697 /// The default implementation of this function can resolve
698 /// target-independent hints provided to MRI::setRegAllocationHint with
699 /// HintType == 0. Targets that override this function should defer to the
700 /// default implementation if they have no reason to change the allocation
701 /// order for VirtReg. There may be target-independent hints.
702 virtual void getRegAllocationHints(unsigned VirtReg,
703 ArrayRef<MCPhysReg> Order,
704 SmallVectorImpl<MCPhysReg> &Hints,
705 const MachineFunction &MF,
706 const VirtRegMap *VRM = nullptr,
707 const LiveRegMatrix *Matrix = nullptr)
710 /// A callback to allow target a chance to update register allocation hints
711 /// when a register is "changed" (e.g. coalesced) to another register.
712 /// e.g. On ARM, some virtual registers should target register pairs,
713 /// if one of pair is coalesced to another register, the allocation hint of
714 /// the other half of the pair should be changed to point to the new register.
715 virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg,
716 MachineFunction &MF) const {
720 /// Allow the target to reverse allocation order of local live ranges. This
721 /// will generally allocate shorter local live ranges first. For targets with
722 /// many registers, this could reduce regalloc compile time by a large
723 /// factor. It is disabled by default for three reasons:
724 /// (1) Top-down allocation is simpler and easier to debug for targets that
725 /// don't benefit from reversing the order.
726 /// (2) Bottom-up allocation could result in poor evicition decisions on some
727 /// targets affecting the performance of compiled code.
728 /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
729 virtual bool reverseLocalAssignment() const { return false; }
731 /// Allow the target to override the cost of using a callee-saved register for
732 /// the first time. Default value of 0 means we will use a callee-saved
733 /// register if it is available.
734 virtual unsigned getCSRFirstUseCost() const { return 0; }
736 /// Returns true if the target requires (and can make use of) the register
738 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
742 /// Returns true if the target wants to use frame pointer based accesses to
743 /// spill to the scavenger emergency spill slot.
744 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
748 /// Returns true if the target requires post PEI scavenging of registers for
749 /// materializing frame index constants.
750 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
754 /// Returns true if the target wants the LocalStackAllocation pass to be run
755 /// and virtual base registers used for more efficient stack access.
756 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
760 /// Return true if target has reserved a spill slot in the stack frame of
761 /// the given function for the specified register. e.g. On x86, if the frame
762 /// register is required, the first fixed stack object is reserved as its
763 /// spill slot. This tells PEI not to create a new stack frame
764 /// object for the given register. It should be called only after
765 /// determineCalleeSaves().
766 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
767 int &FrameIdx) const {
771 /// Returns true if the live-ins should be tracked after register allocation.
772 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
776 /// True if the stack can be realigned for the target.
777 virtual bool canRealignStack(const MachineFunction &MF) const;
779 /// True if storage within the function requires the stack pointer to be
780 /// aligned more than the normal calling convention calls for.
781 /// This cannot be overriden by the target, but canRealignStack can be
783 bool needsStackRealignment(const MachineFunction &MF) const;
785 /// Get the offset from the referenced frame index in the instruction,
787 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
792 /// Returns true if the instruction's frame index reference would be better
793 /// served by a base register other than FP or SP.
794 /// Used by LocalStackFrameAllocation to determine which frame index
795 /// references it should create new base registers for.
796 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
800 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
801 /// before insertion point I.
802 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
803 unsigned BaseReg, int FrameIdx,
804 int64_t Offset) const {
805 llvm_unreachable("materializeFrameBaseRegister does not exist on this "
809 /// Resolve a frame index operand of an instruction
810 /// to reference the indicated base register plus offset instead.
811 virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
812 int64_t Offset) const {
813 llvm_unreachable("resolveFrameIndex does not exist on this target");
816 /// Determine whether a given base register plus offset immediate is
817 /// encodable to resolve a frame index.
818 virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
819 int64_t Offset) const {
820 llvm_unreachable("isFrameOffsetLegal does not exist on this target");
823 /// Spill the register so it can be used by the register scavenger.
824 /// Return true if the register was spilled, false otherwise.
825 /// If this function does not spill the register, the scavenger
826 /// will instead spill it to the emergency spill slot.
828 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
829 MachineBasicBlock::iterator I,
830 MachineBasicBlock::iterator &UseMI,
831 const TargetRegisterClass *RC,
832 unsigned Reg) const {
836 /// This method must be overriden to eliminate abstract frame indices from
837 /// instructions which may use them. The instruction referenced by the
838 /// iterator contains an MO_FrameIndex operand which must be eliminated by
839 /// this method. This method may modify or replace the specified instruction,
840 /// as long as it keeps the iterator pointing at the finished product.
841 /// SPAdj is the SP adjustment due to call frame setup instruction.
842 /// FIOperandNum is the FI operand number.
843 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
844 int SPAdj, unsigned FIOperandNum,
845 RegScavenger *RS = nullptr) const = 0;
847 //===--------------------------------------------------------------------===//
850 /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true.
851 virtual bool shouldCoalesce(MachineInstr *MI,
852 const TargetRegisterClass *SrcRC,
854 const TargetRegisterClass *DstRC,
856 const TargetRegisterClass *NewRC) const
859 //===--------------------------------------------------------------------===//
860 /// Debug information queries.
862 /// getFrameRegister - This method should return the register used as a base
863 /// for values allocated in the current stack frame.
864 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
868 //===----------------------------------------------------------------------===//
869 // SuperRegClassIterator
870 //===----------------------------------------------------------------------===//
872 // Iterate over the possible super-registers for a given register class. The
873 // iterator will visit a list of pairs (Idx, Mask) corresponding to the
874 // possible classes of super-registers.
876 // Each bit mask will have at least one set bit, and each set bit in Mask
877 // corresponds to a SuperRC such that:
879 // For all Reg in SuperRC: Reg:Idx is in RC.
881 // The iterator can include (O, RC->getSubClassMask()) as the first entry which
882 // also satisfies the above requirement, assuming Reg:0 == Reg.
884 class SuperRegClassIterator {
885 const unsigned RCMaskWords;
888 const uint32_t *Mask;
891 /// Create a SuperRegClassIterator that visits all the super-register classes
892 /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
893 SuperRegClassIterator(const TargetRegisterClass *RC,
894 const TargetRegisterInfo *TRI,
895 bool IncludeSelf = false)
896 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
898 Idx(RC->getSuperRegIndices()),
899 Mask(RC->getSubClassMask()) {
904 /// Returns true if this iterator is still pointing at a valid entry.
905 bool isValid() const { return Idx; }
907 /// Returns the current sub-register index.
908 unsigned getSubReg() const { return SubReg; }
910 /// Returns the bit mask if register classes that getSubReg() projects into
912 const uint32_t *getMask() const { return Mask; }
914 /// Advance iterator to the next entry.
916 assert(isValid() && "Cannot move iterator past end.");
924 // This is useful when building IndexedMaps keyed on virtual registers
925 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
926 unsigned operator()(unsigned Reg) const {
927 return TargetRegisterInfo::virtReg2Index(Reg);
931 /// Helper class for printing registers on a raw_ostream.
932 /// Prints virtual and physical registers with or without a TRI instance.
935 /// %noreg - NoRegister
936 /// %vreg5 - a virtual register.
937 /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
938 /// %EAX - a physical register
939 /// %physreg17 - a physical register when no TRI instance given.
941 /// Usage: OS << PrintReg(Reg, TRI) << '\n';
944 const TargetRegisterInfo *TRI;
948 explicit PrintReg(unsigned reg, const TargetRegisterInfo *tri = nullptr,
950 : TRI(tri), Reg(reg), SubIdx(subidx) {}
951 void print(raw_ostream&) const;
954 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
959 /// Helper class for printing register units on a raw_ostream.
961 /// Register units are named after their root registers:
963 /// AL - Single root.
964 /// FP0~ST7 - Dual roots.
966 /// Usage: OS << PrintRegUnit(Unit, TRI) << '\n';
970 const TargetRegisterInfo *TRI;
973 PrintRegUnit(unsigned unit, const TargetRegisterInfo *tri)
974 : TRI(tri), Unit(unit) {}
975 void print(raw_ostream&) const;
978 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintRegUnit &PR) {
983 /// It is often convenient to track virtual registers and
984 /// physical register units in the same list.
985 class PrintVRegOrUnit : protected PrintRegUnit {
987 PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *tri)
988 : PrintRegUnit(VRegOrUnit, tri) {}
989 void print(raw_ostream&) const;
992 static inline raw_ostream &operator<<(raw_ostream &OS,
993 const PrintVRegOrUnit &PR) {
998 /// Helper class for printing lane masks.
1000 /// They are currently printed out as hexadecimal numbers.
1001 /// Usage: OS << PrintLaneMask(Mask);
1002 class PrintLaneMask {
1004 LaneBitmask LaneMask;
1006 PrintLaneMask(LaneBitmask LaneMask)
1007 : LaneMask(LaneMask) {}
1008 void print(raw_ostream&) const;
1011 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintLaneMask &P) {
1016 } // End llvm namespace