1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/ADT/DenseSet.h"
28 class MachineFunction;
31 template<class T> class SmallVectorImpl;
34 /// TargetRegisterDesc - This record contains all of the information known about
35 /// a particular register. The Overlaps field contains a pointer to a zero
36 /// terminated array of registers that this register aliases, starting with
37 /// itself. This is needed for architectures like X86 which have AL alias AX
38 /// alias EAX. The SubRegs field is a zero terminated array of registers that
39 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers of
40 /// AX. The SuperRegs field is a zero terminated array of registers that are
41 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
44 struct TargetRegisterDesc {
45 const char *Name; // Printable name for the reg (for debugging)
46 const unsigned *Overlaps; // Overlapping registers, described above
47 const unsigned *SubRegs; // Sub-register set, described above
48 const unsigned *SuperRegs; // Super-register set, described above
49 unsigned CostPerUse; // Extra cost of instructions using register.
52 class TargetRegisterClass {
54 typedef const unsigned* iterator;
55 typedef const unsigned* const_iterator;
57 typedef const EVT* vt_iterator;
58 typedef const TargetRegisterClass* const * sc_iterator;
62 const vt_iterator VTs;
63 const sc_iterator SubClasses;
64 const sc_iterator SuperClasses;
65 const sc_iterator SubRegClasses;
66 const sc_iterator SuperRegClasses;
67 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
69 const iterator RegsBegin, RegsEnd;
70 DenseSet<unsigned> RegSet;
72 TargetRegisterClass(unsigned id,
75 const TargetRegisterClass * const *subcs,
76 const TargetRegisterClass * const *supcs,
77 const TargetRegisterClass * const *subregcs,
78 const TargetRegisterClass * const *superregcs,
79 unsigned RS, unsigned Al, int CC,
80 iterator RB, iterator RE)
81 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
82 SubRegClasses(subregcs), SuperRegClasses(superregcs),
83 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {
84 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
87 virtual ~TargetRegisterClass() {} // Allow subclasses
89 /// getID() - Return the register class ID number.
91 unsigned getID() const { return ID; }
93 /// getName() - Return the register class name for debugging.
95 const char *getName() const { return Name; }
97 /// begin/end - Return all of the registers in this class.
99 iterator begin() const { return RegsBegin; }
100 iterator end() const { return RegsEnd; }
102 /// getNumRegs - Return the number of registers in this class.
104 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
106 /// getRegister - Return the specified register in the class.
108 unsigned getRegister(unsigned i) const {
109 assert(i < getNumRegs() && "Register number out of range!");
113 /// contains - Return true if the specified register is included in this
114 /// register class. This does not include virtual registers.
115 bool contains(unsigned Reg) const {
116 return RegSet.count(Reg);
119 /// contains - Return true if both registers are in this class.
120 bool contains(unsigned Reg1, unsigned Reg2) const {
121 return contains(Reg1) && contains(Reg2);
124 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
126 bool hasType(EVT vt) const {
127 for(int i = 0; VTs[i] != MVT::Other; ++i)
133 /// vt_begin / vt_end - Loop over all of the value types that can be
134 /// represented by values in this register class.
135 vt_iterator vt_begin() const {
139 vt_iterator vt_end() const {
141 while (*I != MVT::Other) ++I;
145 /// subregclasses_begin / subregclasses_end - Loop over all of
146 /// the subreg register classes of this register class.
147 sc_iterator subregclasses_begin() const {
148 return SubRegClasses;
151 sc_iterator subregclasses_end() const {
152 sc_iterator I = SubRegClasses;
153 while (*I != NULL) ++I;
157 /// getSubRegisterRegClass - Return the register class of subregisters with
158 /// index SubIdx, or NULL if no such class exists.
159 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
160 assert(SubIdx>0 && "Invalid subregister index");
161 return SubRegClasses[SubIdx-1];
164 /// superregclasses_begin / superregclasses_end - Loop over all of
165 /// the superreg register classes of this register class.
166 sc_iterator superregclasses_begin() const {
167 return SuperRegClasses;
170 sc_iterator superregclasses_end() const {
171 sc_iterator I = SuperRegClasses;
172 while (*I != NULL) ++I;
176 /// hasSubClass - return true if the specified TargetRegisterClass
177 /// is a proper subset of this TargetRegisterClass.
178 bool hasSubClass(const TargetRegisterClass *cs) const {
179 for (int i = 0; SubClasses[i] != NULL; ++i)
180 if (SubClasses[i] == cs)
185 /// subclasses_begin / subclasses_end - Loop over all of the classes
186 /// that are proper subsets of this register class.
187 sc_iterator subclasses_begin() const {
191 sc_iterator subclasses_end() const {
192 sc_iterator I = SubClasses;
193 while (*I != NULL) ++I;
197 /// hasSuperClass - return true if the specified TargetRegisterClass is a
198 /// proper superset of this TargetRegisterClass.
199 bool hasSuperClass(const TargetRegisterClass *cs) const {
200 for (int i = 0; SuperClasses[i] != NULL; ++i)
201 if (SuperClasses[i] == cs)
206 /// superclasses_begin / superclasses_end - Loop over all of the classes
207 /// that are proper supersets of this register class.
208 sc_iterator superclasses_begin() const {
212 sc_iterator superclasses_end() const {
213 sc_iterator I = SuperClasses;
214 while (*I != NULL) ++I;
218 /// isASubClass - return true if this TargetRegisterClass is a subset
219 /// class of at least one other TargetRegisterClass.
220 bool isASubClass() const {
221 return SuperClasses[0] != 0;
224 /// allocation_order_begin/end - These methods define a range of registers
225 /// which specify the registers in this class that are valid to register
226 /// allocate, and the preferred order to allocate them in. For example,
227 /// callee saved registers should be at the end of the list, because it is
228 /// cheaper to allocate caller saved registers.
230 /// These methods take a MachineFunction argument, which can be used to tune
231 /// the allocatable registers based on the characteristics of the function,
232 /// subtarget, or other criteria.
234 /// Register allocators should account for the fact that an allocation
235 /// order iterator may return a reserved register and always check
236 /// if the register is allocatable (getAllocatableSet()) before using it.
238 /// By default, these methods return all registers in the class.
240 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
243 virtual iterator allocation_order_end(const MachineFunction &MF) const {
247 /// getSize - Return the size of the register in bytes, which is also the size
248 /// of a stack slot allocated to hold a spilled copy of this register.
249 unsigned getSize() const { return RegSize; }
251 /// getAlignment - Return the minimum required alignment for a register of
253 unsigned getAlignment() const { return Alignment; }
255 /// getCopyCost - Return the cost of copying a value between two registers in
256 /// this class. A negative number means the register class is very expensive
257 /// to copy e.g. status flag register classes.
258 int getCopyCost() const { return CopyCost; }
262 /// TargetRegisterInfo base class - We assume that the target defines a static
263 /// array of TargetRegisterDesc objects that represent all of the machine
264 /// registers that the target has. As such, we simply have to track a pointer
265 /// to this array so that we can turn register number into a register
268 class TargetRegisterInfo {
270 const unsigned* SubregHash;
271 const unsigned SubregHashSize;
272 const unsigned* AliasesHash;
273 const unsigned AliasesHashSize;
275 typedef const TargetRegisterClass * const * regclass_iterator;
277 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
278 const char *const *SubRegIndexNames; // Names of subreg indexes.
279 unsigned NumRegs; // Number of entries in the array
281 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
283 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
286 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
287 regclass_iterator RegClassBegin,
288 regclass_iterator RegClassEnd,
289 const char *const *subregindexnames,
290 int CallFrameSetupOpcode = -1,
291 int CallFrameDestroyOpcode = -1,
292 const unsigned* subregs = 0,
293 const unsigned subregsize = 0,
294 const unsigned* aliases = 0,
295 const unsigned aliasessize = 0);
296 virtual ~TargetRegisterInfo();
299 // Register numbers can represent physical registers, virtual registers, and
300 // sometimes stack slots. The unsigned values are divided into these ranges:
302 // 0 Not a register, can be used as a sentinel.
303 // [1;2^30) Physical registers assigned by TableGen.
304 // [2^30;2^31) Stack slots. (Rarely used.)
305 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
307 // Further sentinels can be allocated from the small negative integers.
308 // DenseMapInfo<unsigned> uses -1u and -2u.
310 /// isStackSlot - Sometimes it is useful the be able to store a non-negative
311 /// frame index in a variable that normally holds a register. isStackSlot()
312 /// returns true if Reg is in the range used for stack slots.
314 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
315 /// slots, so if a variable may contains a stack slot, always check
316 /// isStackSlot() first.
318 static bool isStackSlot(unsigned Reg) {
319 return int(Reg) >= (1 << 30);
322 /// stackSlot2Index - Compute the frame index from a register value
323 /// representing a stack slot.
324 static int stackSlot2Index(unsigned Reg) {
325 assert(isStackSlot(Reg) && "Not a stack slot");
326 return int(Reg - (1u << 30));
329 /// index2StackSlot - Convert a non-negative frame index to a stack slot
331 static unsigned index2StackSlot(int FI) {
332 assert(FI >= 0 && "Cannot hold a negative frame index.");
333 return FI + (1u << 30);
336 /// isPhysicalRegister - Return true if the specified register number is in
337 /// the physical register namespace.
338 static bool isPhysicalRegister(unsigned Reg) {
339 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
343 /// isVirtualRegister - Return true if the specified register number is in
344 /// the virtual register namespace.
345 static bool isVirtualRegister(unsigned Reg) {
346 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
350 /// virtReg2Index - Convert a virtual register number to a 0-based index.
351 /// The first virtual register in a function will get the index 0.
352 static unsigned virtReg2Index(unsigned Reg) {
353 assert(isVirtualRegister(Reg) && "Not a virtual register");
354 return Reg & ~(1u << 31);
357 /// index2VirtReg - Convert a 0-based index to a virtual register number.
358 /// This is the inverse operation of VirtReg2IndexFunctor below.
359 static unsigned index2VirtReg(unsigned Index) {
360 return Index | (1u << 31);
363 /// getMinimalPhysRegClass - Returns the Register Class of a physical
364 /// register of the given type, picking the most sub register class of
365 /// the right type that contains this physreg.
366 const TargetRegisterClass *
367 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
369 /// getAllocatableSet - Returns a bitset indexed by register number
370 /// indicating if a register is allocatable or not. If a register class is
371 /// specified, returns the subset for the class.
372 BitVector getAllocatableSet(const MachineFunction &MF,
373 const TargetRegisterClass *RC = NULL) const;
375 const TargetRegisterDesc &operator[](unsigned RegNo) const {
376 assert(RegNo < NumRegs &&
377 "Attempting to access record for invalid register number!");
381 /// Provide a get method, equivalent to [], but more useful if we have a
382 /// pointer to this object.
384 const TargetRegisterDesc &get(unsigned RegNo) const {
385 return operator[](RegNo);
388 /// getAliasSet - Return the set of registers aliased by the specified
389 /// register, or a null list of there are none. The list returned is zero
392 const unsigned *getAliasSet(unsigned RegNo) const {
393 // The Overlaps set always begins with Reg itself.
394 return get(RegNo).Overlaps + 1;
397 /// getOverlaps - Return a list of registers that overlap Reg, including
398 /// itself. This is the same as the alias set except Reg is included in the
400 /// These are exactly the registers in { x | regsOverlap(x, Reg) }.
402 const unsigned *getOverlaps(unsigned RegNo) const {
403 return get(RegNo).Overlaps;
406 /// getSubRegisters - Return the list of registers that are sub-registers of
407 /// the specified register, or a null list of there are none. The list
408 /// returned is zero terminated and sorted according to super-sub register
409 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
411 const unsigned *getSubRegisters(unsigned RegNo) const {
412 return get(RegNo).SubRegs;
415 /// getSuperRegisters - Return the list of registers that are super-registers
416 /// of the specified register, or a null list of there are none. The list
417 /// returned is zero terminated and sorted according to super-sub register
418 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
420 const unsigned *getSuperRegisters(unsigned RegNo) const {
421 return get(RegNo).SuperRegs;
424 /// getName - Return the human-readable symbolic target-specific name for the
425 /// specified physical register.
426 const char *getName(unsigned RegNo) const {
427 return get(RegNo).Name;
430 /// getCostPerUse - Return the additional cost of using this register instead
431 /// of other registers in its class.
432 unsigned getCostPerUse(unsigned RegNo) const {
433 return get(RegNo).CostPerUse;
436 /// getNumRegs - Return the number of registers this target has (useful for
437 /// sizing arrays holding per register information)
438 unsigned getNumRegs() const {
442 /// getSubRegIndexName - Return the human-readable symbolic target-specific
443 /// name for the specified SubRegIndex.
444 const char *getSubRegIndexName(unsigned SubIdx) const {
445 assert(SubIdx && "This is not a subregister index");
446 return SubRegIndexNames[SubIdx-1];
449 /// regsOverlap - Returns true if the two registers are equal or alias each
450 /// other. The registers may be virtual register.
451 bool regsOverlap(unsigned regA, unsigned regB) const {
455 if (isVirtualRegister(regA) || isVirtualRegister(regB))
458 // regA and regB are distinct physical registers. Do they alias?
459 size_t index = (regA + regB * 37) & (AliasesHashSize-1);
460 unsigned ProbeAmt = 0;
461 while (AliasesHash[index*2] != 0 &&
462 AliasesHash[index*2+1] != 0) {
463 if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB)
466 index = (index + ProbeAmt) & (AliasesHashSize-1);
473 /// isSubRegister - Returns true if regB is a sub-register of regA.
475 bool isSubRegister(unsigned regA, unsigned regB) const {
476 // SubregHash is a simple quadratically probed hash table.
477 size_t index = (regA + regB * 37) & (SubregHashSize-1);
478 unsigned ProbeAmt = 2;
479 while (SubregHash[index*2] != 0 &&
480 SubregHash[index*2+1] != 0) {
481 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
484 index = (index + ProbeAmt) & (SubregHashSize-1);
491 /// isSuperRegister - Returns true if regB is a super-register of regA.
493 bool isSuperRegister(unsigned regA, unsigned regB) const {
494 return isSubRegister(regB, regA);
497 /// getCalleeSavedRegs - Return a null-terminated list of all of the
498 /// callee saved registers on this target. The register should be in the
499 /// order of desired callee-save stack frame offset. The first register is
500 /// closed to the incoming stack pointer if stack grows down, and vice versa.
501 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
505 /// getReservedRegs - Returns a bitset indexed by physical register number
506 /// indicating if a register is a special register that has particular uses
507 /// and should be considered unavailable at all times, e.g. SP, RA. This is
508 /// used by register scavenger to determine what registers are free.
509 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
511 /// getSubReg - Returns the physical register number of sub-register "Index"
512 /// for physical register RegNo. Return zero if the sub-register does not
514 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
516 /// getSubRegIndex - For a given register pair, return the sub-register index
517 /// if the second register is a sub-register of the first. Return zero
519 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0;
521 /// getMatchingSuperReg - Return a super-register of the specified register
522 /// Reg so its sub-register of index SubIdx is Reg.
523 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
524 const TargetRegisterClass *RC) const {
525 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
526 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
531 /// canCombineSubRegIndices - Given a register class and a list of
532 /// subregister indices, return true if it's possible to combine the
533 /// subregister indices into one that corresponds to a larger
534 /// subregister. Return the new subregister index by reference. Note the
535 /// new index may be zero if the given subregisters can be combined to
536 /// form the whole register.
537 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
538 SmallVectorImpl<unsigned> &SubIndices,
539 unsigned &NewSubIdx) const {
543 /// getMatchingSuperRegClass - Return a subclass of the specified register
544 /// class A so that each register in it has a sub-register of the
545 /// specified sub-register index which is in the specified register class B.
546 virtual const TargetRegisterClass *
547 getMatchingSuperRegClass(const TargetRegisterClass *A,
548 const TargetRegisterClass *B, unsigned Idx) const {
552 /// composeSubRegIndices - Return the subregister index you get from composing
553 /// two subregister indices.
555 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
556 /// returns c. Note that composeSubRegIndices does not tell you about illegal
557 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
558 /// b, composeSubRegIndices doesn't tell you.
560 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
561 /// ssub_0:S0 - ssub_3:S3 subregs.
562 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
564 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const {
565 // This default implementation is correct for most targets.
569 //===--------------------------------------------------------------------===//
570 // Register Class Information
573 /// Register class iterators
575 regclass_iterator regclass_begin() const { return RegClassBegin; }
576 regclass_iterator regclass_end() const { return RegClassEnd; }
578 unsigned getNumRegClasses() const {
579 return (unsigned)(regclass_end()-regclass_begin());
582 /// getRegClass - Returns the register class associated with the enumeration
583 /// value. See class TargetOperandInfo.
584 const TargetRegisterClass *getRegClass(unsigned i) const {
585 assert(i < getNumRegClasses() && "Register Class ID out of range");
586 return RegClassBegin[i];
589 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
590 /// values. If a target supports multiple different pointer register classes,
591 /// kind specifies which one is indicated.
592 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
593 assert(0 && "Target didn't implement getPointerRegClass!");
594 return 0; // Must return a value in order to compile with VS 2005
597 /// getCrossCopyRegClass - Returns a legal register class to copy a register
598 /// in the specified class to or from. If it is possible to copy the register
599 /// directly without using a cross register class copy, return the specified
600 /// RC. Returns NULL if it is not possible to copy between a two registers of
601 /// the specified class.
602 virtual const TargetRegisterClass *
603 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
607 /// getLargestLegalSuperClass - Returns the largest super class of RC that is
608 /// legal to use in the current sub-target and has the same spill size.
609 /// The returned register class can be used to create virtual registers which
610 /// means that all its registers can be copied and spilled.
611 virtual const TargetRegisterClass*
612 getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
613 /// The default implementation is very conservative and doesn't allow the
614 /// register allocator to inflate register classes.
618 /// getRegPressureLimit - Return the register pressure "high water mark" for
619 /// the specific register class. The scheduler is in high register pressure
620 /// mode (for the specific register class) if it goes over the limit.
621 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
622 MachineFunction &MF) const {
626 /// getAllocationOrder - Returns the register allocation order for a specified
627 /// register class in the form of a pair of TargetRegisterClass iterators.
628 virtual std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
629 getAllocationOrder(const TargetRegisterClass *RC,
630 unsigned HintType, unsigned HintReg,
631 const MachineFunction &MF) const {
632 return std::make_pair(RC->allocation_order_begin(MF),
633 RC->allocation_order_end(MF));
636 /// ResolveRegAllocHint - Resolves the specified register allocation hint
637 /// to a physical register. Returns the physical register if it is successful.
638 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
639 const MachineFunction &MF) const {
640 if (Type == 0 && Reg && isPhysicalRegister(Reg))
645 /// avoidWriteAfterWrite - Return true if the register allocator should avoid
646 /// writing a register from RC in two consecutive instructions.
647 /// This can avoid pipeline stalls on certain architectures.
648 /// It does cause increased register pressure, though.
649 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
653 /// UpdateRegAllocHint - A callback to allow target a chance to update
654 /// register allocation hints when a register is "changed" (e.g. coalesced)
655 /// to another register. e.g. On ARM, some virtual registers should target
656 /// register pairs, if one of pair is coalesced to another register, the
657 /// allocation hint of the other half of the pair should be changed to point
658 /// to the new register.
659 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
660 MachineFunction &MF) const {
664 /// requiresRegisterScavenging - returns true if the target requires (and can
665 /// make use of) the register scavenger.
666 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
670 /// useFPForScavengingIndex - returns true if the target wants to use
671 /// frame pointer based accesses to spill to the scavenger emergency spill
673 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
677 /// requiresFrameIndexScavenging - returns true if the target requires post
678 /// PEI scavenging of registers for materializing frame index constants.
679 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
683 /// requiresVirtualBaseRegisters - Returns true if the target wants the
684 /// LocalStackAllocation pass to be run and virtual base registers
685 /// used for more efficient stack access.
686 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
690 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
691 /// the stack frame of the given function for the specified register. e.g. On
692 /// x86, if the frame register is required, the first fixed stack object is
693 /// reserved as its spill slot. This tells PEI not to create a new stack frame
694 /// object for the given register. It should be called only after
695 /// processFunctionBeforeCalleeSavedScan().
696 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
697 int &FrameIdx) const {
701 /// needsStackRealignment - true if storage within the function requires the
702 /// stack pointer to be aligned more than the normal calling convention calls
704 virtual bool needsStackRealignment(const MachineFunction &MF) const {
708 /// getFrameIndexInstrOffset - Get the offset from the referenced frame
709 /// index in the instruction, if there is one.
710 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
715 /// needsFrameBaseReg - Returns true if the instruction's frame index
716 /// reference would be better served by a base register other than FP
717 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
718 /// references it should create new base registers for.
719 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
723 /// materializeFrameBaseRegister - Insert defining instruction(s) for
724 /// BaseReg to be a pointer to FrameIdx before insertion point I.
725 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
726 unsigned BaseReg, int FrameIdx,
727 int64_t Offset) const {
728 assert(0 && "materializeFrameBaseRegister does not exist on this target");
731 /// resolveFrameIndex - Resolve a frame index operand of an instruction
732 /// to reference the indicated base register plus offset instead.
733 virtual void resolveFrameIndex(MachineBasicBlock::iterator I,
734 unsigned BaseReg, int64_t Offset) const {
735 assert(0 && "resolveFrameIndex does not exist on this target");
738 /// isFrameOffsetLegal - Determine whether a given offset immediate is
739 /// encodable to resolve a frame index.
740 virtual bool isFrameOffsetLegal(const MachineInstr *MI,
741 int64_t Offset) const {
742 assert(0 && "isFrameOffsetLegal does not exist on this target");
743 return false; // Must return a value in order to compile with VS 2005
746 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
747 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
748 /// targets use pseudo instructions in order to abstract away the difference
749 /// between operating with a frame pointer and operating without, through the
750 /// use of these two instructions.
752 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
753 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
755 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
756 /// code insertion to eliminate call frame setup and destroy pseudo
757 /// instructions (but only if the Target is using them). It is responsible
758 /// for eliminating these instructions, replacing them with concrete
759 /// instructions. This method need only be implemented if using call frame
760 /// setup/destroy pseudo instructions.
763 eliminateCallFramePseudoInstr(MachineFunction &MF,
764 MachineBasicBlock &MBB,
765 MachineBasicBlock::iterator MI) const {
766 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
767 "eliminateCallFramePseudoInstr must be implemented if using"
768 " call frame setup/destroy pseudo instructions!");
769 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
773 /// saveScavengerRegister - Spill the register so it can be used by the
774 /// register scavenger. Return true if the register was spilled, false
775 /// otherwise. If this function does not spill the register, the scavenger
776 /// will instead spill it to the emergency spill slot.
778 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
779 MachineBasicBlock::iterator I,
780 MachineBasicBlock::iterator &UseMI,
781 const TargetRegisterClass *RC,
782 unsigned Reg) const {
786 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
787 /// frame indices from instructions which may use them. The instruction
788 /// referenced by the iterator contains an MO_FrameIndex operand which must be
789 /// eliminated by this method. This method may modify or replace the
790 /// specified instruction, as long as it keeps the iterator pointing at the
791 /// finished product. SPAdj is the SP adjustment due to call frame setup
793 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
794 int SPAdj, RegScavenger *RS=NULL) const = 0;
796 //===--------------------------------------------------------------------===//
797 /// Debug information queries.
799 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
800 /// number. Returns -1 if there is no equivalent value. The second
801 /// parameter allows targets to use different numberings for EH info and
803 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
805 /// getFrameRegister - This method should return the register used as a base
806 /// for values allocated in the current stack frame.
807 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
809 /// getRARegister - This method should return the register where the return
810 /// address can be found.
811 virtual unsigned getRARegister() const = 0;
815 // This is useful when building IndexedMaps keyed on virtual registers
816 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
817 unsigned operator()(unsigned Reg) const {
818 return TargetRegisterInfo::virtReg2Index(Reg);
822 /// getCommonSubClass - find the largest common subclass of A and B. Return NULL
823 /// if there is no common subclass.
824 const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A,
825 const TargetRegisterClass *B);
827 /// PrintReg - Helper class for printing registers on a raw_ostream.
828 /// Prints virtual and physical registers with or without a TRI instance.
831 /// %noreg - NoRegister
832 /// %vreg5 - a virtual register.
833 /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
834 /// %EAX - a physical register
835 /// %physreg17 - a physical register when no TRI instance given.
837 /// Usage: OS << PrintReg(Reg, TRI) << '\n';
840 const TargetRegisterInfo *TRI;
844 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0)
845 : TRI(tri), Reg(reg), SubIdx(subidx) {}
846 void print(raw_ostream&) const;
849 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
854 } // End llvm namespace