1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/CallingConv.h"
30 class MachineFunction;
32 template<class T> class SmallVectorImpl;
35 class TargetRegisterClass {
37 typedef const unsigned* iterator;
38 typedef const unsigned* const_iterator;
39 typedef const EVT* vt_iterator;
40 typedef const TargetRegisterClass* const * sc_iterator;
42 virtual void anchor();
43 const MCRegisterClass *MC;
44 const vt_iterator VTs;
45 const unsigned *SubClassMask;
46 const sc_iterator SuperClasses;
47 const sc_iterator SuperRegClasses;
49 TargetRegisterClass(const MCRegisterClass *MC, const EVT *vts,
50 const unsigned *subcm,
51 const TargetRegisterClass * const *supcs,
52 const TargetRegisterClass * const *superregcs)
53 : MC(MC), VTs(vts), SubClassMask(subcm), SuperClasses(supcs),
54 SuperRegClasses(superregcs) {}
56 virtual ~TargetRegisterClass() {} // Allow subclasses
58 /// getID() - Return the register class ID number.
60 unsigned getID() const { return MC->getID(); }
62 /// getName() - Return the register class name for debugging.
64 const char *getName() const { return MC->getName(); }
66 /// begin/end - Return all of the registers in this class.
68 iterator begin() const { return MC->begin(); }
69 iterator end() const { return MC->end(); }
71 /// getNumRegs - Return the number of registers in this class.
73 unsigned getNumRegs() const { return MC->getNumRegs(); }
75 /// getRegister - Return the specified register in the class.
77 unsigned getRegister(unsigned i) const {
78 return MC->getRegister(i);
81 /// contains - Return true if the specified register is included in this
82 /// register class. This does not include virtual registers.
83 bool contains(unsigned Reg) const {
84 return MC->contains(Reg);
87 /// contains - Return true if both registers are in this class.
88 bool contains(unsigned Reg1, unsigned Reg2) const {
89 return MC->contains(Reg1, Reg2);
92 /// getSize - Return the size of the register in bytes, which is also the size
93 /// of a stack slot allocated to hold a spilled copy of this register.
94 unsigned getSize() const { return MC->getSize(); }
96 /// getAlignment - Return the minimum required alignment for a register of
98 unsigned getAlignment() const { return MC->getAlignment(); }
100 /// getCopyCost - Return the cost of copying a value between two registers in
101 /// this class. A negative number means the register class is very expensive
102 /// to copy e.g. status flag register classes.
103 int getCopyCost() const { return MC->getCopyCost(); }
105 /// isAllocatable - Return true if this register class may be used to create
106 /// virtual registers.
107 bool isAllocatable() const { return MC->isAllocatable(); }
109 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
111 bool hasType(EVT vt) const {
112 for(int i = 0; VTs[i] != MVT::Other; ++i)
118 /// vt_begin / vt_end - Loop over all of the value types that can be
119 /// represented by values in this register class.
120 vt_iterator vt_begin() const {
124 vt_iterator vt_end() const {
126 while (*I != MVT::Other) ++I;
130 /// superregclasses_begin / superregclasses_end - Loop over all of
131 /// the superreg register classes of this register class.
132 sc_iterator superregclasses_begin() const {
133 return SuperRegClasses;
136 sc_iterator superregclasses_end() const {
137 sc_iterator I = SuperRegClasses;
138 while (*I != NULL) ++I;
142 /// hasSubClass - return true if the specified TargetRegisterClass
143 /// is a proper sub-class of this TargetRegisterClass.
144 bool hasSubClass(const TargetRegisterClass *RC) const {
145 return RC != this && hasSubClassEq(RC);
148 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
150 bool hasSubClassEq(const TargetRegisterClass *RC) const {
151 unsigned ID = RC->getID();
152 return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
155 /// hasSuperClass - return true if the specified TargetRegisterClass is a
156 /// proper super-class of this TargetRegisterClass.
157 bool hasSuperClass(const TargetRegisterClass *RC) const {
158 return RC->hasSubClass(this);
161 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this
163 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
164 return RC->hasSubClassEq(this);
167 /// getSubClassMask - Returns a bit vector of subclasses, including this one.
168 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
170 const unsigned *getSubClassMask() const {
174 /// getSuperClasses - Returns a NULL terminated list of super-classes. The
175 /// classes are ordered by ID which is also a topological ordering from large
176 /// to small classes. The list does NOT include the current class.
177 sc_iterator getSuperClasses() const {
181 /// isASubClass - return true if this TargetRegisterClass is a subset
182 /// class of at least one other TargetRegisterClass.
183 bool isASubClass() const {
184 return SuperClasses[0] != 0;
187 /// getRawAllocationOrder - Returns the preferred order for allocating
188 /// registers from this register class in MF. The raw order comes directly
189 /// from the .td file and may include reserved registers that are not
190 /// allocatable. Register allocators should also make sure to allocate
191 /// callee-saved registers only after all the volatiles are used. The
192 /// RegisterClassInfo class provides filtered allocation orders with
193 /// callee-saved registers moved to the end.
195 /// The MachineFunction argument can be used to tune the allocatable
196 /// registers based on the characteristics of the function, subtarget, or
199 /// By default, this method returns all registers in the class.
202 ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const {
203 return makeArrayRef(begin(), getNumRegs());
207 /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
208 /// registers. These are used by codegen, not by MC.
209 struct TargetRegisterInfoDesc {
210 unsigned CostPerUse; // Extra cost of instructions using register.
211 bool inAllocatableClass; // Register belongs to an allocatable regclass.
214 /// TargetRegisterInfo base class - We assume that the target defines a static
215 /// array of TargetRegisterDesc objects that represent all of the machine
216 /// registers that the target has. As such, we simply have to track a pointer
217 /// to this array so that we can turn register number into a register
220 class TargetRegisterInfo : public MCRegisterInfo {
222 typedef const TargetRegisterClass * const * regclass_iterator;
224 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
225 const char *const *SubRegIndexNames; // Names of subreg indexes.
226 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
229 TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
230 regclass_iterator RegClassBegin,
231 regclass_iterator RegClassEnd,
232 const char *const *subregindexnames);
233 virtual ~TargetRegisterInfo();
236 // Register numbers can represent physical registers, virtual registers, and
237 // sometimes stack slots. The unsigned values are divided into these ranges:
239 // 0 Not a register, can be used as a sentinel.
240 // [1;2^30) Physical registers assigned by TableGen.
241 // [2^30;2^31) Stack slots. (Rarely used.)
242 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
244 // Further sentinels can be allocated from the small negative integers.
245 // DenseMapInfo<unsigned> uses -1u and -2u.
247 /// isStackSlot - Sometimes it is useful the be able to store a non-negative
248 /// frame index in a variable that normally holds a register. isStackSlot()
249 /// returns true if Reg is in the range used for stack slots.
251 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
252 /// slots, so if a variable may contains a stack slot, always check
253 /// isStackSlot() first.
255 static bool isStackSlot(unsigned Reg) {
256 return int(Reg) >= (1 << 30);
259 /// stackSlot2Index - Compute the frame index from a register value
260 /// representing a stack slot.
261 static int stackSlot2Index(unsigned Reg) {
262 assert(isStackSlot(Reg) && "Not a stack slot");
263 return int(Reg - (1u << 30));
266 /// index2StackSlot - Convert a non-negative frame index to a stack slot
268 static unsigned index2StackSlot(int FI) {
269 assert(FI >= 0 && "Cannot hold a negative frame index.");
270 return FI + (1u << 30);
273 /// isPhysicalRegister - Return true if the specified register number is in
274 /// the physical register namespace.
275 static bool isPhysicalRegister(unsigned Reg) {
276 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
280 /// isVirtualRegister - Return true if the specified register number is in
281 /// the virtual register namespace.
282 static bool isVirtualRegister(unsigned Reg) {
283 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
287 /// virtReg2Index - Convert a virtual register number to a 0-based index.
288 /// The first virtual register in a function will get the index 0.
289 static unsigned virtReg2Index(unsigned Reg) {
290 assert(isVirtualRegister(Reg) && "Not a virtual register");
291 return Reg & ~(1u << 31);
294 /// index2VirtReg - Convert a 0-based index to a virtual register number.
295 /// This is the inverse operation of VirtReg2IndexFunctor below.
296 static unsigned index2VirtReg(unsigned Index) {
297 return Index | (1u << 31);
300 /// getMinimalPhysRegClass - Returns the Register Class of a physical
301 /// register of the given type, picking the most sub register class of
302 /// the right type that contains this physreg.
303 const TargetRegisterClass *
304 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
306 /// getAllocatableSet - Returns a bitset indexed by register number
307 /// indicating if a register is allocatable or not. If a register class is
308 /// specified, returns the subset for the class.
309 BitVector getAllocatableSet(const MachineFunction &MF,
310 const TargetRegisterClass *RC = NULL) const;
312 /// getCostPerUse - Return the additional cost of using this register instead
313 /// of other registers in its class.
314 unsigned getCostPerUse(unsigned RegNo) const {
315 return InfoDesc[RegNo].CostPerUse;
318 /// isInAllocatableClass - Return true if the register is in the allocation
319 /// of any register class.
320 bool isInAllocatableClass(unsigned RegNo) const {
321 return InfoDesc[RegNo].inAllocatableClass;
324 /// getSubRegIndexName - Return the human-readable symbolic target-specific
325 /// name for the specified SubRegIndex.
326 const char *getSubRegIndexName(unsigned SubIdx) const {
327 assert(SubIdx && "This is not a subregister index");
328 return SubRegIndexNames[SubIdx-1];
331 /// regsOverlap - Returns true if the two registers are equal or alias each
332 /// other. The registers may be virtual register.
333 bool regsOverlap(unsigned regA, unsigned regB) const {
334 if (regA == regB) return true;
335 if (isVirtualRegister(regA) || isVirtualRegister(regB))
337 for (const unsigned *regList = getOverlaps(regA)+1; *regList; ++regList) {
338 if (*regList == regB) return true;
343 /// isSubRegister - Returns true if regB is a sub-register of regA.
345 bool isSubRegister(unsigned regA, unsigned regB) const {
346 return isSuperRegister(regB, regA);
349 /// isSuperRegister - Returns true if regB is a super-register of regA.
351 bool isSuperRegister(unsigned regA, unsigned regB) const {
352 for (const unsigned *regList = getSuperRegisters(regA); *regList;++regList){
353 if (*regList == regB) return true;
358 /// getCalleeSavedRegs - Return a null-terminated list of all of the
359 /// callee saved registers on this target. The register should be in the
360 /// order of desired callee-save stack frame offset. The first register is
361 /// closest to the incoming stack pointer if stack grows down, and vice versa.
363 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
366 /// getCallPreservedMask - Return a mask of call-preserved registers for the
367 /// given calling convention on the current sub-target. The mask should
368 /// include all call-preserved aliases. This is used by the register
369 /// allocator to determine which registers can be live across a call.
371 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
372 /// A set bit indicates that all bits of the corresponding register are
373 /// preserved across the function call. The bit mask is expected to be
374 /// sub-register complete, i.e. if A is preserved, so are all its
377 /// Bits are numbered from the LSB, so the bit for physical register Reg can
378 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
380 /// A NULL pointer means that no register mask will be used, and call
381 /// instructions should use implicit-def operands to indicate call clobbered
384 virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const {
385 // The default mask clobbers everything. All targets should override.
389 /// getReservedRegs - Returns a bitset indexed by physical register number
390 /// indicating if a register is a special register that has particular uses
391 /// and should be considered unavailable at all times, e.g. SP, RA. This is
392 /// used by register scavenger to determine what registers are free.
393 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
395 /// getSubReg - Returns the physical register number of sub-register "Index"
396 /// for physical register RegNo. Return zero if the sub-register does not
398 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
400 /// getSubRegIndex - For a given register pair, return the sub-register index
401 /// if the second register is a sub-register of the first. Return zero
403 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0;
405 /// getMatchingSuperReg - Return a super-register of the specified register
406 /// Reg so its sub-register of index SubIdx is Reg.
407 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
408 const TargetRegisterClass *RC) const {
409 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
410 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
415 /// canCombineSubRegIndices - Given a register class and a list of
416 /// subregister indices, return true if it's possible to combine the
417 /// subregister indices into one that corresponds to a larger
418 /// subregister. Return the new subregister index by reference. Note the
419 /// new index may be zero if the given subregisters can be combined to
420 /// form the whole register.
421 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
422 SmallVectorImpl<unsigned> &SubIndices,
423 unsigned &NewSubIdx) const {
427 /// getMatchingSuperRegClass - Return a subclass of the specified register
428 /// class A so that each register in it has a sub-register of the
429 /// specified sub-register index which is in the specified register class B.
431 /// TableGen will synthesize missing A sub-classes.
432 virtual const TargetRegisterClass *
433 getMatchingSuperRegClass(const TargetRegisterClass *A,
434 const TargetRegisterClass *B, unsigned Idx) const =0;
436 /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that
437 /// supports the sub-register index Idx.
438 /// If no such sub-class exists, return NULL.
439 /// If all registers in RC already have an Idx sub-register, return RC.
441 /// TableGen generates a version of this function that is good enough in most
442 /// cases. Targets can override if they have constraints that TableGen
443 /// doesn't understand. For example, the x86 sub_8bit sub-register index is
444 /// supported by the full GR32 register class in 64-bit mode, but only by the
445 /// GR32_ABCD regiister class in 32-bit mode.
447 /// TableGen will synthesize missing RC sub-classes.
448 virtual const TargetRegisterClass *
449 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const =0;
451 /// composeSubRegIndices - Return the subregister index you get from composing
452 /// two subregister indices.
454 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
455 /// returns c. Note that composeSubRegIndices does not tell you about illegal
456 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
457 /// b, composeSubRegIndices doesn't tell you.
459 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
460 /// ssub_0:S0 - ssub_3:S3 subregs.
461 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
463 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const {
464 // This default implementation is correct for most targets.
468 //===--------------------------------------------------------------------===//
469 // Register Class Information
472 /// Register class iterators
474 regclass_iterator regclass_begin() const { return RegClassBegin; }
475 regclass_iterator regclass_end() const { return RegClassEnd; }
477 unsigned getNumRegClasses() const {
478 return (unsigned)(regclass_end()-regclass_begin());
481 /// getRegClass - Returns the register class associated with the enumeration
482 /// value. See class MCOperandInfo.
483 const TargetRegisterClass *getRegClass(unsigned i) const {
484 assert(i < getNumRegClasses() && "Register Class ID out of range");
485 return RegClassBegin[i];
488 /// getCommonSubClass - find the largest common subclass of A and B. Return
489 /// NULL if there is no common subclass.
490 const TargetRegisterClass *
491 getCommonSubClass(const TargetRegisterClass *A,
492 const TargetRegisterClass *B) const;
494 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
495 /// values. If a target supports multiple different pointer register classes,
496 /// kind specifies which one is indicated.
497 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
498 assert(0 && "Target didn't implement getPointerRegClass!");
499 return 0; // Must return a value in order to compile with VS 2005
502 /// getCrossCopyRegClass - Returns a legal register class to copy a register
503 /// in the specified class to or from. If it is possible to copy the register
504 /// directly without using a cross register class copy, return the specified
505 /// RC. Returns NULL if it is not possible to copy between a two registers of
506 /// the specified class.
507 virtual const TargetRegisterClass *
508 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
512 /// getLargestLegalSuperClass - Returns the largest super class of RC that is
513 /// legal to use in the current sub-target and has the same spill size.
514 /// The returned register class can be used to create virtual registers which
515 /// means that all its registers can be copied and spilled.
516 virtual const TargetRegisterClass*
517 getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
518 /// The default implementation is very conservative and doesn't allow the
519 /// register allocator to inflate register classes.
523 /// getRegPressureLimit - Return the register pressure "high water mark" for
524 /// the specific register class. The scheduler is in high register pressure
525 /// mode (for the specific register class) if it goes over the limit.
526 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
527 MachineFunction &MF) const {
531 /// getRawAllocationOrder - Returns the register allocation order for a
532 /// specified register class with a target-dependent hint. The returned list
533 /// may contain reserved registers that cannot be allocated.
535 /// Register allocators need only call this function to resolve
536 /// target-dependent hints, but it should work without hinting as well.
537 virtual ArrayRef<unsigned>
538 getRawAllocationOrder(const TargetRegisterClass *RC,
539 unsigned HintType, unsigned HintReg,
540 const MachineFunction &MF) const {
541 return RC->getRawAllocationOrder(MF);
544 /// ResolveRegAllocHint - Resolves the specified register allocation hint
545 /// to a physical register. Returns the physical register if it is successful.
546 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
547 const MachineFunction &MF) const {
548 if (Type == 0 && Reg && isPhysicalRegister(Reg))
553 /// avoidWriteAfterWrite - Return true if the register allocator should avoid
554 /// writing a register from RC in two consecutive instructions.
555 /// This can avoid pipeline stalls on certain architectures.
556 /// It does cause increased register pressure, though.
557 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
561 /// UpdateRegAllocHint - A callback to allow target a chance to update
562 /// register allocation hints when a register is "changed" (e.g. coalesced)
563 /// to another register. e.g. On ARM, some virtual registers should target
564 /// register pairs, if one of pair is coalesced to another register, the
565 /// allocation hint of the other half of the pair should be changed to point
566 /// to the new register.
567 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
568 MachineFunction &MF) const {
572 /// requiresRegisterScavenging - returns true if the target requires (and can
573 /// make use of) the register scavenger.
574 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
578 /// useFPForScavengingIndex - returns true if the target wants to use
579 /// frame pointer based accesses to spill to the scavenger emergency spill
581 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
585 /// requiresFrameIndexScavenging - returns true if the target requires post
586 /// PEI scavenging of registers for materializing frame index constants.
587 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
591 /// requiresVirtualBaseRegisters - Returns true if the target wants the
592 /// LocalStackAllocation pass to be run and virtual base registers
593 /// used for more efficient stack access.
594 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
598 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
599 /// the stack frame of the given function for the specified register. e.g. On
600 /// x86, if the frame register is required, the first fixed stack object is
601 /// reserved as its spill slot. This tells PEI not to create a new stack frame
602 /// object for the given register. It should be called only after
603 /// processFunctionBeforeCalleeSavedScan().
604 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
605 int &FrameIdx) const {
609 /// needsStackRealignment - true if storage within the function requires the
610 /// stack pointer to be aligned more than the normal calling convention calls
612 virtual bool needsStackRealignment(const MachineFunction &MF) const {
616 /// getFrameIndexInstrOffset - Get the offset from the referenced frame
617 /// index in the instruction, if there is one.
618 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
623 /// needsFrameBaseReg - Returns true if the instruction's frame index
624 /// reference would be better served by a base register other than FP
625 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
626 /// references it should create new base registers for.
627 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
631 /// materializeFrameBaseRegister - Insert defining instruction(s) for
632 /// BaseReg to be a pointer to FrameIdx before insertion point I.
633 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
634 unsigned BaseReg, int FrameIdx,
635 int64_t Offset) const {
636 assert(0 && "materializeFrameBaseRegister does not exist on this target");
639 /// resolveFrameIndex - Resolve a frame index operand of an instruction
640 /// to reference the indicated base register plus offset instead.
641 virtual void resolveFrameIndex(MachineBasicBlock::iterator I,
642 unsigned BaseReg, int64_t Offset) const {
643 assert(0 && "resolveFrameIndex does not exist on this target");
646 /// isFrameOffsetLegal - Determine whether a given offset immediate is
647 /// encodable to resolve a frame index.
648 virtual bool isFrameOffsetLegal(const MachineInstr *MI,
649 int64_t Offset) const {
650 assert(0 && "isFrameOffsetLegal does not exist on this target");
651 return false; // Must return a value in order to compile with VS 2005
654 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
655 /// code insertion to eliminate call frame setup and destroy pseudo
656 /// instructions (but only if the Target is using them). It is responsible
657 /// for eliminating these instructions, replacing them with concrete
658 /// instructions. This method need only be implemented if using call frame
659 /// setup/destroy pseudo instructions.
662 eliminateCallFramePseudoInstr(MachineFunction &MF,
663 MachineBasicBlock &MBB,
664 MachineBasicBlock::iterator MI) const {
665 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
669 /// saveScavengerRegister - Spill the register so it can be used by the
670 /// register scavenger. Return true if the register was spilled, false
671 /// otherwise. If this function does not spill the register, the scavenger
672 /// will instead spill it to the emergency spill slot.
674 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
675 MachineBasicBlock::iterator I,
676 MachineBasicBlock::iterator &UseMI,
677 const TargetRegisterClass *RC,
678 unsigned Reg) const {
682 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
683 /// frame indices from instructions which may use them. The instruction
684 /// referenced by the iterator contains an MO_FrameIndex operand which must be
685 /// eliminated by this method. This method may modify or replace the
686 /// specified instruction, as long as it keeps the iterator pointing at the
687 /// finished product. SPAdj is the SP adjustment due to call frame setup
689 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
690 int SPAdj, RegScavenger *RS=NULL) const = 0;
692 //===--------------------------------------------------------------------===//
693 /// Debug information queries.
695 /// getFrameRegister - This method should return the register used as a base
696 /// for values allocated in the current stack frame.
697 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
699 /// getCompactUnwindRegNum - This function maps the register to the number for
700 /// compact unwind encoding. Return -1 if the register isn't valid.
701 virtual int getCompactUnwindRegNum(unsigned, bool) const {
707 // This is useful when building IndexedMaps keyed on virtual registers
708 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
709 unsigned operator()(unsigned Reg) const {
710 return TargetRegisterInfo::virtReg2Index(Reg);
714 /// PrintReg - Helper class for printing registers on a raw_ostream.
715 /// Prints virtual and physical registers with or without a TRI instance.
718 /// %noreg - NoRegister
719 /// %vreg5 - a virtual register.
720 /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
721 /// %EAX - a physical register
722 /// %physreg17 - a physical register when no TRI instance given.
724 /// Usage: OS << PrintReg(Reg, TRI) << '\n';
727 const TargetRegisterInfo *TRI;
731 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0)
732 : TRI(tri), Reg(reg), SubIdx(subidx) {}
733 void print(raw_ostream&) const;
736 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
741 } // End llvm namespace