1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/ADT/ArrayRef.h"
29 class MachineFunction;
31 template<class T> class SmallVectorImpl;
34 class TargetRegisterClass {
36 typedef const unsigned* iterator;
37 typedef const unsigned* const_iterator;
38 typedef const EVT* vt_iterator;
39 typedef const TargetRegisterClass* const * sc_iterator;
41 const MCRegisterClass *MC;
42 const vt_iterator VTs;
43 const unsigned *SubClassMask;
44 const sc_iterator SuperClasses;
45 const sc_iterator SuperRegClasses;
47 TargetRegisterClass(const MCRegisterClass *MC, const EVT *vts,
48 const unsigned *subcm,
49 const TargetRegisterClass * const *supcs,
50 const TargetRegisterClass * const *superregcs)
51 : MC(MC), VTs(vts), SubClassMask(subcm), SuperClasses(supcs),
52 SuperRegClasses(superregcs) {}
54 virtual ~TargetRegisterClass() {} // Allow subclasses
56 /// getID() - Return the register class ID number.
58 unsigned getID() const { return MC->getID(); }
60 /// getName() - Return the register class name for debugging.
62 const char *getName() const { return MC->getName(); }
64 /// begin/end - Return all of the registers in this class.
66 iterator begin() const { return MC->begin(); }
67 iterator end() const { return MC->end(); }
69 /// getNumRegs - Return the number of registers in this class.
71 unsigned getNumRegs() const { return MC->getNumRegs(); }
73 /// getRegister - Return the specified register in the class.
75 unsigned getRegister(unsigned i) const {
76 return MC->getRegister(i);
79 /// contains - Return true if the specified register is included in this
80 /// register class. This does not include virtual registers.
81 bool contains(unsigned Reg) const {
82 return MC->contains(Reg);
85 /// contains - Return true if both registers are in this class.
86 bool contains(unsigned Reg1, unsigned Reg2) const {
87 return MC->contains(Reg1, Reg2);
90 /// getSize - Return the size of the register in bytes, which is also the size
91 /// of a stack slot allocated to hold a spilled copy of this register.
92 unsigned getSize() const { return MC->getSize(); }
94 /// getAlignment - Return the minimum required alignment for a register of
96 unsigned getAlignment() const { return MC->getAlignment(); }
98 /// getCopyCost - Return the cost of copying a value between two registers in
99 /// this class. A negative number means the register class is very expensive
100 /// to copy e.g. status flag register classes.
101 int getCopyCost() const { return MC->getCopyCost(); }
103 /// isAllocatable - Return true if this register class may be used to create
104 /// virtual registers.
105 bool isAllocatable() const { return MC->isAllocatable(); }
107 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
109 bool hasType(EVT vt) const {
110 for(int i = 0; VTs[i] != MVT::Other; ++i)
116 /// vt_begin / vt_end - Loop over all of the value types that can be
117 /// represented by values in this register class.
118 vt_iterator vt_begin() const {
122 vt_iterator vt_end() const {
124 while (*I != MVT::Other) ++I;
128 /// superregclasses_begin / superregclasses_end - Loop over all of
129 /// the superreg register classes of this register class.
130 sc_iterator superregclasses_begin() const {
131 return SuperRegClasses;
134 sc_iterator superregclasses_end() const {
135 sc_iterator I = SuperRegClasses;
136 while (*I != NULL) ++I;
140 /// hasSubClass - return true if the specified TargetRegisterClass
141 /// is a proper sub-class of this TargetRegisterClass.
142 bool hasSubClass(const TargetRegisterClass *RC) const {
143 return RC != this && hasSubClassEq(RC);
146 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
148 bool hasSubClassEq(const TargetRegisterClass *RC) const {
149 unsigned ID = RC->getID();
150 return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
153 /// hasSuperClass - return true if the specified TargetRegisterClass is a
154 /// proper super-class of this TargetRegisterClass.
155 bool hasSuperClass(const TargetRegisterClass *RC) const {
156 return RC->hasSubClass(this);
159 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this
161 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
162 return RC->hasSubClassEq(this);
165 /// getSubClassMask - Returns a bit vector of subclasses, including this one.
166 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
168 const unsigned *getSubClassMask() const {
172 /// getSuperClasses - Returns a NULL terminated list of super-classes. The
173 /// classes are ordered by ID which is also a topological ordering from large
174 /// to small classes. The list does NOT include the current class.
175 sc_iterator getSuperClasses() const {
179 /// isASubClass - return true if this TargetRegisterClass is a subset
180 /// class of at least one other TargetRegisterClass.
181 bool isASubClass() const {
182 return SuperClasses[0] != 0;
185 /// getRawAllocationOrder - Returns the preferred order for allocating
186 /// registers from this register class in MF. The raw order comes directly
187 /// from the .td file and may include reserved registers that are not
188 /// allocatable. Register allocators should also make sure to allocate
189 /// callee-saved registers only after all the volatiles are used. The
190 /// RegisterClassInfo class provides filtered allocation orders with
191 /// callee-saved registers moved to the end.
193 /// The MachineFunction argument can be used to tune the allocatable
194 /// registers based on the characteristics of the function, subtarget, or
197 /// By default, this method returns all registers in the class.
200 ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const {
201 return makeArrayRef(begin(), getNumRegs());
205 /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
206 /// registers. These are used by codegen, not by MC.
207 struct TargetRegisterInfoDesc {
208 unsigned CostPerUse; // Extra cost of instructions using register.
209 bool inAllocatableClass; // Register belongs to an allocatable regclass.
212 /// TargetRegisterInfo base class - We assume that the target defines a static
213 /// array of TargetRegisterDesc objects that represent all of the machine
214 /// registers that the target has. As such, we simply have to track a pointer
215 /// to this array so that we can turn register number into a register
218 class TargetRegisterInfo : public MCRegisterInfo {
220 typedef const TargetRegisterClass * const * regclass_iterator;
222 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
223 const char *const *SubRegIndexNames; // Names of subreg indexes.
224 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
227 TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
228 regclass_iterator RegClassBegin,
229 regclass_iterator RegClassEnd,
230 const char *const *subregindexnames);
231 virtual ~TargetRegisterInfo();
234 // Register numbers can represent physical registers, virtual registers, and
235 // sometimes stack slots. The unsigned values are divided into these ranges:
237 // 0 Not a register, can be used as a sentinel.
238 // [1;2^30) Physical registers assigned by TableGen.
239 // [2^30;2^31) Stack slots. (Rarely used.)
240 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
242 // Further sentinels can be allocated from the small negative integers.
243 // DenseMapInfo<unsigned> uses -1u and -2u.
245 /// isStackSlot - Sometimes it is useful the be able to store a non-negative
246 /// frame index in a variable that normally holds a register. isStackSlot()
247 /// returns true if Reg is in the range used for stack slots.
249 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
250 /// slots, so if a variable may contains a stack slot, always check
251 /// isStackSlot() first.
253 static bool isStackSlot(unsigned Reg) {
254 return int(Reg) >= (1 << 30);
257 /// stackSlot2Index - Compute the frame index from a register value
258 /// representing a stack slot.
259 static int stackSlot2Index(unsigned Reg) {
260 assert(isStackSlot(Reg) && "Not a stack slot");
261 return int(Reg - (1u << 30));
264 /// index2StackSlot - Convert a non-negative frame index to a stack slot
266 static unsigned index2StackSlot(int FI) {
267 assert(FI >= 0 && "Cannot hold a negative frame index.");
268 return FI + (1u << 30);
271 /// isPhysicalRegister - Return true if the specified register number is in
272 /// the physical register namespace.
273 static bool isPhysicalRegister(unsigned Reg) {
274 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
278 /// isVirtualRegister - Return true if the specified register number is in
279 /// the virtual register namespace.
280 static bool isVirtualRegister(unsigned Reg) {
281 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
285 /// virtReg2Index - Convert a virtual register number to a 0-based index.
286 /// The first virtual register in a function will get the index 0.
287 static unsigned virtReg2Index(unsigned Reg) {
288 assert(isVirtualRegister(Reg) && "Not a virtual register");
289 return Reg & ~(1u << 31);
292 /// index2VirtReg - Convert a 0-based index to a virtual register number.
293 /// This is the inverse operation of VirtReg2IndexFunctor below.
294 static unsigned index2VirtReg(unsigned Index) {
295 return Index | (1u << 31);
298 /// getMinimalPhysRegClass - Returns the Register Class of a physical
299 /// register of the given type, picking the most sub register class of
300 /// the right type that contains this physreg.
301 const TargetRegisterClass *
302 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
304 /// getAllocatableSet - Returns a bitset indexed by register number
305 /// indicating if a register is allocatable or not. If a register class is
306 /// specified, returns the subset for the class.
307 BitVector getAllocatableSet(const MachineFunction &MF,
308 const TargetRegisterClass *RC = NULL) const;
310 /// getCostPerUse - Return the additional cost of using this register instead
311 /// of other registers in its class.
312 unsigned getCostPerUse(unsigned RegNo) const {
313 return InfoDesc[RegNo].CostPerUse;
316 /// isInAllocatableClass - Return true if the register is in the allocation
317 /// of any register class.
318 bool isInAllocatableClass(unsigned RegNo) const {
319 return InfoDesc[RegNo].inAllocatableClass;
322 /// getSubRegIndexName - Return the human-readable symbolic target-specific
323 /// name for the specified SubRegIndex.
324 const char *getSubRegIndexName(unsigned SubIdx) const {
325 assert(SubIdx && "This is not a subregister index");
326 return SubRegIndexNames[SubIdx-1];
329 /// regsOverlap - Returns true if the two registers are equal or alias each
330 /// other. The registers may be virtual register.
331 bool regsOverlap(unsigned regA, unsigned regB) const {
332 if (regA == regB) return true;
333 if (isVirtualRegister(regA) || isVirtualRegister(regB))
335 for (const unsigned *regList = getOverlaps(regA)+1; *regList; ++regList) {
336 if (*regList == regB) return true;
341 /// isSubRegister - Returns true if regB is a sub-register of regA.
343 bool isSubRegister(unsigned regA, unsigned regB) const {
344 return isSuperRegister(regB, regA);
347 /// isSuperRegister - Returns true if regB is a super-register of regA.
349 bool isSuperRegister(unsigned regA, unsigned regB) const {
350 for (const unsigned *regList = getSuperRegisters(regA); *regList;++regList){
351 if (*regList == regB) return true;
356 /// getCalleeSavedRegs - Return a null-terminated list of all of the
357 /// callee saved registers on this target. The register should be in the
358 /// order of desired callee-save stack frame offset. The first register is
359 /// closed to the incoming stack pointer if stack grows down, and vice versa.
360 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
364 /// getReservedRegs - Returns a bitset indexed by physical register number
365 /// indicating if a register is a special register that has particular uses
366 /// and should be considered unavailable at all times, e.g. SP, RA. This is
367 /// used by register scavenger to determine what registers are free.
368 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
370 /// getSubReg - Returns the physical register number of sub-register "Index"
371 /// for physical register RegNo. Return zero if the sub-register does not
373 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
375 /// getSubRegIndex - For a given register pair, return the sub-register index
376 /// if the second register is a sub-register of the first. Return zero
378 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0;
380 /// getMatchingSuperReg - Return a super-register of the specified register
381 /// Reg so its sub-register of index SubIdx is Reg.
382 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
383 const TargetRegisterClass *RC) const {
384 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
385 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
390 /// canCombineSubRegIndices - Given a register class and a list of
391 /// subregister indices, return true if it's possible to combine the
392 /// subregister indices into one that corresponds to a larger
393 /// subregister. Return the new subregister index by reference. Note the
394 /// new index may be zero if the given subregisters can be combined to
395 /// form the whole register.
396 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
397 SmallVectorImpl<unsigned> &SubIndices,
398 unsigned &NewSubIdx) const {
402 /// getMatchingSuperRegClass - Return a subclass of the specified register
403 /// class A so that each register in it has a sub-register of the
404 /// specified sub-register index which is in the specified register class B.
405 virtual const TargetRegisterClass *
406 getMatchingSuperRegClass(const TargetRegisterClass *A,
407 const TargetRegisterClass *B, unsigned Idx) const {
411 /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that
412 /// supports the sub-register index Idx.
413 /// If no such sub-class exists, return NULL.
414 /// If all registers in RC already have an Idx sub-register, return RC.
416 /// TableGen generates a version of this function that is good enough in most
417 /// cases. Targets can override if they have constraints that TableGen
418 /// doesn't understand. For example, the x86 sub_8bit sub-register index is
419 /// supported by the full GR32 register class in 64-bit mode, but only by the
420 /// GR32_ABCD regiister class in 32-bit mode.
422 virtual const TargetRegisterClass *
423 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const =0;
425 /// composeSubRegIndices - Return the subregister index you get from composing
426 /// two subregister indices.
428 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
429 /// returns c. Note that composeSubRegIndices does not tell you about illegal
430 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
431 /// b, composeSubRegIndices doesn't tell you.
433 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
434 /// ssub_0:S0 - ssub_3:S3 subregs.
435 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
437 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const {
438 // This default implementation is correct for most targets.
442 //===--------------------------------------------------------------------===//
443 // Register Class Information
446 /// Register class iterators
448 regclass_iterator regclass_begin() const { return RegClassBegin; }
449 regclass_iterator regclass_end() const { return RegClassEnd; }
451 unsigned getNumRegClasses() const {
452 return (unsigned)(regclass_end()-regclass_begin());
455 /// getRegClass - Returns the register class associated with the enumeration
456 /// value. See class MCOperandInfo.
457 const TargetRegisterClass *getRegClass(unsigned i) const {
458 assert(i < getNumRegClasses() && "Register Class ID out of range");
459 return RegClassBegin[i];
462 /// getCommonSubClass - find the largest common subclass of A and B. Return
463 /// NULL if there is no common subclass.
464 const TargetRegisterClass *
465 getCommonSubClass(const TargetRegisterClass *A,
466 const TargetRegisterClass *B) const;
468 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
469 /// values. If a target supports multiple different pointer register classes,
470 /// kind specifies which one is indicated.
471 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
472 assert(0 && "Target didn't implement getPointerRegClass!");
473 return 0; // Must return a value in order to compile with VS 2005
476 /// getCrossCopyRegClass - Returns a legal register class to copy a register
477 /// in the specified class to or from. If it is possible to copy the register
478 /// directly without using a cross register class copy, return the specified
479 /// RC. Returns NULL if it is not possible to copy between a two registers of
480 /// the specified class.
481 virtual const TargetRegisterClass *
482 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
486 /// getLargestLegalSuperClass - Returns the largest super class of RC that is
487 /// legal to use in the current sub-target and has the same spill size.
488 /// The returned register class can be used to create virtual registers which
489 /// means that all its registers can be copied and spilled.
490 virtual const TargetRegisterClass*
491 getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
492 /// The default implementation is very conservative and doesn't allow the
493 /// register allocator to inflate register classes.
497 /// getRegPressureLimit - Return the register pressure "high water mark" for
498 /// the specific register class. The scheduler is in high register pressure
499 /// mode (for the specific register class) if it goes over the limit.
500 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
501 MachineFunction &MF) const {
505 /// getRawAllocationOrder - Returns the register allocation order for a
506 /// specified register class with a target-dependent hint. The returned list
507 /// may contain reserved registers that cannot be allocated.
509 /// Register allocators need only call this function to resolve
510 /// target-dependent hints, but it should work without hinting as well.
511 virtual ArrayRef<unsigned>
512 getRawAllocationOrder(const TargetRegisterClass *RC,
513 unsigned HintType, unsigned HintReg,
514 const MachineFunction &MF) const {
515 return RC->getRawAllocationOrder(MF);
518 /// ResolveRegAllocHint - Resolves the specified register allocation hint
519 /// to a physical register. Returns the physical register if it is successful.
520 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
521 const MachineFunction &MF) const {
522 if (Type == 0 && Reg && isPhysicalRegister(Reg))
527 /// avoidWriteAfterWrite - Return true if the register allocator should avoid
528 /// writing a register from RC in two consecutive instructions.
529 /// This can avoid pipeline stalls on certain architectures.
530 /// It does cause increased register pressure, though.
531 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
535 /// UpdateRegAllocHint - A callback to allow target a chance to update
536 /// register allocation hints when a register is "changed" (e.g. coalesced)
537 /// to another register. e.g. On ARM, some virtual registers should target
538 /// register pairs, if one of pair is coalesced to another register, the
539 /// allocation hint of the other half of the pair should be changed to point
540 /// to the new register.
541 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
542 MachineFunction &MF) const {
546 /// requiresRegisterScavenging - returns true if the target requires (and can
547 /// make use of) the register scavenger.
548 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
552 /// useFPForScavengingIndex - returns true if the target wants to use
553 /// frame pointer based accesses to spill to the scavenger emergency spill
555 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
559 /// requiresFrameIndexScavenging - returns true if the target requires post
560 /// PEI scavenging of registers for materializing frame index constants.
561 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
565 /// requiresVirtualBaseRegisters - Returns true if the target wants the
566 /// LocalStackAllocation pass to be run and virtual base registers
567 /// used for more efficient stack access.
568 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
572 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
573 /// the stack frame of the given function for the specified register. e.g. On
574 /// x86, if the frame register is required, the first fixed stack object is
575 /// reserved as its spill slot. This tells PEI not to create a new stack frame
576 /// object for the given register. It should be called only after
577 /// processFunctionBeforeCalleeSavedScan().
578 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
579 int &FrameIdx) const {
583 /// needsStackRealignment - true if storage within the function requires the
584 /// stack pointer to be aligned more than the normal calling convention calls
586 virtual bool needsStackRealignment(const MachineFunction &MF) const {
590 /// getFrameIndexInstrOffset - Get the offset from the referenced frame
591 /// index in the instruction, if there is one.
592 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
597 /// needsFrameBaseReg - Returns true if the instruction's frame index
598 /// reference would be better served by a base register other than FP
599 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
600 /// references it should create new base registers for.
601 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
605 /// materializeFrameBaseRegister - Insert defining instruction(s) for
606 /// BaseReg to be a pointer to FrameIdx before insertion point I.
607 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
608 unsigned BaseReg, int FrameIdx,
609 int64_t Offset) const {
610 assert(0 && "materializeFrameBaseRegister does not exist on this target");
613 /// resolveFrameIndex - Resolve a frame index operand of an instruction
614 /// to reference the indicated base register plus offset instead.
615 virtual void resolveFrameIndex(MachineBasicBlock::iterator I,
616 unsigned BaseReg, int64_t Offset) const {
617 assert(0 && "resolveFrameIndex does not exist on this target");
620 /// isFrameOffsetLegal - Determine whether a given offset immediate is
621 /// encodable to resolve a frame index.
622 virtual bool isFrameOffsetLegal(const MachineInstr *MI,
623 int64_t Offset) const {
624 assert(0 && "isFrameOffsetLegal does not exist on this target");
625 return false; // Must return a value in order to compile with VS 2005
628 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
629 /// code insertion to eliminate call frame setup and destroy pseudo
630 /// instructions (but only if the Target is using them). It is responsible
631 /// for eliminating these instructions, replacing them with concrete
632 /// instructions. This method need only be implemented if using call frame
633 /// setup/destroy pseudo instructions.
636 eliminateCallFramePseudoInstr(MachineFunction &MF,
637 MachineBasicBlock &MBB,
638 MachineBasicBlock::iterator MI) const {
639 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
643 /// saveScavengerRegister - Spill the register so it can be used by the
644 /// register scavenger. Return true if the register was spilled, false
645 /// otherwise. If this function does not spill the register, the scavenger
646 /// will instead spill it to the emergency spill slot.
648 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
649 MachineBasicBlock::iterator I,
650 MachineBasicBlock::iterator &UseMI,
651 const TargetRegisterClass *RC,
652 unsigned Reg) const {
656 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
657 /// frame indices from instructions which may use them. The instruction
658 /// referenced by the iterator contains an MO_FrameIndex operand which must be
659 /// eliminated by this method. This method may modify or replace the
660 /// specified instruction, as long as it keeps the iterator pointing at the
661 /// finished product. SPAdj is the SP adjustment due to call frame setup
663 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
664 int SPAdj, RegScavenger *RS=NULL) const = 0;
666 //===--------------------------------------------------------------------===//
667 /// Debug information queries.
669 /// getFrameRegister - This method should return the register used as a base
670 /// for values allocated in the current stack frame.
671 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
673 /// getCompactUnwindRegNum - This function maps the register to the number for
674 /// compact unwind encoding. Return -1 if the register isn't valid.
675 virtual int getCompactUnwindRegNum(unsigned, bool) const {
681 // This is useful when building IndexedMaps keyed on virtual registers
682 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
683 unsigned operator()(unsigned Reg) const {
684 return TargetRegisterInfo::virtReg2Index(Reg);
688 /// PrintReg - Helper class for printing registers on a raw_ostream.
689 /// Prints virtual and physical registers with or without a TRI instance.
692 /// %noreg - NoRegister
693 /// %vreg5 - a virtual register.
694 /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
695 /// %EAX - a physical register
696 /// %physreg17 - a physical register when no TRI instance given.
698 /// Usage: OS << PrintReg(Reg, TRI) << '\n';
701 const TargetRegisterInfo *TRI;
705 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0)
706 : TRI(tri), Reg(reg), SubIdx(subidx) {}
707 void print(raw_ostream&) const;
710 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
715 } // End llvm namespace