1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/ADT/DenseSet.h"
28 class MachineFunction;
32 /// TargetRegisterDesc - This record contains all of the information known about
33 /// a particular register. The AliasSet field (if not null) contains a pointer
34 /// to a Zero terminated array of registers that this register aliases. This is
35 /// needed for architectures like X86 which have AL alias AX alias EAX.
36 /// Registers that this does not apply to simply should set this to null.
37 /// The SubRegs field is a zero terminated array of registers that are
38 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
39 /// The SuperRegs field is a zero terminated array of registers that are
40 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
43 struct TargetRegisterDesc {
44 const char *Name; // Printable name for the reg (for debugging)
45 const unsigned *AliasSet; // Register Alias Set, described above
46 const unsigned *SubRegs; // Sub-register set, described above
47 const unsigned *SuperRegs; // Super-register set, described above
50 class TargetRegisterClass {
52 typedef const unsigned* iterator;
53 typedef const unsigned* const_iterator;
55 typedef const EVT* vt_iterator;
56 typedef const TargetRegisterClass* const * sc_iterator;
60 const vt_iterator VTs;
61 const sc_iterator SubClasses;
62 const sc_iterator SuperClasses;
63 const sc_iterator SubRegClasses;
64 const sc_iterator SuperRegClasses;
65 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
67 const iterator RegsBegin, RegsEnd;
68 DenseSet<unsigned> RegSet;
70 TargetRegisterClass(unsigned id,
73 const TargetRegisterClass * const *subcs,
74 const TargetRegisterClass * const *supcs,
75 const TargetRegisterClass * const *subregcs,
76 const TargetRegisterClass * const *superregcs,
77 unsigned RS, unsigned Al, int CC,
78 iterator RB, iterator RE)
79 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
80 SubRegClasses(subregcs), SuperRegClasses(superregcs),
81 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {
82 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
85 virtual ~TargetRegisterClass() {} // Allow subclasses
87 /// getID() - Return the register class ID number.
89 unsigned getID() const { return ID; }
91 /// getName() - Return the register class name for debugging.
93 const char *getName() const { return Name; }
95 /// begin/end - Return all of the registers in this class.
97 iterator begin() const { return RegsBegin; }
98 iterator end() const { return RegsEnd; }
100 /// getNumRegs - Return the number of registers in this class.
102 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
104 /// getRegister - Return the specified register in the class.
106 unsigned getRegister(unsigned i) const {
107 assert(i < getNumRegs() && "Register number out of range!");
111 /// contains - Return true if the specified register is included in this
113 bool contains(unsigned Reg) const {
114 return RegSet.count(Reg);
117 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
119 bool hasType(EVT vt) const {
120 for(int i = 0; VTs[i].getSimpleVT().SimpleTy != MVT::Other; ++i)
126 /// vt_begin / vt_end - Loop over all of the value types that can be
127 /// represented by values in this register class.
128 vt_iterator vt_begin() const {
132 vt_iterator vt_end() const {
134 while (I->getSimpleVT().SimpleTy != MVT::Other) ++I;
138 /// subregclasses_begin / subregclasses_end - Loop over all of
139 /// the subreg register classes of this register class.
140 sc_iterator subregclasses_begin() const {
141 return SubRegClasses;
144 sc_iterator subregclasses_end() const {
145 sc_iterator I = SubRegClasses;
146 while (*I != NULL) ++I;
150 /// getSubRegisterRegClass - Return the register class of subregisters with
151 /// index SubIdx, or NULL if no such class exists.
152 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
153 assert(SubIdx>0 && "Invalid subregister index");
154 for (unsigned s = 0; s != SubIdx-1; ++s)
155 if (!SubRegClasses[s])
157 return SubRegClasses[SubIdx-1];
160 /// superregclasses_begin / superregclasses_end - Loop over all of
161 /// the superreg register classes of this register class.
162 sc_iterator superregclasses_begin() const {
163 return SuperRegClasses;
166 sc_iterator superregclasses_end() const {
167 sc_iterator I = SuperRegClasses;
168 while (*I != NULL) ++I;
172 /// hasSubClass - return true if the the specified TargetRegisterClass
173 /// is a proper subset of this TargetRegisterClass.
174 bool hasSubClass(const TargetRegisterClass *cs) const {
175 for (int i = 0; SubClasses[i] != NULL; ++i)
176 if (SubClasses[i] == cs)
181 /// subclasses_begin / subclasses_end - Loop over all of the classes
182 /// that are proper subsets of this register class.
183 sc_iterator subclasses_begin() const {
187 sc_iterator subclasses_end() const {
188 sc_iterator I = SubClasses;
189 while (*I != NULL) ++I;
193 /// hasSuperClass - return true if the specified TargetRegisterClass is a
194 /// proper superset of this TargetRegisterClass.
195 bool hasSuperClass(const TargetRegisterClass *cs) const {
196 for (int i = 0; SuperClasses[i] != NULL; ++i)
197 if (SuperClasses[i] == cs)
202 /// superclasses_begin / superclasses_end - Loop over all of the classes
203 /// that are proper supersets of this register class.
204 sc_iterator superclasses_begin() const {
208 sc_iterator superclasses_end() const {
209 sc_iterator I = SuperClasses;
210 while (*I != NULL) ++I;
214 /// isASubClass - return true if this TargetRegisterClass is a subset
215 /// class of at least one other TargetRegisterClass.
216 bool isASubClass() const {
217 return SuperClasses[0] != 0;
220 /// allocation_order_begin/end - These methods define a range of registers
221 /// which specify the registers in this class that are valid to register
222 /// allocate, and the preferred order to allocate them in. For example,
223 /// callee saved registers should be at the end of the list, because it is
224 /// cheaper to allocate caller saved registers.
226 /// These methods take a MachineFunction argument, which can be used to tune
227 /// the allocatable registers based on the characteristics of the function.
228 /// One simple example is that the frame pointer register can be used if
229 /// frame-pointer-elimination is performed.
231 /// By default, these methods return all registers in the class.
233 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
236 virtual iterator allocation_order_end(const MachineFunction &MF) const {
240 /// getSize - Return the size of the register in bytes, which is also the size
241 /// of a stack slot allocated to hold a spilled copy of this register.
242 unsigned getSize() const { return RegSize; }
244 /// getAlignment - Return the minimum required alignment for a register of
246 unsigned getAlignment() const { return Alignment; }
248 /// getCopyCost - Return the cost of copying a value between two registers in
249 /// this class. A negative number means the register class is very expensive
250 /// to copy e.g. status flag register classes.
251 int getCopyCost() const { return CopyCost; }
255 /// TargetRegisterInfo base class - We assume that the target defines a static
256 /// array of TargetRegisterDesc objects that represent all of the machine
257 /// registers that the target has. As such, we simply have to track a pointer
258 /// to this array so that we can turn register number into a register
261 class TargetRegisterInfo {
263 const unsigned* SubregHash;
264 const unsigned SubregHashSize;
265 const unsigned* SuperregHash;
266 const unsigned SuperregHashSize;
267 const unsigned* AliasesHash;
268 const unsigned AliasesHashSize;
270 typedef const TargetRegisterClass * const * regclass_iterator;
272 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
273 unsigned NumRegs; // Number of entries in the array
275 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
277 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
279 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
280 regclass_iterator RegClassBegin,
281 regclass_iterator RegClassEnd,
282 int CallFrameSetupOpcode = -1,
283 int CallFrameDestroyOpcode = -1,
284 const unsigned* subregs = 0,
285 const unsigned subregsize = 0,
286 const unsigned* superregs = 0,
287 const unsigned superregsize = 0,
288 const unsigned* aliases = 0,
289 const unsigned aliasessize = 0);
290 virtual ~TargetRegisterInfo();
293 enum { // Define some target independent constants
294 /// NoRegister - This physical register is not a real target register. It
295 /// is useful as a sentinal.
298 /// FirstVirtualRegister - This is the first register number that is
299 /// considered to be a 'virtual' register, which is part of the SSA
300 /// namespace. This must be the same for all targets, which means that each
301 /// target is limited to 1024 registers.
302 FirstVirtualRegister = 1024
305 /// isPhysicalRegister - Return true if the specified register number is in
306 /// the physical register namespace.
307 static bool isPhysicalRegister(unsigned Reg) {
308 assert(Reg && "this is not a register!");
309 return Reg < FirstVirtualRegister;
312 /// isVirtualRegister - Return true if the specified register number is in
313 /// the virtual register namespace.
314 static bool isVirtualRegister(unsigned Reg) {
315 assert(Reg && "this is not a register!");
316 return Reg >= FirstVirtualRegister;
319 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
320 /// register of the given type. If type is EVT::Other, then just return any
321 /// register class the register belongs to.
322 virtual const TargetRegisterClass *
323 getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const;
325 /// getAllocatableSet - Returns a bitset indexed by register number
326 /// indicating if a register is allocatable or not. If a register class is
327 /// specified, returns the subset for the class.
328 BitVector getAllocatableSet(MachineFunction &MF,
329 const TargetRegisterClass *RC = NULL) const;
331 const TargetRegisterDesc &operator[](unsigned RegNo) const {
332 assert(RegNo < NumRegs &&
333 "Attempting to access record for invalid register number!");
337 /// Provide a get method, equivalent to [], but more useful if we have a
338 /// pointer to this object.
340 const TargetRegisterDesc &get(unsigned RegNo) const {
341 return operator[](RegNo);
344 /// getAliasSet - Return the set of registers aliased by the specified
345 /// register, or a null list of there are none. The list returned is zero
348 const unsigned *getAliasSet(unsigned RegNo) const {
349 return get(RegNo).AliasSet;
352 /// getSubRegisters - Return the list of registers that are sub-registers of
353 /// the specified register, or a null list of there are none. The list
354 /// returned is zero terminated and sorted according to super-sub register
355 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
357 const unsigned *getSubRegisters(unsigned RegNo) const {
358 return get(RegNo).SubRegs;
361 /// getSuperRegisters - Return the list of registers that are super-registers
362 /// of the specified register, or a null list of there are none. The list
363 /// returned is zero terminated and sorted according to super-sub register
364 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
366 const unsigned *getSuperRegisters(unsigned RegNo) const {
367 return get(RegNo).SuperRegs;
370 /// getName - Return the human-readable symbolic target-specific name for the
371 /// specified physical register.
372 const char *getName(unsigned RegNo) const {
373 return get(RegNo).Name;
376 /// getNumRegs - Return the number of registers this target has (useful for
377 /// sizing arrays holding per register information)
378 unsigned getNumRegs() const {
382 /// regsOverlap - Returns true if the two registers are equal or alias each
383 /// other. The registers may be virtual register.
384 bool regsOverlap(unsigned regA, unsigned regB) const {
388 if (isVirtualRegister(regA) || isVirtualRegister(regB))
391 // regA and regB are distinct physical registers. Do they alias?
392 size_t index = (regA + regB * 37) & (AliasesHashSize-1);
393 unsigned ProbeAmt = 0;
394 while (AliasesHash[index*2] != 0 &&
395 AliasesHash[index*2+1] != 0) {
396 if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB)
399 index = (index + ProbeAmt) & (AliasesHashSize-1);
406 /// isSubRegister - Returns true if regB is a sub-register of regA.
408 bool isSubRegister(unsigned regA, unsigned regB) const {
409 // SubregHash is a simple quadratically probed hash table.
410 size_t index = (regA + regB * 37) & (SubregHashSize-1);
411 unsigned ProbeAmt = 2;
412 while (SubregHash[index*2] != 0 &&
413 SubregHash[index*2+1] != 0) {
414 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
417 index = (index + ProbeAmt) & (SubregHashSize-1);
424 /// isSuperRegister - Returns true if regB is a super-register of regA.
426 bool isSuperRegister(unsigned regA, unsigned regB) const {
427 // SuperregHash is a simple quadratically probed hash table.
428 size_t index = (regA + regB * 37) & (SuperregHashSize-1);
429 unsigned ProbeAmt = 2;
430 while (SuperregHash[index*2] != 0 &&
431 SuperregHash[index*2+1] != 0) {
432 if (SuperregHash[index*2] == regA && SuperregHash[index*2+1] == regB)
435 index = (index + ProbeAmt) & (SuperregHashSize-1);
442 /// getCalleeSavedRegs - Return a null-terminated list of all of the
443 /// callee saved registers on this target. The register should be in the
444 /// order of desired callee-save stack frame offset. The first register is
445 /// closed to the incoming stack pointer if stack grows down, and vice versa.
446 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
449 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
450 /// register classes to spill each callee saved register with. The order and
451 /// length of this list match the getCalleeSaveRegs() list.
452 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
453 const MachineFunction *MF) const =0;
455 /// getReservedRegs - Returns a bitset indexed by physical register number
456 /// indicating if a register is a special register that has particular uses
457 /// and should be considered unavailable at all times, e.g. SP, RA. This is
458 /// used by register scavenger to determine what registers are free.
459 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
461 /// getSubReg - Returns the physical register number of sub-register "Index"
462 /// for physical register RegNo. Return zero if the sub-register does not
464 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
466 /// getMatchingSuperReg - Return a super-register of the specified register
467 /// Reg so its sub-register of index SubIdx is Reg.
468 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
469 const TargetRegisterClass *RC) const {
470 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
471 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
476 /// getMatchingSuperRegClass - Return a subclass of the specified register
477 /// class A so that each register in it has a sub-register of the
478 /// specified sub-register index which is in the specified register class B.
479 virtual const TargetRegisterClass *
480 getMatchingSuperRegClass(const TargetRegisterClass *A,
481 const TargetRegisterClass *B, unsigned Idx) const {
485 //===--------------------------------------------------------------------===//
486 // Register Class Information
489 /// Register class iterators
491 regclass_iterator regclass_begin() const { return RegClassBegin; }
492 regclass_iterator regclass_end() const { return RegClassEnd; }
494 unsigned getNumRegClasses() const {
495 return (unsigned)(regclass_end()-regclass_begin());
498 /// getRegClass - Returns the register class associated with the enumeration
499 /// value. See class TargetOperandInfo.
500 const TargetRegisterClass *getRegClass(unsigned i) const {
501 assert(i <= getNumRegClasses() && "Register Class ID out of range");
502 return i ? RegClassBegin[i - 1] : NULL;
505 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
506 /// values. If a target supports multiple different pointer register classes,
507 /// kind specifies which one is indicated.
508 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
509 assert(0 && "Target didn't implement getPointerRegClass!");
510 return 0; // Must return a value in order to compile with VS 2005
513 /// getCrossCopyRegClass - Returns a legal register class to copy a register
514 /// in the specified class to or from. Returns NULL if it is possible to copy
515 /// between a two registers of the specified class.
516 virtual const TargetRegisterClass *
517 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
521 /// getAllocationOrder - Returns the register allocation order for a specified
522 /// register class in the form of a pair of TargetRegisterClass iterators.
523 virtual std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
524 getAllocationOrder(const TargetRegisterClass *RC,
525 unsigned HintType, unsigned HintReg,
526 const MachineFunction &MF) const {
527 return std::make_pair(RC->allocation_order_begin(MF),
528 RC->allocation_order_end(MF));
531 /// ResolveRegAllocHint - Resolves the specified register allocation hint
532 /// to a physical register. Returns the physical register if it is successful.
533 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
534 const MachineFunction &MF) const {
535 if (Type == 0 && Reg && isPhysicalRegister(Reg))
540 /// UpdateRegAllocHint - A callback to allow target a chance to update
541 /// register allocation hints when a register is "changed" (e.g. coalesced)
542 /// to another register. e.g. On ARM, some virtual registers should target
543 /// register pairs, if one of pair is coalesced to another register, the
544 /// allocation hint of the other half of the pair should be changed to point
545 /// to the new register.
546 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
547 MachineFunction &MF) const {
551 /// targetHandlesStackFrameRounding - Returns true if the target is
552 /// responsible for rounding up the stack frame (probably at emitPrologue
554 virtual bool targetHandlesStackFrameRounding() const {
558 /// requiresRegisterScavenging - returns true if the target requires (and can
559 /// make use of) the register scavenger.
560 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
564 /// requiresFrameIndexScavenging - returns true if the target requires post
565 /// PEI scavenging of registers for materializing frame index constants.
566 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
570 /// hasFP - Return true if the specified function should have a dedicated
571 /// frame pointer register. For most targets this is true only if the function
572 /// has variable sized allocas or if frame pointer elimination is disabled.
573 virtual bool hasFP(const MachineFunction &MF) const = 0;
575 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
576 /// not required, we reserve argument space for call sites in the function
577 /// immediately on entry to the current function. This eliminates the need for
578 /// add/sub sp brackets around call sites. Returns true if the call frame is
579 /// included as part of the stack frame.
580 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
584 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
585 /// the stack frame of the given function for the specified register. e.g. On
586 /// x86, if the frame register is required, the first fixed stack object is
587 /// reserved as its spill slot. This tells PEI not to create a new stack frame
588 /// object for the given register. It should be called only after
589 /// processFunctionBeforeCalleeSavedScan().
590 virtual bool hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
591 int &FrameIdx) const {
595 /// needsStackRealignment - true if storage within the function requires the
596 /// stack pointer to be aligned more than the normal calling convention calls
598 virtual bool needsStackRealignment(const MachineFunction &MF) const {
602 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
603 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
604 /// targets use pseudo instructions in order to abstract away the difference
605 /// between operating with a frame pointer and operating without, through the
606 /// use of these two instructions.
608 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
609 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
611 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
612 /// code insertion to eliminate call frame setup and destroy pseudo
613 /// instructions (but only if the Target is using them). It is responsible
614 /// for eliminating these instructions, replacing them with concrete
615 /// instructions. This method need only be implemented if using call frame
616 /// setup/destroy pseudo instructions.
619 eliminateCallFramePseudoInstr(MachineFunction &MF,
620 MachineBasicBlock &MBB,
621 MachineBasicBlock::iterator MI) const {
622 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
623 "eliminateCallFramePseudoInstr must be implemented if using"
624 " call frame setup/destroy pseudo instructions!");
625 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
628 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
629 /// before PrologEpilogInserter scans the physical registers used to determine
630 /// what callee saved registers should be spilled. This method is optional.
631 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
632 RegScavenger *RS = NULL) const {
636 /// processFunctionBeforeFrameFinalized - This method is called immediately
637 /// before the specified functions frame layout (MF.getFrameInfo()) is
638 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
639 /// replaced with direct constants. This method is optional.
641 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
644 /// saveScavengerRegister - Save the register so it can be used by the
645 /// register scavenger. Return true if the register was saved, false
646 /// otherwise. If this function does not save the register, the scavenger
647 /// will instead spill it to the emergency spill slot.
649 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
650 MachineBasicBlock::iterator I,
651 const TargetRegisterClass *RC,
652 unsigned Reg) const {return false;}
654 /// restoreScavengerRegister - Restore a register saved by
655 /// saveScavengerRegister().
657 virtual void restoreScavengerRegister(MachineBasicBlock &MBB,
658 MachineBasicBlock::iterator I,
659 const TargetRegisterClass *RC,
660 unsigned Reg) const {}
662 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
663 /// frame indices from instructions which may use them. The instruction
664 /// referenced by the iterator contains an MO_FrameIndex operand which must be
665 /// eliminated by this method. This method may modify or replace the
666 /// specified instruction, as long as it keeps the iterator pointing the the
667 /// finished product. SPAdj is the SP adjustment due to call frame setup
670 /// When -enable-frame-index-scavenging is enabled, the virtual register
671 /// allocated for this frame index is returned and its value is stored in
673 virtual unsigned eliminateFrameIndex(MachineBasicBlock::iterator MI,
674 int SPAdj, int *Value = NULL,
675 RegScavenger *RS=NULL) const = 0;
677 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
679 virtual void emitPrologue(MachineFunction &MF) const = 0;
680 virtual void emitEpilogue(MachineFunction &MF,
681 MachineBasicBlock &MBB) const = 0;
683 //===--------------------------------------------------------------------===//
684 /// Debug information queries.
686 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
687 /// number. Returns -1 if there is no equivalent value. The second
688 /// parameter allows targets to use different numberings for EH info and
690 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
692 /// getFrameRegister - This method should return the register used as a base
693 /// for values allocated in the current stack frame.
694 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
696 /// getFrameIndexOffset - Returns the displacement from the frame register to
697 /// the stack frame of the specified index.
698 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const;
700 /// getRARegister - This method should return the register where the return
701 /// address can be found.
702 virtual unsigned getRARegister() const = 0;
704 /// getInitialFrameState - Returns a list of machine moves that are assumed
705 /// on entry to all functions. Note that LabelID is ignored (assumed to be
706 /// the beginning of the function.)
707 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
711 // This is useful when building IndexedMaps keyed on virtual registers
712 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
713 unsigned operator()(unsigned Reg) const {
714 return Reg - TargetRegisterInfo::FirstVirtualRegister;
718 /// getCommonSubClass - find the largest common subclass of A and B. Return NULL
719 /// if there is no common subclass.
720 const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A,
721 const TargetRegisterClass *B);
723 } // End llvm namespace