1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/DenseSet.h"
30 class MachineFunction;
32 template<class T> class SmallVectorImpl;
35 class TargetRegisterClass {
37 typedef const unsigned* iterator;
38 typedef const unsigned* const_iterator;
40 typedef const EVT* vt_iterator;
41 typedef const TargetRegisterClass* const * sc_iterator;
45 const vt_iterator VTs;
46 const sc_iterator SubClasses;
47 const sc_iterator SuperClasses;
48 const sc_iterator SubRegClasses;
49 const sc_iterator SuperRegClasses;
50 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
52 const bool Allocatable;
53 const iterator RegsBegin, RegsEnd;
54 DenseSet<unsigned> RegSet;
56 TargetRegisterClass(unsigned id,
59 const TargetRegisterClass * const *subcs,
60 const TargetRegisterClass * const *supcs,
61 const TargetRegisterClass * const *subregcs,
62 const TargetRegisterClass * const *superregcs,
63 unsigned RS, unsigned Al, int CC, bool Allocable,
64 iterator RB, iterator RE)
65 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
66 SubRegClasses(subregcs), SuperRegClasses(superregcs),
67 RegSize(RS), Alignment(Al), CopyCost(CC), Allocatable(Allocable),
68 RegsBegin(RB), RegsEnd(RE) {
69 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
72 virtual ~TargetRegisterClass() {} // Allow subclasses
74 /// getID() - Return the register class ID number.
76 unsigned getID() const { return ID; }
78 /// getName() - Return the register class name for debugging.
80 const char *getName() const { return Name; }
82 /// begin/end - Return all of the registers in this class.
84 iterator begin() const { return RegsBegin; }
85 iterator end() const { return RegsEnd; }
87 /// getNumRegs - Return the number of registers in this class.
89 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
91 /// getRegister - Return the specified register in the class.
93 unsigned getRegister(unsigned i) const {
94 assert(i < getNumRegs() && "Register number out of range!");
98 /// contains - Return true if the specified register is included in this
99 /// register class. This does not include virtual registers.
100 bool contains(unsigned Reg) const {
101 return RegSet.count(Reg);
104 /// contains - Return true if both registers are in this class.
105 bool contains(unsigned Reg1, unsigned Reg2) const {
106 return contains(Reg1) && contains(Reg2);
109 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
111 bool hasType(EVT vt) const {
112 for(int i = 0; VTs[i] != MVT::Other; ++i)
118 /// vt_begin / vt_end - Loop over all of the value types that can be
119 /// represented by values in this register class.
120 vt_iterator vt_begin() const {
124 vt_iterator vt_end() const {
126 while (*I != MVT::Other) ++I;
130 /// subregclasses_begin / subregclasses_end - Loop over all of
131 /// the subreg register classes of this register class.
132 sc_iterator subregclasses_begin() const {
133 return SubRegClasses;
136 sc_iterator subregclasses_end() const {
137 sc_iterator I = SubRegClasses;
138 while (*I != NULL) ++I;
142 /// getSubRegisterRegClass - Return the register class of subregisters with
143 /// index SubIdx, or NULL if no such class exists.
144 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
145 assert(SubIdx>0 && "Invalid subregister index");
146 return SubRegClasses[SubIdx-1];
149 /// superregclasses_begin / superregclasses_end - Loop over all of
150 /// the superreg register classes of this register class.
151 sc_iterator superregclasses_begin() const {
152 return SuperRegClasses;
155 sc_iterator superregclasses_end() const {
156 sc_iterator I = SuperRegClasses;
157 while (*I != NULL) ++I;
161 /// hasSubClass - return true if the specified TargetRegisterClass
162 /// is a proper subset of this TargetRegisterClass.
163 bool hasSubClass(const TargetRegisterClass *cs) const {
164 for (int i = 0; SubClasses[i] != NULL; ++i)
165 if (SubClasses[i] == cs)
170 /// hasSubClassEq - Returns true if RC is a subclass of or equal to this
172 bool hasSubClassEq(const TargetRegisterClass *RC) const {
173 return RC == this || hasSubClass(RC);
176 /// subclasses_begin / subclasses_end - Loop over all of the classes
177 /// that are proper subsets of this register class.
178 sc_iterator subclasses_begin() const {
182 sc_iterator subclasses_end() const {
183 sc_iterator I = SubClasses;
184 while (*I != NULL) ++I;
188 /// hasSuperClass - return true if the specified TargetRegisterClass is a
189 /// proper superset of this TargetRegisterClass.
190 bool hasSuperClass(const TargetRegisterClass *cs) const {
191 for (int i = 0; SuperClasses[i] != NULL; ++i)
192 if (SuperClasses[i] == cs)
197 /// hasSuperClassEq - Returns true if RC is a superclass of or equal to this
199 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
200 return RC == this || hasSuperClass(RC);
203 /// superclasses_begin / superclasses_end - Loop over all of the classes
204 /// that are proper supersets of this register class.
205 sc_iterator superclasses_begin() const {
209 sc_iterator superclasses_end() const {
210 sc_iterator I = SuperClasses;
211 while (*I != NULL) ++I;
215 /// isASubClass - return true if this TargetRegisterClass is a subset
216 /// class of at least one other TargetRegisterClass.
217 bool isASubClass() const {
218 return SuperClasses[0] != 0;
221 /// getRawAllocationOrder - Returns the preferred order for allocating
222 /// registers from this register class in MF. The raw order comes directly
223 /// from the .td file and may include reserved registers that are not
224 /// allocatable. Register allocators should also make sure to allocate
225 /// callee-saved registers only after all the volatiles are used. The
226 /// RegisterClassInfo class provides filtered allocation orders with
227 /// callee-saved registers moved to the end.
229 /// The MachineFunction argument can be used to tune the allocatable
230 /// registers based on the characteristics of the function, subtarget, or
233 /// By default, this method returns all registers in the class.
236 ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const {
237 return makeArrayRef(begin(), getNumRegs());
240 /// getSize - Return the size of the register in bytes, which is also the size
241 /// of a stack slot allocated to hold a spilled copy of this register.
242 unsigned getSize() const { return RegSize; }
244 /// getAlignment - Return the minimum required alignment for a register of
246 unsigned getAlignment() const { return Alignment; }
248 /// getCopyCost - Return the cost of copying a value between two registers in
249 /// this class. A negative number means the register class is very expensive
250 /// to copy e.g. status flag register classes.
251 int getCopyCost() const { return CopyCost; }
253 /// isAllocatable - Return true if this register class may be used to create
254 /// virtual registers.
255 bool isAllocatable() const { return Allocatable; }
258 /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
259 /// registers. These are used by codegen, not by MC.
260 struct TargetRegisterInfoDesc {
261 unsigned CostPerUse; // Extra cost of instructions using register.
262 bool inAllocatableClass; // Register belongs to an allocatable regclass.
265 /// TargetRegisterInfo base class - We assume that the target defines a static
266 /// array of TargetRegisterDesc objects that represent all of the machine
267 /// registers that the target has. As such, we simply have to track a pointer
268 /// to this array so that we can turn register number into a register
271 class TargetRegisterInfo : public MCRegisterInfo {
273 typedef const TargetRegisterClass * const * regclass_iterator;
275 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
276 const char *const *SubRegIndexNames; // Names of subreg indexes.
277 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
280 TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
281 regclass_iterator RegClassBegin,
282 regclass_iterator RegClassEnd,
283 const char *const *subregindexnames);
284 virtual ~TargetRegisterInfo();
287 // Register numbers can represent physical registers, virtual registers, and
288 // sometimes stack slots. The unsigned values are divided into these ranges:
290 // 0 Not a register, can be used as a sentinel.
291 // [1;2^30) Physical registers assigned by TableGen.
292 // [2^30;2^31) Stack slots. (Rarely used.)
293 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
295 // Further sentinels can be allocated from the small negative integers.
296 // DenseMapInfo<unsigned> uses -1u and -2u.
298 /// isStackSlot - Sometimes it is useful the be able to store a non-negative
299 /// frame index in a variable that normally holds a register. isStackSlot()
300 /// returns true if Reg is in the range used for stack slots.
302 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
303 /// slots, so if a variable may contains a stack slot, always check
304 /// isStackSlot() first.
306 static bool isStackSlot(unsigned Reg) {
307 return int(Reg) >= (1 << 30);
310 /// stackSlot2Index - Compute the frame index from a register value
311 /// representing a stack slot.
312 static int stackSlot2Index(unsigned Reg) {
313 assert(isStackSlot(Reg) && "Not a stack slot");
314 return int(Reg - (1u << 30));
317 /// index2StackSlot - Convert a non-negative frame index to a stack slot
319 static unsigned index2StackSlot(int FI) {
320 assert(FI >= 0 && "Cannot hold a negative frame index.");
321 return FI + (1u << 30);
324 /// isPhysicalRegister - Return true if the specified register number is in
325 /// the physical register namespace.
326 static bool isPhysicalRegister(unsigned Reg) {
327 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
331 /// isVirtualRegister - Return true if the specified register number is in
332 /// the virtual register namespace.
333 static bool isVirtualRegister(unsigned Reg) {
334 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
338 /// virtReg2Index - Convert a virtual register number to a 0-based index.
339 /// The first virtual register in a function will get the index 0.
340 static unsigned virtReg2Index(unsigned Reg) {
341 assert(isVirtualRegister(Reg) && "Not a virtual register");
342 return Reg & ~(1u << 31);
345 /// index2VirtReg - Convert a 0-based index to a virtual register number.
346 /// This is the inverse operation of VirtReg2IndexFunctor below.
347 static unsigned index2VirtReg(unsigned Index) {
348 return Index | (1u << 31);
351 /// getMinimalPhysRegClass - Returns the Register Class of a physical
352 /// register of the given type, picking the most sub register class of
353 /// the right type that contains this physreg.
354 const TargetRegisterClass *
355 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
357 /// getAllocatableSet - Returns a bitset indexed by register number
358 /// indicating if a register is allocatable or not. If a register class is
359 /// specified, returns the subset for the class.
360 BitVector getAllocatableSet(const MachineFunction &MF,
361 const TargetRegisterClass *RC = NULL) const;
363 /// getCostPerUse - Return the additional cost of using this register instead
364 /// of other registers in its class.
365 unsigned getCostPerUse(unsigned RegNo) const {
366 return InfoDesc[RegNo].CostPerUse;
369 /// isInAllocatableClass - Return true if the register is in the allocation
370 /// of any register class.
371 bool isInAllocatableClass(unsigned RegNo) const {
372 return InfoDesc[RegNo].inAllocatableClass;
375 /// getSubRegIndexName - Return the human-readable symbolic target-specific
376 /// name for the specified SubRegIndex.
377 const char *getSubRegIndexName(unsigned SubIdx) const {
378 assert(SubIdx && "This is not a subregister index");
379 return SubRegIndexNames[SubIdx-1];
382 /// regsOverlap - Returns true if the two registers are equal or alias each
383 /// other. The registers may be virtual register.
384 bool regsOverlap(unsigned regA, unsigned regB) const {
385 if (regA == regB) return true;
386 if (isVirtualRegister(regA) || isVirtualRegister(regB))
388 for (const unsigned *regList = getOverlaps(regA)+1; *regList; ++regList) {
389 if (*regList == regB) return true;
394 /// isSubRegister - Returns true if regB is a sub-register of regA.
396 bool isSubRegister(unsigned regA, unsigned regB) const {
397 return isSuperRegister(regB, regA);
400 /// isSuperRegister - Returns true if regB is a super-register of regA.
402 bool isSuperRegister(unsigned regA, unsigned regB) const {
403 for (const unsigned *regList = getSuperRegisters(regA); *regList;++regList){
404 if (*regList == regB) return true;
409 /// getCalleeSavedRegs - Return a null-terminated list of all of the
410 /// callee saved registers on this target. The register should be in the
411 /// order of desired callee-save stack frame offset. The first register is
412 /// closed to the incoming stack pointer if stack grows down, and vice versa.
413 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
417 /// getReservedRegs - Returns a bitset indexed by physical register number
418 /// indicating if a register is a special register that has particular uses
419 /// and should be considered unavailable at all times, e.g. SP, RA. This is
420 /// used by register scavenger to determine what registers are free.
421 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
423 /// getSubReg - Returns the physical register number of sub-register "Index"
424 /// for physical register RegNo. Return zero if the sub-register does not
426 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
428 /// getSubRegIndex - For a given register pair, return the sub-register index
429 /// if the second register is a sub-register of the first. Return zero
431 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0;
433 /// getMatchingSuperReg - Return a super-register of the specified register
434 /// Reg so its sub-register of index SubIdx is Reg.
435 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
436 const TargetRegisterClass *RC) const {
437 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
438 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
443 /// canCombineSubRegIndices - Given a register class and a list of
444 /// subregister indices, return true if it's possible to combine the
445 /// subregister indices into one that corresponds to a larger
446 /// subregister. Return the new subregister index by reference. Note the
447 /// new index may be zero if the given subregisters can be combined to
448 /// form the whole register.
449 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
450 SmallVectorImpl<unsigned> &SubIndices,
451 unsigned &NewSubIdx) const {
455 /// getMatchingSuperRegClass - Return a subclass of the specified register
456 /// class A so that each register in it has a sub-register of the
457 /// specified sub-register index which is in the specified register class B.
458 virtual const TargetRegisterClass *
459 getMatchingSuperRegClass(const TargetRegisterClass *A,
460 const TargetRegisterClass *B, unsigned Idx) const {
464 /// composeSubRegIndices - Return the subregister index you get from composing
465 /// two subregister indices.
467 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
468 /// returns c. Note that composeSubRegIndices does not tell you about illegal
469 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
470 /// b, composeSubRegIndices doesn't tell you.
472 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
473 /// ssub_0:S0 - ssub_3:S3 subregs.
474 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
476 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const {
477 // This default implementation is correct for most targets.
481 //===--------------------------------------------------------------------===//
482 // Register Class Information
485 /// Register class iterators
487 regclass_iterator regclass_begin() const { return RegClassBegin; }
488 regclass_iterator regclass_end() const { return RegClassEnd; }
490 unsigned getNumRegClasses() const {
491 return (unsigned)(regclass_end()-regclass_begin());
494 /// getRegClass - Returns the register class associated with the enumeration
495 /// value. See class MCOperandInfo.
496 const TargetRegisterClass *getRegClass(unsigned i) const {
497 assert(i < getNumRegClasses() && "Register Class ID out of range");
498 return RegClassBegin[i];
501 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
502 /// values. If a target supports multiple different pointer register classes,
503 /// kind specifies which one is indicated.
504 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
505 assert(0 && "Target didn't implement getPointerRegClass!");
506 return 0; // Must return a value in order to compile with VS 2005
509 /// getCrossCopyRegClass - Returns a legal register class to copy a register
510 /// in the specified class to or from. If it is possible to copy the register
511 /// directly without using a cross register class copy, return the specified
512 /// RC. Returns NULL if it is not possible to copy between a two registers of
513 /// the specified class.
514 virtual const TargetRegisterClass *
515 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
519 /// getLargestLegalSuperClass - Returns the largest super class of RC that is
520 /// legal to use in the current sub-target and has the same spill size.
521 /// The returned register class can be used to create virtual registers which
522 /// means that all its registers can be copied and spilled.
523 virtual const TargetRegisterClass*
524 getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
525 /// The default implementation is very conservative and doesn't allow the
526 /// register allocator to inflate register classes.
530 /// getRegPressureLimit - Return the register pressure "high water mark" for
531 /// the specific register class. The scheduler is in high register pressure
532 /// mode (for the specific register class) if it goes over the limit.
533 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
534 MachineFunction &MF) const {
538 /// getRawAllocationOrder - Returns the register allocation order for a
539 /// specified register class with a target-dependent hint. The returned list
540 /// may contain reserved registers that cannot be allocated.
542 /// Register allocators need only call this function to resolve
543 /// target-dependent hints, but it should work without hinting as well.
544 virtual ArrayRef<unsigned>
545 getRawAllocationOrder(const TargetRegisterClass *RC,
546 unsigned HintType, unsigned HintReg,
547 const MachineFunction &MF) const {
548 return RC->getRawAllocationOrder(MF);
551 /// ResolveRegAllocHint - Resolves the specified register allocation hint
552 /// to a physical register. Returns the physical register if it is successful.
553 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
554 const MachineFunction &MF) const {
555 if (Type == 0 && Reg && isPhysicalRegister(Reg))
560 /// avoidWriteAfterWrite - Return true if the register allocator should avoid
561 /// writing a register from RC in two consecutive instructions.
562 /// This can avoid pipeline stalls on certain architectures.
563 /// It does cause increased register pressure, though.
564 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
568 /// UpdateRegAllocHint - A callback to allow target a chance to update
569 /// register allocation hints when a register is "changed" (e.g. coalesced)
570 /// to another register. e.g. On ARM, some virtual registers should target
571 /// register pairs, if one of pair is coalesced to another register, the
572 /// allocation hint of the other half of the pair should be changed to point
573 /// to the new register.
574 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
575 MachineFunction &MF) const {
579 /// requiresRegisterScavenging - returns true if the target requires (and can
580 /// make use of) the register scavenger.
581 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
585 /// useFPForScavengingIndex - returns true if the target wants to use
586 /// frame pointer based accesses to spill to the scavenger emergency spill
588 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
592 /// requiresFrameIndexScavenging - returns true if the target requires post
593 /// PEI scavenging of registers for materializing frame index constants.
594 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
598 /// requiresVirtualBaseRegisters - Returns true if the target wants the
599 /// LocalStackAllocation pass to be run and virtual base registers
600 /// used for more efficient stack access.
601 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
605 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
606 /// the stack frame of the given function for the specified register. e.g. On
607 /// x86, if the frame register is required, the first fixed stack object is
608 /// reserved as its spill slot. This tells PEI not to create a new stack frame
609 /// object for the given register. It should be called only after
610 /// processFunctionBeforeCalleeSavedScan().
611 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
612 int &FrameIdx) const {
616 /// needsStackRealignment - true if storage within the function requires the
617 /// stack pointer to be aligned more than the normal calling convention calls
619 virtual bool needsStackRealignment(const MachineFunction &MF) const {
623 /// getFrameIndexInstrOffset - Get the offset from the referenced frame
624 /// index in the instruction, if there is one.
625 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
630 /// needsFrameBaseReg - Returns true if the instruction's frame index
631 /// reference would be better served by a base register other than FP
632 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
633 /// references it should create new base registers for.
634 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
638 /// materializeFrameBaseRegister - Insert defining instruction(s) for
639 /// BaseReg to be a pointer to FrameIdx before insertion point I.
640 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
641 unsigned BaseReg, int FrameIdx,
642 int64_t Offset) const {
643 assert(0 && "materializeFrameBaseRegister does not exist on this target");
646 /// resolveFrameIndex - Resolve a frame index operand of an instruction
647 /// to reference the indicated base register plus offset instead.
648 virtual void resolveFrameIndex(MachineBasicBlock::iterator I,
649 unsigned BaseReg, int64_t Offset) const {
650 assert(0 && "resolveFrameIndex does not exist on this target");
653 /// isFrameOffsetLegal - Determine whether a given offset immediate is
654 /// encodable to resolve a frame index.
655 virtual bool isFrameOffsetLegal(const MachineInstr *MI,
656 int64_t Offset) const {
657 assert(0 && "isFrameOffsetLegal does not exist on this target");
658 return false; // Must return a value in order to compile with VS 2005
661 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
662 /// code insertion to eliminate call frame setup and destroy pseudo
663 /// instructions (but only if the Target is using them). It is responsible
664 /// for eliminating these instructions, replacing them with concrete
665 /// instructions. This method need only be implemented if using call frame
666 /// setup/destroy pseudo instructions.
669 eliminateCallFramePseudoInstr(MachineFunction &MF,
670 MachineBasicBlock &MBB,
671 MachineBasicBlock::iterator MI) const {
672 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
676 /// saveScavengerRegister - Spill the register so it can be used by the
677 /// register scavenger. Return true if the register was spilled, false
678 /// otherwise. If this function does not spill the register, the scavenger
679 /// will instead spill it to the emergency spill slot.
681 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
682 MachineBasicBlock::iterator I,
683 MachineBasicBlock::iterator &UseMI,
684 const TargetRegisterClass *RC,
685 unsigned Reg) const {
689 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
690 /// frame indices from instructions which may use them. The instruction
691 /// referenced by the iterator contains an MO_FrameIndex operand which must be
692 /// eliminated by this method. This method may modify or replace the
693 /// specified instruction, as long as it keeps the iterator pointing at the
694 /// finished product. SPAdj is the SP adjustment due to call frame setup
696 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
697 int SPAdj, RegScavenger *RS=NULL) const = 0;
699 //===--------------------------------------------------------------------===//
700 /// Debug information queries.
702 /// getFrameRegister - This method should return the register used as a base
703 /// for values allocated in the current stack frame.
704 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
706 /// getCompactUnwindRegNum - This function maps the register to the number for
707 /// compact unwind encoding. Return -1 if the register isn't valid.
708 virtual int getCompactUnwindRegNum(unsigned, bool) const {
714 // This is useful when building IndexedMaps keyed on virtual registers
715 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
716 unsigned operator()(unsigned Reg) const {
717 return TargetRegisterInfo::virtReg2Index(Reg);
721 /// getCommonSubClass - find the largest common subclass of A and B. Return NULL
722 /// if there is no common subclass.
723 const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A,
724 const TargetRegisterClass *B);
726 /// PrintReg - Helper class for printing registers on a raw_ostream.
727 /// Prints virtual and physical registers with or without a TRI instance.
730 /// %noreg - NoRegister
731 /// %vreg5 - a virtual register.
732 /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
733 /// %EAX - a physical register
734 /// %physreg17 - a physical register when no TRI instance given.
736 /// Usage: OS << PrintReg(Reg, TRI) << '\n';
739 const TargetRegisterInfo *TRI;
743 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0)
744 : TRI(tri), Reg(reg), SubIdx(subidx) {}
745 void print(raw_ostream&) const;
748 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
753 } // End llvm namespace