1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineValueType.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/MC/MCRegisterInfo.h"
30 class MachineFunction;
32 template<class T> class SmallVectorImpl;
36 class TargetRegisterClass {
38 typedef const MCPhysReg* iterator;
39 typedef const MCPhysReg* const_iterator;
40 typedef const MVT::SimpleValueType* vt_iterator;
41 typedef const TargetRegisterClass* const * sc_iterator;
43 // Instance variables filled by tablegen, do not use!
44 const MCRegisterClass *MC;
45 const vt_iterator VTs;
46 const uint32_t *SubClassMask;
47 const uint16_t *SuperRegIndices;
48 const sc_iterator SuperClasses;
49 ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
51 /// getID() - Return the register class ID number.
53 unsigned getID() const { return MC->getID(); }
55 /// begin/end - Return all of the registers in this class.
57 iterator begin() const { return MC->begin(); }
58 iterator end() const { return MC->end(); }
60 /// getNumRegs - Return the number of registers in this class.
62 unsigned getNumRegs() const { return MC->getNumRegs(); }
64 /// getRegister - Return the specified register in the class.
66 unsigned getRegister(unsigned i) const {
67 return MC->getRegister(i);
70 /// contains - Return true if the specified register is included in this
71 /// register class. This does not include virtual registers.
72 bool contains(unsigned Reg) const {
73 return MC->contains(Reg);
76 /// contains - Return true if both registers are in this class.
77 bool contains(unsigned Reg1, unsigned Reg2) const {
78 return MC->contains(Reg1, Reg2);
81 /// getSize - Return the size of the register in bytes, which is also the size
82 /// of a stack slot allocated to hold a spilled copy of this register.
83 unsigned getSize() const { return MC->getSize(); }
85 /// getAlignment - Return the minimum required alignment for a register of
87 unsigned getAlignment() const { return MC->getAlignment(); }
89 /// getCopyCost - Return the cost of copying a value between two registers in
90 /// this class. A negative number means the register class is very expensive
91 /// to copy e.g. status flag register classes.
92 int getCopyCost() const { return MC->getCopyCost(); }
94 /// isAllocatable - Return true if this register class may be used to create
95 /// virtual registers.
96 bool isAllocatable() const { return MC->isAllocatable(); }
98 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
100 bool hasType(MVT vt) const {
101 for(int i = 0; VTs[i] != MVT::Other; ++i)
102 if (MVT(VTs[i]) == vt)
107 /// vt_begin / vt_end - Loop over all of the value types that can be
108 /// represented by values in this register class.
109 vt_iterator vt_begin() const {
113 vt_iterator vt_end() const {
115 while (*I != MVT::Other) ++I;
119 /// hasSubClass - return true if the specified TargetRegisterClass
120 /// is a proper sub-class of this TargetRegisterClass.
121 bool hasSubClass(const TargetRegisterClass *RC) const {
122 return RC != this && hasSubClassEq(RC);
125 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
127 bool hasSubClassEq(const TargetRegisterClass *RC) const {
128 unsigned ID = RC->getID();
129 return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
132 /// hasSuperClass - return true if the specified TargetRegisterClass is a
133 /// proper super-class of this TargetRegisterClass.
134 bool hasSuperClass(const TargetRegisterClass *RC) const {
135 return RC->hasSubClass(this);
138 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this
140 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
141 return RC->hasSubClassEq(this);
144 /// getSubClassMask - Returns a bit vector of subclasses, including this one.
145 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
147 const uint32_t *getSubClassMask() const {
151 /// getSuperRegIndices - Returns a 0-terminated list of sub-register indices
152 /// that project some super-register class into this register class. The list
153 /// has an entry for each Idx such that:
155 /// There exists SuperRC where:
156 /// For all Reg in SuperRC:
157 /// this->contains(Reg:Idx)
159 const uint16_t *getSuperRegIndices() const {
160 return SuperRegIndices;
163 /// getSuperClasses - Returns a NULL terminated list of super-classes. The
164 /// classes are ordered by ID which is also a topological ordering from large
165 /// to small classes. The list does NOT include the current class.
166 sc_iterator getSuperClasses() const {
170 /// isASubClass - return true if this TargetRegisterClass is a subset
171 /// class of at least one other TargetRegisterClass.
172 bool isASubClass() const {
173 return SuperClasses[0] != nullptr;
176 /// getRawAllocationOrder - Returns the preferred order for allocating
177 /// registers from this register class in MF. The raw order comes directly
178 /// from the .td file and may include reserved registers that are not
179 /// allocatable. Register allocators should also make sure to allocate
180 /// callee-saved registers only after all the volatiles are used. The
181 /// RegisterClassInfo class provides filtered allocation orders with
182 /// callee-saved registers moved to the end.
184 /// The MachineFunction argument can be used to tune the allocatable
185 /// registers based on the characteristics of the function, subtarget, or
188 /// By default, this method returns all registers in the class.
190 ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
191 return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
195 /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
196 /// registers. These are used by codegen, not by MC.
197 struct TargetRegisterInfoDesc {
198 unsigned CostPerUse; // Extra cost of instructions using register.
199 bool inAllocatableClass; // Register belongs to an allocatable regclass.
202 /// Each TargetRegisterClass has a per register weight, and weight
203 /// limit which must be less than the limits of its pressure sets.
204 struct RegClassWeight {
206 unsigned WeightLimit;
209 /// TargetRegisterInfo base class - We assume that the target defines a static
210 /// array of TargetRegisterDesc objects that represent all of the machine
211 /// registers that the target has. As such, we simply have to track a pointer
212 /// to this array so that we can turn register number into a register
215 class TargetRegisterInfo : public MCRegisterInfo {
217 typedef const TargetRegisterClass * const * regclass_iterator;
219 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
220 const char *const *SubRegIndexNames; // Names of subreg indexes.
221 // Pointer to array of lane masks, one per sub-reg index.
222 const unsigned *SubRegIndexLaneMasks;
224 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
225 unsigned CoveringLanes;
228 TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
229 regclass_iterator RegClassBegin,
230 regclass_iterator RegClassEnd,
231 const char *const *SRINames,
232 const unsigned *SRILaneMasks,
233 unsigned CoveringLanes);
234 virtual ~TargetRegisterInfo();
237 // Register numbers can represent physical registers, virtual registers, and
238 // sometimes stack slots. The unsigned values are divided into these ranges:
240 // 0 Not a register, can be used as a sentinel.
241 // [1;2^30) Physical registers assigned by TableGen.
242 // [2^30;2^31) Stack slots. (Rarely used.)
243 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
245 // Further sentinels can be allocated from the small negative integers.
246 // DenseMapInfo<unsigned> uses -1u and -2u.
248 /// isStackSlot - Sometimes it is useful the be able to store a non-negative
249 /// frame index in a variable that normally holds a register. isStackSlot()
250 /// returns true if Reg is in the range used for stack slots.
252 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
253 /// slots, so if a variable may contains a stack slot, always check
254 /// isStackSlot() first.
256 static bool isStackSlot(unsigned Reg) {
257 return int(Reg) >= (1 << 30);
260 /// stackSlot2Index - Compute the frame index from a register value
261 /// representing a stack slot.
262 static int stackSlot2Index(unsigned Reg) {
263 assert(isStackSlot(Reg) && "Not a stack slot");
264 return int(Reg - (1u << 30));
267 /// index2StackSlot - Convert a non-negative frame index to a stack slot
269 static unsigned index2StackSlot(int FI) {
270 assert(FI >= 0 && "Cannot hold a negative frame index.");
271 return FI + (1u << 30);
274 /// isPhysicalRegister - Return true if the specified register number is in
275 /// the physical register namespace.
276 static bool isPhysicalRegister(unsigned Reg) {
277 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
281 /// isVirtualRegister - Return true if the specified register number is in
282 /// the virtual register namespace.
283 static bool isVirtualRegister(unsigned Reg) {
284 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
288 /// virtReg2Index - Convert a virtual register number to a 0-based index.
289 /// The first virtual register in a function will get the index 0.
290 static unsigned virtReg2Index(unsigned Reg) {
291 assert(isVirtualRegister(Reg) && "Not a virtual register");
292 return Reg & ~(1u << 31);
295 /// index2VirtReg - Convert a 0-based index to a virtual register number.
296 /// This is the inverse operation of VirtReg2IndexFunctor below.
297 static unsigned index2VirtReg(unsigned Index) {
298 return Index | (1u << 31);
301 /// getMinimalPhysRegClass - Returns the Register Class of a physical
302 /// register of the given type, picking the most sub register class of
303 /// the right type that contains this physreg.
304 const TargetRegisterClass *
305 getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const;
307 /// getAllocatableClass - Return the maximal subclass of the given register
308 /// class that is alloctable, or NULL.
309 const TargetRegisterClass *
310 getAllocatableClass(const TargetRegisterClass *RC) const;
312 /// getAllocatableSet - Returns a bitset indexed by register number
313 /// indicating if a register is allocatable or not. If a register class is
314 /// specified, returns the subset for the class.
315 BitVector getAllocatableSet(const MachineFunction &MF,
316 const TargetRegisterClass *RC = nullptr) const;
318 /// getCostPerUse - Return the additional cost of using this register instead
319 /// of other registers in its class.
320 unsigned getCostPerUse(unsigned RegNo) const {
321 return InfoDesc[RegNo].CostPerUse;
324 /// isInAllocatableClass - Return true if the register is in the allocation
325 /// of any register class.
326 bool isInAllocatableClass(unsigned RegNo) const {
327 return InfoDesc[RegNo].inAllocatableClass;
330 /// getSubRegIndexName - Return the human-readable symbolic target-specific
331 /// name for the specified SubRegIndex.
332 const char *getSubRegIndexName(unsigned SubIdx) const {
333 assert(SubIdx && SubIdx < getNumSubRegIndices() &&
334 "This is not a subregister index");
335 return SubRegIndexNames[SubIdx-1];
338 /// getSubRegIndexLaneMask - Return a bitmask representing the parts of a
339 /// register that are covered by SubIdx.
341 /// Lane masks for sub-register indices are similar to register units for
342 /// physical registers. The individual bits in a lane mask can't be assigned
343 /// any specific meaning. They can be used to check if two sub-register
346 /// If the target has a register such that:
348 /// getSubReg(Reg, A) overlaps getSubReg(Reg, B)
352 /// getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B) != 0
354 /// The converse is not necessarily true. If two lane masks have a common
355 /// bit, the corresponding sub-registers may not overlap, but it can be
356 /// assumed that they usually will.
357 unsigned getSubRegIndexLaneMask(unsigned SubIdx) const {
358 // SubIdx == 0 is allowed, it has the lane mask ~0u.
359 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
360 return SubRegIndexLaneMasks[SubIdx];
363 /// The lane masks returned by getSubRegIndexLaneMask() above can only be
364 /// used to determine if sub-registers overlap - they can't be used to
365 /// determine if a set of sub-registers completely cover another
368 /// The X86 general purpose registers have two lanes corresponding to the
369 /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
370 /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
371 /// sub_32bit sub-register.
373 /// On the other hand, the ARM NEON lanes fully cover their registers: The
374 /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
375 /// This is related to the CoveredBySubRegs property on register definitions.
377 /// This function returns a bit mask of lanes that completely cover their
378 /// sub-registers. More precisely, given:
380 /// Covering = getCoveringLanes();
381 /// MaskA = getSubRegIndexLaneMask(SubA);
382 /// MaskB = getSubRegIndexLaneMask(SubB);
384 /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
386 unsigned getCoveringLanes() const { return CoveringLanes; }
388 /// regsOverlap - Returns true if the two registers are equal or alias each
389 /// other. The registers may be virtual register.
390 bool regsOverlap(unsigned regA, unsigned regB) const {
391 if (regA == regB) return true;
392 if (isVirtualRegister(regA) || isVirtualRegister(regB))
395 // Regunits are numerically ordered. Find a common unit.
396 MCRegUnitIterator RUA(regA, this);
397 MCRegUnitIterator RUB(regB, this);
399 if (*RUA == *RUB) return true;
400 if (*RUA < *RUB) ++RUA;
402 } while (RUA.isValid() && RUB.isValid());
406 /// hasRegUnit - Returns true if Reg contains RegUnit.
407 bool hasRegUnit(unsigned Reg, unsigned RegUnit) const {
408 for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
409 if (*Units == RegUnit)
414 /// getCalleeSavedRegs - Return a null-terminated list of all of the
415 /// callee saved registers on this target. The register should be in the
416 /// order of desired callee-save stack frame offset. The first register is
417 /// closest to the incoming stack pointer if stack grows down, and vice versa.
419 virtual const MCPhysReg*
420 getCalleeSavedRegs(const MachineFunction *MF = nullptr) const = 0;
422 /// getCallPreservedMask - Return a mask of call-preserved registers for the
423 /// given calling convention on the current sub-target. The mask should
424 /// include all call-preserved aliases. This is used by the register
425 /// allocator to determine which registers can be live across a call.
427 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
428 /// A set bit indicates that all bits of the corresponding register are
429 /// preserved across the function call. The bit mask is expected to be
430 /// sub-register complete, i.e. if A is preserved, so are all its
433 /// Bits are numbered from the LSB, so the bit for physical register Reg can
434 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
436 /// A NULL pointer means that no register mask will be used, and call
437 /// instructions should use implicit-def operands to indicate call clobbered
440 virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const {
441 // The default mask clobbers everything. All targets should override.
445 /// getReservedRegs - Returns a bitset indexed by physical register number
446 /// indicating if a register is a special register that has particular uses
447 /// and should be considered unavailable at all times, e.g. SP, RA. This is
448 /// used by register scavenger to determine what registers are free.
449 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
451 /// getMatchingSuperReg - Return a super-register of the specified register
452 /// Reg so its sub-register of index SubIdx is Reg.
453 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
454 const TargetRegisterClass *RC) const {
455 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
458 /// getMatchingSuperRegClass - Return a subclass of the specified register
459 /// class A so that each register in it has a sub-register of the
460 /// specified sub-register index which is in the specified register class B.
462 /// TableGen will synthesize missing A sub-classes.
463 virtual const TargetRegisterClass *
464 getMatchingSuperRegClass(const TargetRegisterClass *A,
465 const TargetRegisterClass *B, unsigned Idx) const;
467 /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that
468 /// supports the sub-register index Idx.
469 /// If no such sub-class exists, return NULL.
470 /// If all registers in RC already have an Idx sub-register, return RC.
472 /// TableGen generates a version of this function that is good enough in most
473 /// cases. Targets can override if they have constraints that TableGen
474 /// doesn't understand. For example, the x86 sub_8bit sub-register index is
475 /// supported by the full GR32 register class in 64-bit mode, but only by the
476 /// GR32_ABCD regiister class in 32-bit mode.
478 /// TableGen will synthesize missing RC sub-classes.
479 virtual const TargetRegisterClass *
480 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
481 assert(Idx == 0 && "Target has no sub-registers");
485 /// composeSubRegIndices - Return the subregister index you get from composing
486 /// two subregister indices.
488 /// The special null sub-register index composes as the identity.
490 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
491 /// returns c. Note that composeSubRegIndices does not tell you about illegal
492 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
493 /// b, composeSubRegIndices doesn't tell you.
495 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
496 /// ssub_0:S0 - ssub_3:S3 subregs.
497 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
499 unsigned composeSubRegIndices(unsigned a, unsigned b) const {
502 return composeSubRegIndicesImpl(a, b);
505 /// Debugging helper: dump register in human readable form to dbgs() stream.
506 static void dumpReg(unsigned Reg, unsigned SubRegIndex = 0,
507 const TargetRegisterInfo* TRI = nullptr);
510 /// Overridden by TableGen in targets that have sub-registers.
511 virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
512 llvm_unreachable("Target has no sub-registers");
516 /// getCommonSuperRegClass - Find a common super-register class if it exists.
518 /// Find a register class, SuperRC and two sub-register indices, PreA and
521 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
523 /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
525 /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
527 /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
528 /// requirements, and there is no register class with a smaller spill size
529 /// that satisfies the requirements.
531 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
533 /// Either of the PreA and PreB sub-register indices may be returned as 0. In
534 /// that case, the returned register class will be a sub-class of the
535 /// corresponding argument register class.
537 /// The function returns NULL if no register class can be found.
539 const TargetRegisterClass*
540 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
541 const TargetRegisterClass *RCB, unsigned SubB,
542 unsigned &PreA, unsigned &PreB) const;
544 //===--------------------------------------------------------------------===//
545 // Register Class Information
548 /// Register class iterators
550 regclass_iterator regclass_begin() const { return RegClassBegin; }
551 regclass_iterator regclass_end() const { return RegClassEnd; }
553 unsigned getNumRegClasses() const {
554 return (unsigned)(regclass_end()-regclass_begin());
557 /// getRegClass - Returns the register class associated with the enumeration
558 /// value. See class MCOperandInfo.
559 const TargetRegisterClass *getRegClass(unsigned i) const {
560 assert(i < getNumRegClasses() && "Register Class ID out of range");
561 return RegClassBegin[i];
564 /// getRegClassName - Returns the name of the register class.
565 const char *getRegClassName(const TargetRegisterClass *Class) const {
566 return MCRegisterInfo::getRegClassName(Class->MC);
569 /// getCommonSubClass - find the largest common subclass of A and B. Return
570 /// NULL if there is no common subclass.
571 const TargetRegisterClass *
572 getCommonSubClass(const TargetRegisterClass *A,
573 const TargetRegisterClass *B) const;
575 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
576 /// values. If a target supports multiple different pointer register classes,
577 /// kind specifies which one is indicated.
578 virtual const TargetRegisterClass *
579 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
580 llvm_unreachable("Target didn't implement getPointerRegClass!");
583 /// getCrossCopyRegClass - Returns a legal register class to copy a register
584 /// in the specified class to or from. If it is possible to copy the register
585 /// directly without using a cross register class copy, return the specified
586 /// RC. Returns NULL if it is not possible to copy between a two registers of
587 /// the specified class.
588 virtual const TargetRegisterClass *
589 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
593 /// getLargestLegalSuperClass - Returns the largest super class of RC that is
594 /// legal to use in the current sub-target and has the same spill size.
595 /// The returned register class can be used to create virtual registers which
596 /// means that all its registers can be copied and spilled.
597 virtual const TargetRegisterClass*
598 getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
599 /// The default implementation is very conservative and doesn't allow the
600 /// register allocator to inflate register classes.
604 /// getRegPressureLimit - Return the register pressure "high water mark" for
605 /// the specific register class. The scheduler is in high register pressure
606 /// mode (for the specific register class) if it goes over the limit.
608 /// Note: this is the old register pressure model that relies on a manually
609 /// specified representative register class per value type.
610 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
611 MachineFunction &MF) const {
615 /// Get the weight in units of pressure for this register class.
616 virtual const RegClassWeight &getRegClassWeight(
617 const TargetRegisterClass *RC) const = 0;
619 /// Get the weight in units of pressure for this register unit.
620 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
622 /// Get the number of dimensions of register pressure.
623 virtual unsigned getNumRegPressureSets() const = 0;
625 /// Get the name of this register unit pressure set.
626 virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
628 /// Get the register unit pressure limit for this dimension.
629 /// This limit must be adjusted dynamically for reserved registers.
630 virtual unsigned getRegPressureSetLimit(unsigned Idx) const = 0;
632 /// Get the dimensions of register pressure impacted by this register class.
633 /// Returns a -1 terminated array of pressure set IDs.
634 virtual const int *getRegClassPressureSets(
635 const TargetRegisterClass *RC) const = 0;
637 /// Get the dimensions of register pressure impacted by this register unit.
638 /// Returns a -1 terminated array of pressure set IDs.
639 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
641 /// Get a list of 'hint' registers that the register allocator should try
642 /// first when allocating a physical register for the virtual register
643 /// VirtReg. These registers are effectively moved to the front of the
644 /// allocation order.
646 /// The Order argument is the allocation order for VirtReg's register class
647 /// as returned from RegisterClassInfo::getOrder(). The hint registers must
648 /// come from Order, and they must not be reserved.
650 /// The default implementation of this function can resolve
651 /// target-independent hints provided to MRI::setRegAllocationHint with
652 /// HintType == 0. Targets that override this function should defer to the
653 /// default implementation if they have no reason to change the allocation
654 /// order for VirtReg. There may be target-independent hints.
655 virtual void getRegAllocationHints(unsigned VirtReg,
656 ArrayRef<MCPhysReg> Order,
657 SmallVectorImpl<MCPhysReg> &Hints,
658 const MachineFunction &MF,
659 const VirtRegMap *VRM = nullptr) const;
661 /// avoidWriteAfterWrite - Return true if the register allocator should avoid
662 /// writing a register from RC in two consecutive instructions.
663 /// This can avoid pipeline stalls on certain architectures.
664 /// It does cause increased register pressure, though.
665 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
669 /// UpdateRegAllocHint - A callback to allow target a chance to update
670 /// register allocation hints when a register is "changed" (e.g. coalesced)
671 /// to another register. e.g. On ARM, some virtual registers should target
672 /// register pairs, if one of pair is coalesced to another register, the
673 /// allocation hint of the other half of the pair should be changed to point
674 /// to the new register.
675 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
676 MachineFunction &MF) const {
680 /// Allow the target to reverse allocation order of local live ranges. This
681 /// will generally allocate shorter local live ranges first. For targets with
682 /// many registers, this could reduce regalloc compile time by a large
683 /// factor. It is disabled by default for three reasons:
684 /// (1) Top-down allocation is simpler and easier to debug for targets that
685 /// don't benefit from reversing the order.
686 /// (2) Bottom-up allocation could result in poor evicition decisions on some
687 /// targets affecting the performance of compiled code.
688 /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
689 virtual bool reverseLocalAssignment() const { return false; }
691 /// Allow the target to override the cost of using a callee-saved register for
692 /// the first time. Default value of 0 means we will use a callee-saved
693 /// register if it is available.
694 virtual unsigned getCSRFirstUseCost() const { return 0; }
696 /// requiresRegisterScavenging - returns true if the target requires (and can
697 /// make use of) the register scavenger.
698 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
702 /// useFPForScavengingIndex - returns true if the target wants to use
703 /// frame pointer based accesses to spill to the scavenger emergency spill
705 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
709 /// requiresFrameIndexScavenging - returns true if the target requires post
710 /// PEI scavenging of registers for materializing frame index constants.
711 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
715 /// requiresVirtualBaseRegisters - Returns true if the target wants the
716 /// LocalStackAllocation pass to be run and virtual base registers
717 /// used for more efficient stack access.
718 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
722 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
723 /// the stack frame of the given function for the specified register. e.g. On
724 /// x86, if the frame register is required, the first fixed stack object is
725 /// reserved as its spill slot. This tells PEI not to create a new stack frame
726 /// object for the given register. It should be called only after
727 /// processFunctionBeforeCalleeSavedScan().
728 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
729 int &FrameIdx) const {
733 /// trackLivenessAfterRegAlloc - returns true if the live-ins should be tracked
734 /// after register allocation.
735 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
739 /// needsStackRealignment - true if storage within the function requires the
740 /// stack pointer to be aligned more than the normal calling convention calls
742 virtual bool needsStackRealignment(const MachineFunction &MF) const {
746 /// getFrameIndexInstrOffset - Get the offset from the referenced frame
747 /// index in the instruction, if there is one.
748 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
753 /// needsFrameBaseReg - Returns true if the instruction's frame index
754 /// reference would be better served by a base register other than FP
755 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
756 /// references it should create new base registers for.
757 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
761 /// materializeFrameBaseRegister - Insert defining instruction(s) for
762 /// BaseReg to be a pointer to FrameIdx before insertion point I.
763 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
764 unsigned BaseReg, int FrameIdx,
765 int64_t Offset) const {
766 llvm_unreachable("materializeFrameBaseRegister does not exist on this "
770 /// resolveFrameIndex - Resolve a frame index operand of an instruction
771 /// to reference the indicated base register plus offset instead.
772 virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
773 int64_t Offset) const {
774 llvm_unreachable("resolveFrameIndex does not exist on this target");
777 /// isFrameOffsetLegal - Determine whether a given offset immediate is
778 /// encodable to resolve a frame index.
779 virtual bool isFrameOffsetLegal(const MachineInstr *MI,
780 int64_t Offset) const {
781 llvm_unreachable("isFrameOffsetLegal does not exist on this target");
785 /// saveScavengerRegister - Spill the register so it can be used by the
786 /// register scavenger. Return true if the register was spilled, false
787 /// otherwise. If this function does not spill the register, the scavenger
788 /// will instead spill it to the emergency spill slot.
790 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
791 MachineBasicBlock::iterator I,
792 MachineBasicBlock::iterator &UseMI,
793 const TargetRegisterClass *RC,
794 unsigned Reg) const {
798 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
799 /// frame indices from instructions which may use them. The instruction
800 /// referenced by the iterator contains an MO_FrameIndex operand which must be
801 /// eliminated by this method. This method may modify or replace the
802 /// specified instruction, as long as it keeps the iterator pointing at the
803 /// finished product. SPAdj is the SP adjustment due to call frame setup
804 /// instruction. FIOperandNum is the FI operand number.
805 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
806 int SPAdj, unsigned FIOperandNum,
807 RegScavenger *RS = nullptr) const = 0;
809 //===--------------------------------------------------------------------===//
812 /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true.
813 virtual bool shouldCoalesce(MachineInstr *MI,
814 const TargetRegisterClass *SrcRC,
816 const TargetRegisterClass *DstRC,
818 const TargetRegisterClass *NewRC) const
821 //===--------------------------------------------------------------------===//
822 /// Debug information queries.
824 /// getFrameRegister - This method should return the register used as a base
825 /// for values allocated in the current stack frame.
826 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
830 //===----------------------------------------------------------------------===//
831 // SuperRegClassIterator
832 //===----------------------------------------------------------------------===//
834 // Iterate over the possible super-registers for a given register class. The
835 // iterator will visit a list of pairs (Idx, Mask) corresponding to the
836 // possible classes of super-registers.
838 // Each bit mask will have at least one set bit, and each set bit in Mask
839 // corresponds to a SuperRC such that:
841 // For all Reg in SuperRC: Reg:Idx is in RC.
843 // The iterator can include (O, RC->getSubClassMask()) as the first entry which
844 // also satisfies the above requirement, assuming Reg:0 == Reg.
846 class SuperRegClassIterator {
847 const unsigned RCMaskWords;
850 const uint32_t *Mask;
853 /// Create a SuperRegClassIterator that visits all the super-register classes
854 /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
855 SuperRegClassIterator(const TargetRegisterClass *RC,
856 const TargetRegisterInfo *TRI,
857 bool IncludeSelf = false)
858 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
860 Idx(RC->getSuperRegIndices()),
861 Mask(RC->getSubClassMask()) {
866 /// Returns true if this iterator is still pointing at a valid entry.
867 bool isValid() const { return Idx; }
869 /// Returns the current sub-register index.
870 unsigned getSubReg() const { return SubReg; }
872 /// Returns the bit mask if register classes that getSubReg() projects into
874 const uint32_t *getMask() const { return Mask; }
876 /// Advance iterator to the next entry.
878 assert(isValid() && "Cannot move iterator past end.");
886 // This is useful when building IndexedMaps keyed on virtual registers
887 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
888 unsigned operator()(unsigned Reg) const {
889 return TargetRegisterInfo::virtReg2Index(Reg);
893 /// PrintReg - Helper class for printing registers on a raw_ostream.
894 /// Prints virtual and physical registers with or without a TRI instance.
897 /// %noreg - NoRegister
898 /// %vreg5 - a virtual register.
899 /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
900 /// %EAX - a physical register
901 /// %physreg17 - a physical register when no TRI instance given.
903 /// Usage: OS << PrintReg(Reg, TRI) << '\n';
906 const TargetRegisterInfo *TRI;
910 explicit PrintReg(unsigned reg, const TargetRegisterInfo *tri = nullptr,
912 : TRI(tri), Reg(reg), SubIdx(subidx) {}
913 void print(raw_ostream&) const;
916 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
921 /// PrintRegUnit - Helper class for printing register units on a raw_ostream.
923 /// Register units are named after their root registers:
925 /// AL - Single root.
926 /// FP0~ST7 - Dual roots.
928 /// Usage: OS << PrintRegUnit(Unit, TRI) << '\n';
932 const TargetRegisterInfo *TRI;
935 PrintRegUnit(unsigned unit, const TargetRegisterInfo *tri)
936 : TRI(tri), Unit(unit) {}
937 void print(raw_ostream&) const;
940 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintRegUnit &PR) {
945 /// PrintVRegOrUnit - It is often convenient to track virtual registers and
946 /// physical register units in the same list.
947 class PrintVRegOrUnit : protected PrintRegUnit {
949 PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *tri)
950 : PrintRegUnit(VRegOrUnit, tri) {}
951 void print(raw_ostream&) const;
954 static inline raw_ostream &operator<<(raw_ostream &OS,
955 const PrintVRegOrUnit &PR) {
960 } // End llvm namespace