1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/DenseSet.h"
30 class MachineFunction;
32 template<class T> class SmallVectorImpl;
35 class TargetRegisterClass : public MCRegisterClass {
37 typedef const EVT* vt_iterator;
38 typedef const TargetRegisterClass* const * sc_iterator;
40 const vt_iterator VTs;
41 const sc_iterator SubClasses;
42 const sc_iterator SuperClasses;
43 const sc_iterator SubRegClasses;
44 const sc_iterator SuperRegClasses;
46 TargetRegisterClass(unsigned id, const char *name, const EVT *vts,
47 const TargetRegisterClass * const *subcs,
48 const TargetRegisterClass * const *supcs,
49 const TargetRegisterClass * const *subregcs,
50 const TargetRegisterClass * const *superregcs,
51 unsigned RS, unsigned Al, int CC, bool Allocable,
52 iterator RB, iterator RE)
53 : MCRegisterClass(id, name, RS, Al, CC, Allocable, RB, RE),
54 VTs(vts), SubClasses(subcs), SuperClasses(supcs), SubRegClasses(subregcs),
55 SuperRegClasses(superregcs) {}
57 virtual ~TargetRegisterClass() {} // Allow subclasses
59 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
61 bool hasType(EVT vt) const {
62 for(int i = 0; VTs[i] != MVT::Other; ++i)
68 /// vt_begin / vt_end - Loop over all of the value types that can be
69 /// represented by values in this register class.
70 vt_iterator vt_begin() const {
74 vt_iterator vt_end() const {
76 while (*I != MVT::Other) ++I;
80 /// subregclasses_begin / subregclasses_end - Loop over all of
81 /// the subreg register classes of this register class.
82 sc_iterator subregclasses_begin() const {
86 sc_iterator subregclasses_end() const {
87 sc_iterator I = SubRegClasses;
88 while (*I != NULL) ++I;
92 /// getSubRegisterRegClass - Return the register class of subregisters with
93 /// index SubIdx, or NULL if no such class exists.
94 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
95 assert(SubIdx>0 && "Invalid subregister index");
96 return SubRegClasses[SubIdx-1];
99 /// superregclasses_begin / superregclasses_end - Loop over all of
100 /// the superreg register classes of this register class.
101 sc_iterator superregclasses_begin() const {
102 return SuperRegClasses;
105 sc_iterator superregclasses_end() const {
106 sc_iterator I = SuperRegClasses;
107 while (*I != NULL) ++I;
111 /// hasSubClass - return true if the specified TargetRegisterClass
112 /// is a proper subset of this TargetRegisterClass.
113 bool hasSubClass(const TargetRegisterClass *cs) const {
114 for (int i = 0; SubClasses[i] != NULL; ++i)
115 if (SubClasses[i] == cs)
120 /// hasSubClassEq - Returns true if RC is a subclass of or equal to this
122 bool hasSubClassEq(const TargetRegisterClass *RC) const {
123 return RC == this || hasSubClass(RC);
126 /// subclasses_begin / subclasses_end - Loop over all of the classes
127 /// that are proper subsets of this register class.
128 sc_iterator subclasses_begin() const {
132 sc_iterator subclasses_end() const {
133 sc_iterator I = SubClasses;
134 while (*I != NULL) ++I;
138 /// hasSuperClass - return true if the specified TargetRegisterClass is a
139 /// proper superset of this TargetRegisterClass.
140 bool hasSuperClass(const TargetRegisterClass *cs) const {
141 for (int i = 0; SuperClasses[i] != NULL; ++i)
142 if (SuperClasses[i] == cs)
147 /// hasSuperClassEq - Returns true if RC is a superclass of or equal to this
149 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
150 return RC == this || hasSuperClass(RC);
153 /// superclasses_begin / superclasses_end - Loop over all of the classes
154 /// that are proper supersets of this register class.
155 sc_iterator superclasses_begin() const {
159 sc_iterator superclasses_end() const {
160 sc_iterator I = SuperClasses;
161 while (*I != NULL) ++I;
165 /// isASubClass - return true if this TargetRegisterClass is a subset
166 /// class of at least one other TargetRegisterClass.
167 bool isASubClass() const {
168 return SuperClasses[0] != 0;
171 /// getRawAllocationOrder - Returns the preferred order for allocating
172 /// registers from this register class in MF. The raw order comes directly
173 /// from the .td file and may include reserved registers that are not
174 /// allocatable. Register allocators should also make sure to allocate
175 /// callee-saved registers only after all the volatiles are used. The
176 /// RegisterClassInfo class provides filtered allocation orders with
177 /// callee-saved registers moved to the end.
179 /// The MachineFunction argument can be used to tune the allocatable
180 /// registers based on the characteristics of the function, subtarget, or
183 /// By default, this method returns all registers in the class.
186 ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const {
187 return makeArrayRef(begin(), getNumRegs());
191 /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
192 /// registers. These are used by codegen, not by MC.
193 struct TargetRegisterInfoDesc {
194 unsigned CostPerUse; // Extra cost of instructions using register.
195 bool inAllocatableClass; // Register belongs to an allocatable regclass.
198 /// TargetRegisterInfo base class - We assume that the target defines a static
199 /// array of TargetRegisterDesc objects that represent all of the machine
200 /// registers that the target has. As such, we simply have to track a pointer
201 /// to this array so that we can turn register number into a register
204 class TargetRegisterInfo : public MCRegisterInfo {
206 typedef const TargetRegisterClass * const * regclass_iterator;
208 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
209 const char *const *SubRegIndexNames; // Names of subreg indexes.
210 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
213 TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
214 regclass_iterator RegClassBegin,
215 regclass_iterator RegClassEnd,
216 const char *const *subregindexnames);
217 virtual ~TargetRegisterInfo();
220 // Register numbers can represent physical registers, virtual registers, and
221 // sometimes stack slots. The unsigned values are divided into these ranges:
223 // 0 Not a register, can be used as a sentinel.
224 // [1;2^30) Physical registers assigned by TableGen.
225 // [2^30;2^31) Stack slots. (Rarely used.)
226 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
228 // Further sentinels can be allocated from the small negative integers.
229 // DenseMapInfo<unsigned> uses -1u and -2u.
231 /// isStackSlot - Sometimes it is useful the be able to store a non-negative
232 /// frame index in a variable that normally holds a register. isStackSlot()
233 /// returns true if Reg is in the range used for stack slots.
235 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
236 /// slots, so if a variable may contains a stack slot, always check
237 /// isStackSlot() first.
239 static bool isStackSlot(unsigned Reg) {
240 return int(Reg) >= (1 << 30);
243 /// stackSlot2Index - Compute the frame index from a register value
244 /// representing a stack slot.
245 static int stackSlot2Index(unsigned Reg) {
246 assert(isStackSlot(Reg) && "Not a stack slot");
247 return int(Reg - (1u << 30));
250 /// index2StackSlot - Convert a non-negative frame index to a stack slot
252 static unsigned index2StackSlot(int FI) {
253 assert(FI >= 0 && "Cannot hold a negative frame index.");
254 return FI + (1u << 30);
257 /// isPhysicalRegister - Return true if the specified register number is in
258 /// the physical register namespace.
259 static bool isPhysicalRegister(unsigned Reg) {
260 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
264 /// isVirtualRegister - Return true if the specified register number is in
265 /// the virtual register namespace.
266 static bool isVirtualRegister(unsigned Reg) {
267 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
271 /// virtReg2Index - Convert a virtual register number to a 0-based index.
272 /// The first virtual register in a function will get the index 0.
273 static unsigned virtReg2Index(unsigned Reg) {
274 assert(isVirtualRegister(Reg) && "Not a virtual register");
275 return Reg & ~(1u << 31);
278 /// index2VirtReg - Convert a 0-based index to a virtual register number.
279 /// This is the inverse operation of VirtReg2IndexFunctor below.
280 static unsigned index2VirtReg(unsigned Index) {
281 return Index | (1u << 31);
284 /// getMinimalPhysRegClass - Returns the Register Class of a physical
285 /// register of the given type, picking the most sub register class of
286 /// the right type that contains this physreg.
287 const TargetRegisterClass *
288 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
290 /// getAllocatableSet - Returns a bitset indexed by register number
291 /// indicating if a register is allocatable or not. If a register class is
292 /// specified, returns the subset for the class.
293 BitVector getAllocatableSet(const MachineFunction &MF,
294 const TargetRegisterClass *RC = NULL) const;
296 /// getCostPerUse - Return the additional cost of using this register instead
297 /// of other registers in its class.
298 unsigned getCostPerUse(unsigned RegNo) const {
299 return InfoDesc[RegNo].CostPerUse;
302 /// isInAllocatableClass - Return true if the register is in the allocation
303 /// of any register class.
304 bool isInAllocatableClass(unsigned RegNo) const {
305 return InfoDesc[RegNo].inAllocatableClass;
308 /// getSubRegIndexName - Return the human-readable symbolic target-specific
309 /// name for the specified SubRegIndex.
310 const char *getSubRegIndexName(unsigned SubIdx) const {
311 assert(SubIdx && "This is not a subregister index");
312 return SubRegIndexNames[SubIdx-1];
315 /// regsOverlap - Returns true if the two registers are equal or alias each
316 /// other. The registers may be virtual register.
317 bool regsOverlap(unsigned regA, unsigned regB) const {
318 if (regA == regB) return true;
319 if (isVirtualRegister(regA) || isVirtualRegister(regB))
321 for (const unsigned *regList = getOverlaps(regA)+1; *regList; ++regList) {
322 if (*regList == regB) return true;
327 /// isSubRegister - Returns true if regB is a sub-register of regA.
329 bool isSubRegister(unsigned regA, unsigned regB) const {
330 return isSuperRegister(regB, regA);
333 /// isSuperRegister - Returns true if regB is a super-register of regA.
335 bool isSuperRegister(unsigned regA, unsigned regB) const {
336 for (const unsigned *regList = getSuperRegisters(regA); *regList;++regList){
337 if (*regList == regB) return true;
342 /// getCalleeSavedRegs - Return a null-terminated list of all of the
343 /// callee saved registers on this target. The register should be in the
344 /// order of desired callee-save stack frame offset. The first register is
345 /// closed to the incoming stack pointer if stack grows down, and vice versa.
346 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
350 /// getReservedRegs - Returns a bitset indexed by physical register number
351 /// indicating if a register is a special register that has particular uses
352 /// and should be considered unavailable at all times, e.g. SP, RA. This is
353 /// used by register scavenger to determine what registers are free.
354 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
356 /// getSubReg - Returns the physical register number of sub-register "Index"
357 /// for physical register RegNo. Return zero if the sub-register does not
359 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
361 /// getSubRegIndex - For a given register pair, return the sub-register index
362 /// if the second register is a sub-register of the first. Return zero
364 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0;
366 /// getMatchingSuperReg - Return a super-register of the specified register
367 /// Reg so its sub-register of index SubIdx is Reg.
368 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
369 const TargetRegisterClass *RC) const {
370 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
371 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
376 /// canCombineSubRegIndices - Given a register class and a list of
377 /// subregister indices, return true if it's possible to combine the
378 /// subregister indices into one that corresponds to a larger
379 /// subregister. Return the new subregister index by reference. Note the
380 /// new index may be zero if the given subregisters can be combined to
381 /// form the whole register.
382 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
383 SmallVectorImpl<unsigned> &SubIndices,
384 unsigned &NewSubIdx) const {
388 /// getMatchingSuperRegClass - Return a subclass of the specified register
389 /// class A so that each register in it has a sub-register of the
390 /// specified sub-register index which is in the specified register class B.
391 virtual const TargetRegisterClass *
392 getMatchingSuperRegClass(const TargetRegisterClass *A,
393 const TargetRegisterClass *B, unsigned Idx) const {
397 /// composeSubRegIndices - Return the subregister index you get from composing
398 /// two subregister indices.
400 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
401 /// returns c. Note that composeSubRegIndices does not tell you about illegal
402 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
403 /// b, composeSubRegIndices doesn't tell you.
405 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
406 /// ssub_0:S0 - ssub_3:S3 subregs.
407 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
409 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const {
410 // This default implementation is correct for most targets.
414 //===--------------------------------------------------------------------===//
415 // Register Class Information
418 /// Register class iterators
420 regclass_iterator regclass_begin() const { return RegClassBegin; }
421 regclass_iterator regclass_end() const { return RegClassEnd; }
423 unsigned getNumRegClasses() const {
424 return (unsigned)(regclass_end()-regclass_begin());
427 /// getRegClass - Returns the register class associated with the enumeration
428 /// value. See class MCOperandInfo.
429 const TargetRegisterClass *getRegClass(unsigned i) const {
430 assert(i < getNumRegClasses() && "Register Class ID out of range");
431 return RegClassBegin[i];
434 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
435 /// values. If a target supports multiple different pointer register classes,
436 /// kind specifies which one is indicated.
437 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
438 assert(0 && "Target didn't implement getPointerRegClass!");
439 return 0; // Must return a value in order to compile with VS 2005
442 /// getCrossCopyRegClass - Returns a legal register class to copy a register
443 /// in the specified class to or from. If it is possible to copy the register
444 /// directly without using a cross register class copy, return the specified
445 /// RC. Returns NULL if it is not possible to copy between a two registers of
446 /// the specified class.
447 virtual const TargetRegisterClass *
448 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
452 /// getLargestLegalSuperClass - Returns the largest super class of RC that is
453 /// legal to use in the current sub-target and has the same spill size.
454 /// The returned register class can be used to create virtual registers which
455 /// means that all its registers can be copied and spilled.
456 virtual const TargetRegisterClass*
457 getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
458 /// The default implementation is very conservative and doesn't allow the
459 /// register allocator to inflate register classes.
463 /// getRegPressureLimit - Return the register pressure "high water mark" for
464 /// the specific register class. The scheduler is in high register pressure
465 /// mode (for the specific register class) if it goes over the limit.
466 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
467 MachineFunction &MF) const {
471 /// getRawAllocationOrder - Returns the register allocation order for a
472 /// specified register class with a target-dependent hint. The returned list
473 /// may contain reserved registers that cannot be allocated.
475 /// Register allocators need only call this function to resolve
476 /// target-dependent hints, but it should work without hinting as well.
477 virtual ArrayRef<unsigned>
478 getRawAllocationOrder(const TargetRegisterClass *RC,
479 unsigned HintType, unsigned HintReg,
480 const MachineFunction &MF) const {
481 return RC->getRawAllocationOrder(MF);
484 /// ResolveRegAllocHint - Resolves the specified register allocation hint
485 /// to a physical register. Returns the physical register if it is successful.
486 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
487 const MachineFunction &MF) const {
488 if (Type == 0 && Reg && isPhysicalRegister(Reg))
493 /// avoidWriteAfterWrite - Return true if the register allocator should avoid
494 /// writing a register from RC in two consecutive instructions.
495 /// This can avoid pipeline stalls on certain architectures.
496 /// It does cause increased register pressure, though.
497 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
501 /// UpdateRegAllocHint - A callback to allow target a chance to update
502 /// register allocation hints when a register is "changed" (e.g. coalesced)
503 /// to another register. e.g. On ARM, some virtual registers should target
504 /// register pairs, if one of pair is coalesced to another register, the
505 /// allocation hint of the other half of the pair should be changed to point
506 /// to the new register.
507 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
508 MachineFunction &MF) const {
512 /// requiresRegisterScavenging - returns true if the target requires (and can
513 /// make use of) the register scavenger.
514 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
518 /// useFPForScavengingIndex - returns true if the target wants to use
519 /// frame pointer based accesses to spill to the scavenger emergency spill
521 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
525 /// requiresFrameIndexScavenging - returns true if the target requires post
526 /// PEI scavenging of registers for materializing frame index constants.
527 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
531 /// requiresVirtualBaseRegisters - Returns true if the target wants the
532 /// LocalStackAllocation pass to be run and virtual base registers
533 /// used for more efficient stack access.
534 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
538 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
539 /// the stack frame of the given function for the specified register. e.g. On
540 /// x86, if the frame register is required, the first fixed stack object is
541 /// reserved as its spill slot. This tells PEI not to create a new stack frame
542 /// object for the given register. It should be called only after
543 /// processFunctionBeforeCalleeSavedScan().
544 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
545 int &FrameIdx) const {
549 /// needsStackRealignment - true if storage within the function requires the
550 /// stack pointer to be aligned more than the normal calling convention calls
552 virtual bool needsStackRealignment(const MachineFunction &MF) const {
556 /// getFrameIndexInstrOffset - Get the offset from the referenced frame
557 /// index in the instruction, if there is one.
558 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
563 /// needsFrameBaseReg - Returns true if the instruction's frame index
564 /// reference would be better served by a base register other than FP
565 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
566 /// references it should create new base registers for.
567 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
571 /// materializeFrameBaseRegister - Insert defining instruction(s) for
572 /// BaseReg to be a pointer to FrameIdx before insertion point I.
573 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
574 unsigned BaseReg, int FrameIdx,
575 int64_t Offset) const {
576 assert(0 && "materializeFrameBaseRegister does not exist on this target");
579 /// resolveFrameIndex - Resolve a frame index operand of an instruction
580 /// to reference the indicated base register plus offset instead.
581 virtual void resolveFrameIndex(MachineBasicBlock::iterator I,
582 unsigned BaseReg, int64_t Offset) const {
583 assert(0 && "resolveFrameIndex does not exist on this target");
586 /// isFrameOffsetLegal - Determine whether a given offset immediate is
587 /// encodable to resolve a frame index.
588 virtual bool isFrameOffsetLegal(const MachineInstr *MI,
589 int64_t Offset) const {
590 assert(0 && "isFrameOffsetLegal does not exist on this target");
591 return false; // Must return a value in order to compile with VS 2005
594 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
595 /// code insertion to eliminate call frame setup and destroy pseudo
596 /// instructions (but only if the Target is using them). It is responsible
597 /// for eliminating these instructions, replacing them with concrete
598 /// instructions. This method need only be implemented if using call frame
599 /// setup/destroy pseudo instructions.
602 eliminateCallFramePseudoInstr(MachineFunction &MF,
603 MachineBasicBlock &MBB,
604 MachineBasicBlock::iterator MI) const {
605 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
609 /// saveScavengerRegister - Spill the register so it can be used by the
610 /// register scavenger. Return true if the register was spilled, false
611 /// otherwise. If this function does not spill the register, the scavenger
612 /// will instead spill it to the emergency spill slot.
614 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
615 MachineBasicBlock::iterator I,
616 MachineBasicBlock::iterator &UseMI,
617 const TargetRegisterClass *RC,
618 unsigned Reg) const {
622 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
623 /// frame indices from instructions which may use them. The instruction
624 /// referenced by the iterator contains an MO_FrameIndex operand which must be
625 /// eliminated by this method. This method may modify or replace the
626 /// specified instruction, as long as it keeps the iterator pointing at the
627 /// finished product. SPAdj is the SP adjustment due to call frame setup
629 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
630 int SPAdj, RegScavenger *RS=NULL) const = 0;
632 //===--------------------------------------------------------------------===//
633 /// Debug information queries.
635 /// getFrameRegister - This method should return the register used as a base
636 /// for values allocated in the current stack frame.
637 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
639 /// getCompactUnwindRegNum - This function maps the register to the number for
640 /// compact unwind encoding. Return -1 if the register isn't valid.
641 virtual int getCompactUnwindRegNum(unsigned, bool) const {
647 // This is useful when building IndexedMaps keyed on virtual registers
648 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
649 unsigned operator()(unsigned Reg) const {
650 return TargetRegisterInfo::virtReg2Index(Reg);
654 /// getCommonSubClass - find the largest common subclass of A and B. Return NULL
655 /// if there is no common subclass.
656 const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A,
657 const TargetRegisterClass *B);
659 /// PrintReg - Helper class for printing registers on a raw_ostream.
660 /// Prints virtual and physical registers with or without a TRI instance.
663 /// %noreg - NoRegister
664 /// %vreg5 - a virtual register.
665 /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
666 /// %EAX - a physical register
667 /// %physreg17 - a physical register when no TRI instance given.
669 /// Usage: OS << PrintReg(Reg, TRI) << '\n';
672 const TargetRegisterInfo *TRI;
676 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0)
677 : TRI(tri), Reg(reg), SubIdx(subidx) {}
678 void print(raw_ostream&) const;
681 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
686 } // End llvm namespace