1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/CodeGen/RuntimeLibcalls.h"
35 class TargetRegisterClass;
39 class MachineBasicBlock;
43 //===----------------------------------------------------------------------===//
44 /// TargetLowering - This class defines information used to lower LLVM code to
45 /// legal SelectionDAG operators that the target instruction selector can accept
48 /// This class also defines callbacks that targets must implement to lower
49 /// target-specific constructs to SelectionDAG operators.
51 class TargetLowering {
53 /// LegalizeAction - This enum indicates whether operations are valid for a
54 /// target, and if not, what action should be used to make them valid.
56 Legal, // The target natively supports this operation.
57 Promote, // This operation should be executed in a larger type.
58 Expand, // Try to expand this to other ops, otherwise use a libcall.
59 Custom // Use the LowerOperation hook to implement custom lowering.
62 enum OutOfRangeShiftAmount {
63 Undefined, // Oversized shift amounts are undefined (default).
64 Mask, // Shift amounts are auto masked (anded) to value size.
65 Extend // Oversized shift pulls in zeros or sign bits.
68 enum SetCCResultValue {
69 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend.
70 ZeroOrOneSetCCResult, // SetCC returns a zero extended result.
71 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result.
74 enum SchedPreference {
75 SchedulingForLatency, // Scheduling for shortest total latency.
76 SchedulingForRegPressure // Scheduling for lowest register pressure.
79 TargetLowering(TargetMachine &TM);
80 virtual ~TargetLowering();
82 TargetMachine &getTargetMachine() const { return TM; }
83 const TargetData *getTargetData() const { return TD; }
85 bool isLittleEndian() const { return IsLittleEndian; }
86 MVT::ValueType getPointerTy() const { return PointerTy; }
87 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
88 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
90 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
92 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
94 /// isSelectExpensive - Return true if the select operation is expensive for
96 bool isSelectExpensive() const { return SelectIsExpensive; }
98 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
99 /// a sequence of several shifts, adds, and multiplies for this target.
100 bool isIntDivCheap() const { return IntDivIsCheap; }
102 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
104 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
106 /// getSetCCResultTy - Return the ValueType of the result of setcc operations.
108 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; }
110 /// getSetCCResultContents - For targets without boolean registers, this flag
111 /// returns information about the contents of the high-bits in the setcc
113 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;}
115 /// getSchedulingPreference - Return target scheduling preference.
116 SchedPreference getSchedulingPreference() const {
117 return SchedPreferenceInfo;
120 /// getRegClassFor - Return the register class that should be used for the
121 /// specified value type. This may only be called on legal types.
122 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const {
123 assert(!MVT::isExtendedVT(VT));
124 TargetRegisterClass *RC = RegClassForVT[VT];
125 assert(RC && "This value type is not natively supported!");
129 /// isTypeLegal - Return true if the target has native support for the
130 /// specified value type. This means that it has a register that directly
131 /// holds it without promotions or expansions.
132 bool isTypeLegal(MVT::ValueType VT) const {
133 return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0;
136 class ValueTypeActionImpl {
137 /// ValueTypeActions - This is a bitvector that contains two bits for each
138 /// value type, where the two bits correspond to the LegalizeAction enum.
139 /// This can be queried with "getTypeAction(VT)".
140 uint32_t ValueTypeActions[2];
142 ValueTypeActionImpl() {
143 ValueTypeActions[0] = ValueTypeActions[1] = 0;
145 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
146 ValueTypeActions[0] = RHS.ValueTypeActions[0];
147 ValueTypeActions[1] = RHS.ValueTypeActions[1];
150 LegalizeAction getTypeAction(MVT::ValueType VT) const {
151 if (MVT::isExtendedVT(VT)) return Expand;
152 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3);
154 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) {
155 assert(!MVT::isExtendedVT(VT));
156 assert(unsigned(VT >> 4) <
157 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0]));
158 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31);
162 const ValueTypeActionImpl &getValueTypeActions() const {
163 return ValueTypeActions;
166 /// getTypeAction - Return how we should legalize values of this type, either
167 /// it is already legal (return 'Legal') or we need to promote it to a larger
168 /// type (return 'Promote'), or we need to expand it into multiple registers
169 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
170 LegalizeAction getTypeAction(MVT::ValueType VT) const {
171 return ValueTypeActions.getTypeAction(VT);
174 /// getTypeToTransformTo - For types supported by the target, this is an
175 /// identity function. For types that must be promoted to larger types, this
176 /// returns the larger type to promote to. For integer types that are larger
177 /// than the largest integer register, this contains one step in the expansion
178 /// to get to the smaller register. For illegal floating point types, this
179 /// returns the integer type to transform to.
180 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
181 if (MVT::isExtendedVT(VT))
182 return MVT::getVectorType(MVT::getVectorElementType(VT),
183 MVT::getVectorNumElements(VT) / 2);
185 return TransformToType[VT];
188 /// getTypeToExpandTo - For types supported by the target, this is an
189 /// identity function. For types that must be expanded (i.e. integer types
190 /// that are larger than the largest integer register or illegal floating
191 /// point types), this returns the largest legal type it will be expanded to.
192 MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const {
193 assert(!MVT::isExtendedVT(VT));
195 switch (getTypeAction(VT)) {
199 VT = getTypeToTransformTo(VT);
202 assert(false && "Type is not legal nor is it to be expanded!");
209 /// getVectorTypeBreakdown - Vector types are broken down into some number of
210 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
211 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
212 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
214 /// This method returns the number of registers needed, and the VT for each
215 /// register. It also returns the VT and quantity of the intermediate values
216 /// before they are promoted/expanded.
218 unsigned getVectorTypeBreakdown(MVT::ValueType VT,
219 MVT::ValueType &IntermediateVT,
220 unsigned &NumIntermediates,
221 MVT::ValueType &RegisterVT) const;
223 typedef std::vector<double>::const_iterator legal_fpimm_iterator;
224 legal_fpimm_iterator legal_fpimm_begin() const {
225 return LegalFPImmediates.begin();
227 legal_fpimm_iterator legal_fpimm_end() const {
228 return LegalFPImmediates.end();
231 /// isShuffleMaskLegal - Targets can use this to indicate that they only
232 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
233 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
234 /// are assumed to be legal.
235 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
239 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
240 /// used by Targets can use this to indicate if there is a suitable
241 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
243 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
245 SelectionDAG &DAG) const {
249 /// getOperationAction - Return how this operation should be treated: either
250 /// it is legal, needs to be promoted to a larger size, needs to be
251 /// expanded to some other code sequence, or the target has a custom expander
253 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
254 if (MVT::isExtendedVT(VT)) return Expand;
255 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
258 /// isOperationLegal - Return true if the specified operation is legal on this
260 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
261 return getOperationAction(Op, VT) == Legal ||
262 getOperationAction(Op, VT) == Custom;
265 /// getLoadXAction - Return how this load with extension should be treated:
266 /// either it is legal, needs to be promoted to a larger size, needs to be
267 /// expanded to some other code sequence, or the target has a custom expander
269 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const {
270 if (MVT::isExtendedVT(VT)) return Expand;
271 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3);
274 /// isLoadXLegal - Return true if the specified load with extension is legal
276 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const {
277 return getLoadXAction(LType, VT) == Legal ||
278 getLoadXAction(LType, VT) == Custom;
281 /// getStoreXAction - Return how this store with truncation should be treated:
282 /// either it is legal, needs to be promoted to a larger size, needs to be
283 /// expanded to some other code sequence, or the target has a custom expander
285 LegalizeAction getStoreXAction(MVT::ValueType VT) const {
286 if (MVT::isExtendedVT(VT)) return Expand;
287 return (LegalizeAction)((StoreXActions >> (2*VT)) & 3);
290 /// isStoreXLegal - Return true if the specified store with truncation is
291 /// legal on this target.
292 bool isStoreXLegal(MVT::ValueType VT) const {
293 return getStoreXAction(VT) == Legal || getStoreXAction(VT) == Custom;
296 /// getIndexedLoadAction - Return how the indexed load should be treated:
297 /// either it is legal, needs to be promoted to a larger size, needs to be
298 /// expanded to some other code sequence, or the target has a custom expander
301 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const {
302 if (MVT::isExtendedVT(VT)) return Expand;
303 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3);
306 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
308 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const {
309 return getIndexedLoadAction(IdxMode, VT) == Legal ||
310 getIndexedLoadAction(IdxMode, VT) == Custom;
313 /// getIndexedStoreAction - Return how the indexed store should be treated:
314 /// either it is legal, needs to be promoted to a larger size, needs to be
315 /// expanded to some other code sequence, or the target has a custom expander
318 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const {
319 if (MVT::isExtendedVT(VT)) return Expand;
320 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3);
323 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
325 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const {
326 return getIndexedStoreAction(IdxMode, VT) == Legal ||
327 getIndexedStoreAction(IdxMode, VT) == Custom;
330 /// getTypeToPromoteTo - If the action for this operation is to promote, this
331 /// method returns the ValueType to promote to.
332 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
333 assert(getOperationAction(Op, VT) == Promote &&
334 "This operation isn't promoted!");
336 // See if this has an explicit type specified.
337 std::map<std::pair<unsigned, MVT::ValueType>,
338 MVT::ValueType>::const_iterator PTTI =
339 PromoteToType.find(std::make_pair(Op, VT));
340 if (PTTI != PromoteToType.end()) return PTTI->second;
342 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) &&
343 "Cannot autopromote this type, add it with AddPromotedToType.");
345 MVT::ValueType NVT = VT;
347 NVT = (MVT::ValueType)(NVT+1);
348 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid &&
349 "Didn't find type to promote to!");
350 } while (!isTypeLegal(NVT) ||
351 getOperationAction(Op, NVT) == Promote);
355 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type.
356 /// This is fixed by the LLVM operations except for the pointer size. If
357 /// AllowUnknown is true, this will return MVT::Other for types with no MVT
358 /// counterpart (e.g. structs), otherwise it will assert.
359 MVT::ValueType getValueType(const Type *Ty, bool AllowUnknown = false) const {
360 MVT::ValueType VT = MVT::getValueType(Ty, AllowUnknown);
361 return VT == MVT::iPTR ? PointerTy : VT;
364 /// getRegisterType - Return the type of registers that this ValueType will
365 /// eventually require.
366 MVT::ValueType getRegisterType(MVT::ValueType VT) const {
367 if (!MVT::isExtendedVT(VT))
368 return RegisterTypeForVT[VT];
370 MVT::ValueType VT1, RegisterVT;
371 unsigned NumIntermediates;
372 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
376 /// getNumRegisters - Return the number of registers that this ValueType will
377 /// eventually require. This is one for any types promoted to live in larger
378 /// registers, but may be more than one for types (like i64) that are split
380 unsigned getNumRegisters(MVT::ValueType VT) const {
381 if (!MVT::isExtendedVT(VT))
382 return NumRegistersForVT[VT];
384 MVT::ValueType VT1, VT2;
385 unsigned NumIntermediates;
386 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
389 /// hasTargetDAGCombine - If true, the target has custom DAG combine
390 /// transformations that it can perform for the specified node.
391 bool hasTargetDAGCombine(ISD::NodeType NT) const {
392 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
395 /// This function returns the maximum number of store operations permitted
396 /// to replace a call to llvm.memset. The value is set by the target at the
397 /// performance threshold for such a replacement.
398 /// @brief Get maximum # of store operations permitted for llvm.memset
399 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
401 /// This function returns the maximum number of store operations permitted
402 /// to replace a call to llvm.memcpy. The value is set by the target at the
403 /// performance threshold for such a replacement.
404 /// @brief Get maximum # of store operations permitted for llvm.memcpy
405 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
407 /// This function returns the maximum number of store operations permitted
408 /// to replace a call to llvm.memmove. The value is set by the target at the
409 /// performance threshold for such a replacement.
410 /// @brief Get maximum # of store operations permitted for llvm.memmove
411 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
413 /// This function returns true if the target allows unaligned memory accesses.
414 /// This is used, for example, in situations where an array copy/move/set is
415 /// converted to a sequence of store operations. It's use helps to ensure that
416 /// such replacements don't generate code that causes an alignment error
417 /// (trap) on the target machine.
418 /// @brief Determine if the target supports unaligned memory accesses.
419 bool allowsUnalignedMemoryAccesses() const {
420 return allowUnalignedMemoryAccesses;
423 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
424 /// to implement llvm.setjmp.
425 bool usesUnderscoreSetJmp() const {
426 return UseUnderscoreSetJmp;
429 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
430 /// to implement llvm.longjmp.
431 bool usesUnderscoreLongJmp() const {
432 return UseUnderscoreLongJmp;
435 /// getStackPointerRegisterToSaveRestore - If a physical register, this
436 /// specifies the register that llvm.savestack/llvm.restorestack should save
438 unsigned getStackPointerRegisterToSaveRestore() const {
439 return StackPointerRegisterToSaveRestore;
442 /// getExceptionAddressRegister - If a physical register, this returns
443 /// the register that receives the exception address on entry to a landing
445 unsigned getExceptionAddressRegister() const {
446 return ExceptionPointerRegister;
449 /// getExceptionSelectorRegister - If a physical register, this returns
450 /// the register that receives the exception typeid on entry to a landing
452 unsigned getExceptionSelectorRegister() const {
453 return ExceptionSelectorRegister;
456 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
457 /// set, the default is 200)
458 unsigned getJumpBufSize() const {
462 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
463 /// (if never set, the default is 0)
464 unsigned getJumpBufAlignment() const {
465 return JumpBufAlignment;
468 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
469 /// limit. Any block whose size is greater should not be predicated.
470 virtual unsigned getIfCvtBlockSizeLimit() const {
471 return IfCvtBlockSizeLimit;
474 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
475 /// block to be considered for duplication. Any block whose size is greater
476 /// should not be duplicated to facilitate its predication.
477 virtual unsigned getIfCvtDupBlockSizeLimit() const {
478 return IfCvtDupBlockSizeLimit;
481 /// getPreIndexedAddressParts - returns true by value, base pointer and
482 /// offset pointer and addressing mode by reference if the node's address
483 /// can be legally represented as pre-indexed load / store address.
484 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
486 ISD::MemIndexedMode &AM,
491 /// getPostIndexedAddressParts - returns true by value, base pointer and
492 /// offset pointer and addressing mode by reference if this node can be
493 /// combined with a load / store to form a post-indexed load / store.
494 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
495 SDOperand &Base, SDOperand &Offset,
496 ISD::MemIndexedMode &AM,
501 //===--------------------------------------------------------------------===//
502 // TargetLowering Optimization Methods
505 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
506 /// SDOperands for returning information from TargetLowering to its clients
507 /// that want to combine
508 struct TargetLoweringOpt {
513 TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
515 bool CombineTo(SDOperand O, SDOperand N) {
521 /// ShrinkDemandedConstant - Check to see if the specified operand of the
522 /// specified instruction is a constant integer. If so, check to see if there
523 /// are any bits set in the constant that are not demanded. If so, shrink the
524 /// constant and return true.
525 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded);
528 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
529 /// DemandedMask bits of the result of Op are ever used downstream. If we can
530 /// use this information to simplify Op, create a new simplified DAG node and
531 /// return true, returning the original and new nodes in Old and New.
532 /// Otherwise, analyze the expression and return a mask of KnownOne and
533 /// KnownZero bits for the expression (used to simplify the caller).
534 /// The KnownZero/One bits may only be accurate for those bits in the
536 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
537 uint64_t &KnownZero, uint64_t &KnownOne,
538 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
540 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
541 /// Mask are known to be either zero or one and return them in the
542 /// KnownZero/KnownOne bitsets.
543 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
547 const SelectionDAG &DAG,
548 unsigned Depth = 0) const;
550 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
551 /// targets that want to expose additional information about sign bits to the
553 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op,
554 unsigned Depth = 0) const;
556 struct DAGCombinerInfo {
557 void *DC; // The DAG Combiner object.
559 bool CalledByLegalizer;
563 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc)
564 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {}
566 bool isBeforeLegalize() const { return BeforeLegalize; }
567 bool isCalledByLegalizer() const { return CalledByLegalizer; }
569 void AddToWorklist(SDNode *N);
570 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To);
571 SDOperand CombineTo(SDNode *N, SDOperand Res);
572 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1);
575 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
576 /// and cc. If it is unable to simplify it, return a null SDOperand.
577 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
578 ISD::CondCode Cond, bool foldBooleans,
579 DAGCombinerInfo &DCI) const;
581 /// PerformDAGCombine - This method will be invoked for all target nodes and
582 /// for any target-independent nodes that the target has registered with
585 /// The semantics are as follows:
587 /// SDOperand.Val == 0 - No change was made
588 /// SDOperand.Val == N - N was replaced, is dead, and is already handled.
589 /// otherwise - N should be replaced by the returned Operand.
591 /// In addition, methods provided by DAGCombinerInfo may be used to perform
592 /// more complex transformations.
594 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
596 //===--------------------------------------------------------------------===//
597 // TargetLowering Configuration Methods - These methods should be invoked by
598 // the derived class constructor to configure this object for the target.
602 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
603 /// GOT for PC-relative code.
604 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
606 /// setShiftAmountType - Describe the type that should be used for shift
607 /// amounts. This type defaults to the pointer type.
608 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
610 /// setSetCCResultType - Describe the type that shoudl be used as the result
611 /// of a setcc operation. This defaults to the pointer type.
612 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; }
614 /// setSetCCResultContents - Specify how the target extends the result of a
615 /// setcc operation in a register.
616 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
618 /// setSchedulingPreference - Specify the target scheduling preference.
619 void setSchedulingPreference(SchedPreference Pref) {
620 SchedPreferenceInfo = Pref;
623 /// setShiftAmountFlavor - Describe how the target handles out of range shift
625 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
626 ShiftAmtHandling = OORSA;
629 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
630 /// use _setjmp to implement llvm.setjmp or the non _ version.
631 /// Defaults to false.
632 void setUseUnderscoreSetJmp(bool Val) {
633 UseUnderscoreSetJmp = Val;
636 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
637 /// use _longjmp to implement llvm.longjmp or the non _ version.
638 /// Defaults to false.
639 void setUseUnderscoreLongJmp(bool Val) {
640 UseUnderscoreLongJmp = Val;
643 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
644 /// specifies the register that llvm.savestack/llvm.restorestack should save
646 void setStackPointerRegisterToSaveRestore(unsigned R) {
647 StackPointerRegisterToSaveRestore = R;
650 /// setExceptionPointerRegister - If set to a physical register, this sets
651 /// the register that receives the exception address on entry to a landing
653 void setExceptionPointerRegister(unsigned R) {
654 ExceptionPointerRegister = R;
657 /// setExceptionSelectorRegister - If set to a physical register, this sets
658 /// the register that receives the exception typeid on entry to a landing
660 void setExceptionSelectorRegister(unsigned R) {
661 ExceptionSelectorRegister = R;
664 /// SelectIsExpensive - Tells the code generator not to expand operations
665 /// into sequences that use the select operations if possible.
666 void setSelectIsExpensive() { SelectIsExpensive = true; }
668 /// setIntDivIsCheap - Tells the code generator that integer divide is
669 /// expensive, and if possible, should be replaced by an alternate sequence
670 /// of instructions not containing an integer divide.
671 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
673 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
674 /// srl/add/sra for a signed divide by power of two, and let the target handle
676 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
678 /// addRegisterClass - Add the specified register class as an available
679 /// regclass for the specified value type. This indicates the selector can
680 /// handle values of that class natively.
681 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) {
682 assert(!MVT::isExtendedVT(VT));
683 AvailableRegClasses.push_back(std::make_pair(VT, RC));
684 RegClassForVT[VT] = RC;
687 /// computeRegisterProperties - Once all of the register classes are added,
688 /// this allows us to compute derived properties we expose.
689 void computeRegisterProperties();
691 /// setOperationAction - Indicate that the specified operation does not work
692 /// with the specified type and indicate what to do about it.
693 void setOperationAction(unsigned Op, MVT::ValueType VT,
694 LegalizeAction Action) {
695 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) &&
696 "Table isn't big enough!");
697 OpActions[Op] &= ~(uint64_t(3UL) << VT*2);
698 OpActions[Op] |= (uint64_t)Action << VT*2;
701 /// setLoadXAction - Indicate that the specified load with extension does not
702 /// work with the with specified type and indicate what to do about it.
703 void setLoadXAction(unsigned ExtType, MVT::ValueType VT,
704 LegalizeAction Action) {
705 assert(VT < 32 && ExtType < sizeof(LoadXActions)/sizeof(LoadXActions[0]) &&
706 "Table isn't big enough!");
707 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2);
708 LoadXActions[ExtType] |= (uint64_t)Action << VT*2;
711 /// setStoreXAction - Indicate that the specified store with truncation does
712 /// not work with the with specified type and indicate what to do about it.
713 void setStoreXAction(MVT::ValueType VT, LegalizeAction Action) {
714 assert(VT < 32 && "Table isn't big enough!");
715 StoreXActions &= ~(uint64_t(3UL) << VT*2);
716 StoreXActions |= (uint64_t)Action << VT*2;
719 /// setIndexedLoadAction - Indicate that the specified indexed load does or
720 /// does not work with the with specified type and indicate what to do abort
721 /// it. NOTE: All indexed mode loads are initialized to Expand in
722 /// TargetLowering.cpp
723 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT,
724 LegalizeAction Action) {
725 assert(VT < 32 && IdxMode <
726 sizeof(IndexedModeActions[0]) / sizeof(IndexedModeActions[0][0]) &&
727 "Table isn't big enough!");
728 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2);
729 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2;
732 /// setIndexedStoreAction - Indicate that the specified indexed store does or
733 /// does not work with the with specified type and indicate what to do about
734 /// it. NOTE: All indexed mode stores are initialized to Expand in
735 /// TargetLowering.cpp
736 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT,
737 LegalizeAction Action) {
738 assert(VT < 32 && IdxMode <
739 sizeof(IndexedModeActions[1]) / sizeof(IndexedModeActions[1][0]) &&
740 "Table isn't big enough!");
741 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2);
742 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2;
745 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
746 /// promotion code defaults to trying a larger integer/fp until it can find
747 /// one that works. If that default is insufficient, this method can be used
748 /// by the target to override the default.
749 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT,
750 MVT::ValueType DestVT) {
751 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
754 /// addLegalFPImmediate - Indicate that this target can instruction select
755 /// the specified FP immediate natively.
756 void addLegalFPImmediate(double Imm) {
757 LegalFPImmediates.push_back(Imm);
760 /// setTargetDAGCombine - Targets should invoke this method for each target
761 /// independent node that they want to provide a custom DAG combiner for by
762 /// implementing the PerformDAGCombine virtual method.
763 void setTargetDAGCombine(ISD::NodeType NT) {
764 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
767 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
768 /// bytes); default is 200
769 void setJumpBufSize(unsigned Size) {
773 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
774 /// alignment (in bytes); default is 0
775 void setJumpBufAlignment(unsigned Align) {
776 JumpBufAlignment = Align;
779 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
780 /// limit (in number of instructions); default is 2.
781 void setIfCvtBlockSizeLimit(unsigned Limit) {
782 IfCvtBlockSizeLimit = Limit;
785 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
786 /// of instructions) to be considered for code duplication during
787 /// if-conversion; default is 2.
788 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
789 IfCvtDupBlockSizeLimit = Limit;
794 //===--------------------------------------------------------------------===//
795 // Lowering methods - These methods must be implemented by targets so that
796 // the SelectionDAGLowering code knows how to lower these.
799 /// LowerArguments - This hook must be implemented to indicate how we should
800 /// lower the arguments for the specified function, into the specified DAG.
801 virtual std::vector<SDOperand>
802 LowerArguments(Function &F, SelectionDAG &DAG);
804 /// LowerCallTo - This hook lowers an abstract call to a function into an
805 /// actual call. This returns a pair of operands. The first element is the
806 /// return value for the function (if RetTy is not VoidTy). The second
807 /// element is the outgoing token chain.
808 struct ArgListEntry {
816 ArgListEntry():isSExt(false), isZExt(false), isInReg(false), isSRet(false) { };
818 typedef std::vector<ArgListEntry> ArgListTy;
819 virtual std::pair<SDOperand, SDOperand>
820 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned,
821 bool isVarArg, unsigned CallingConv, bool isTailCall,
822 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
824 /// LowerOperation - This callback is invoked for operations that are
825 /// unsupported by the target, which are registered to use 'custom' lowering,
826 /// and whose defined values are all legal.
827 /// If the target has no operations that require custom lowering, it need not
828 /// implement this. The default implementation of this aborts.
829 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
831 /// CustomPromoteOperation - This callback is invoked for operations that are
832 /// unsupported by the target, are registered to use 'custom' lowering, and
833 /// whose type needs to be promoted.
834 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG);
836 /// getTargetNodeName() - This method returns the name of a target specific
838 virtual const char *getTargetNodeName(unsigned Opcode) const;
840 //===--------------------------------------------------------------------===//
841 // Inline Asm Support hooks
844 enum ConstraintType {
845 C_Register, // Constraint represents a single register.
846 C_RegisterClass, // Constraint represents one or more registers.
847 C_Memory, // Memory constraint.
848 C_Other, // Something else.
849 C_Unknown // Unsupported constraint.
852 /// getConstraintType - Given a constraint, return the type of constraint it
853 /// is for this target.
854 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
857 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
858 /// return a list of registers that can be used to satisfy the constraint.
859 /// This should only be used for C_RegisterClass constraints.
860 virtual std::vector<unsigned>
861 getRegClassForInlineAsmConstraint(const std::string &Constraint,
862 MVT::ValueType VT) const;
864 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
865 /// {edx}), return the register number and the register class for the
868 /// Given a register class constraint, like 'r', if this corresponds directly
869 /// to an LLVM register class, return a register of 0 and the register class
872 /// This should only be used for C_Register constraints. On error,
873 /// this returns a register number of 0 and a null register class pointer..
874 virtual std::pair<unsigned, const TargetRegisterClass*>
875 getRegForInlineAsmConstraint(const std::string &Constraint,
876 MVT::ValueType VT) const;
879 /// isOperandValidForConstraint - Return the specified operand (possibly
880 /// modified) if the specified SDOperand is valid for the specified target
881 /// constraint letter, otherwise return null.
883 isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
886 //===--------------------------------------------------------------------===//
890 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
891 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
892 // instructions are special in various ways, which require special support to
893 // insert. The specified MachineInstr is created but not inserted into any
894 // basic blocks, and the scheduler passes ownership of it to this method.
895 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
896 MachineBasicBlock *MBB);
898 //===--------------------------------------------------------------------===//
899 // Addressing mode description hooks (used by LSR etc).
902 /// AddrMode - This represents an addressing mode of:
903 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
904 /// If BaseGV is null, there is no BaseGV.
905 /// If BaseOffs is zero, there is no base offset.
906 /// If HasBaseReg is false, there is no base register.
907 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
915 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
918 /// isLegalAddressingMode - Return true if the addressing mode represented by
919 /// AM is legal for this target, for a load/store of the specified type.
920 /// TODO: Handle pre/postinc as well.
921 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
923 //===--------------------------------------------------------------------===//
924 // Div utility functions
926 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG,
927 std::vector<SDNode*>* Created) const;
928 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG,
929 std::vector<SDNode*>* Created) const;
932 //===--------------------------------------------------------------------===//
933 // Runtime Library hooks
936 /// setLibcallName - Rename the default libcall routine name for the specified
938 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
939 LibcallRoutineNames[Call] = Name;
942 /// getLibcallName - Get the libcall routine name for the specified libcall.
944 const char *getLibcallName(RTLIB::Libcall Call) const {
945 return LibcallRoutineNames[Call];
948 /// setCmpLibcallCC - Override the default CondCode to be used to test the
949 /// result of the comparison libcall against zero.
950 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
951 CmpLibcallCCs[Call] = CC;
954 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
955 /// the comparison libcall against zero.
956 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
957 return CmpLibcallCCs[Call];
962 const TargetData *TD;
964 /// IsLittleEndian - True if this is a little endian target.
968 /// PointerTy - The type to use for pointers, usually i32 or i64.
970 MVT::ValueType PointerTy;
972 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
974 bool UsesGlobalOffsetTable;
976 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
978 MVT::ValueType ShiftAmountTy;
980 OutOfRangeShiftAmount ShiftAmtHandling;
982 /// SelectIsExpensive - Tells the code generator not to expand operations
983 /// into sequences that use the select operations if possible.
984 bool SelectIsExpensive;
986 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
987 /// constants into a sequence of muls, adds, and shifts. This is a hack until
988 /// a real cost model is in place. If we ever optimize for size, this will be
989 /// set to true unconditionally.
992 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
993 /// srl/add/sra for a signed divide by power of two, and let the target handle
997 /// SetCCResultTy - The type that SetCC operations use. This defaults to the
999 MVT::ValueType SetCCResultTy;
1001 /// SetCCResultContents - Information about the contents of the high-bits in
1002 /// the result of a setcc comparison operation.
1003 SetCCResultValue SetCCResultContents;
1005 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1006 /// total cycles or lowest register usage.
1007 SchedPreference SchedPreferenceInfo;
1009 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1010 /// llvm.setjmp. Defaults to false.
1011 bool UseUnderscoreSetJmp;
1013 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1014 /// llvm.longjmp. Defaults to false.
1015 bool UseUnderscoreLongJmp;
1017 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1018 unsigned JumpBufSize;
1020 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1022 unsigned JumpBufAlignment;
1024 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1026 unsigned IfCvtBlockSizeLimit;
1028 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1029 /// duplicated during if-conversion.
1030 unsigned IfCvtDupBlockSizeLimit;
1032 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1033 /// specifies the register that llvm.savestack/llvm.restorestack should save
1035 unsigned StackPointerRegisterToSaveRestore;
1037 /// ExceptionPointerRegister - If set to a physical register, this specifies
1038 /// the register that receives the exception address on entry to a landing
1040 unsigned ExceptionPointerRegister;
1042 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1043 /// the register that receives the exception typeid on entry to a landing
1045 unsigned ExceptionSelectorRegister;
1047 /// RegClassForVT - This indicates the default register class to use for
1048 /// each ValueType the target supports natively.
1049 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1050 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1051 MVT::ValueType RegisterTypeForVT[MVT::LAST_VALUETYPE];
1053 /// TransformToType - For any value types we are promoting or expanding, this
1054 /// contains the value type that we are changing to. For Expanded types, this
1055 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1056 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1057 /// by the system, this holds the same type (e.g. i32 -> i32).
1058 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
1060 /// OpActions - For each operation and each value type, keep a LegalizeAction
1061 /// that indicates how instruction selection should deal with the operation.
1062 /// Most operations are Legal (aka, supported natively by the target), but
1063 /// operations that are not should be described. Note that operations on
1064 /// non-legal value types are not described here.
1065 uint64_t OpActions[156];
1067 /// LoadXActions - For each load of load extension type and each value type,
1068 /// keep a LegalizeAction that indicates how instruction selection should deal
1070 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE];
1072 /// StoreXActions - For each store with truncation of each value type, keep a
1073 /// LegalizeAction that indicates how instruction selection should deal with
1075 uint64_t StoreXActions;
1077 /// IndexedModeActions - For each indexed mode and each value type, keep a
1078 /// pair of LegalizeAction that indicates how instruction selection should
1079 /// deal with the load / store.
1080 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
1082 ValueTypeActionImpl ValueTypeActions;
1084 std::vector<double> LegalFPImmediates;
1086 std::vector<std::pair<MVT::ValueType,
1087 TargetRegisterClass*> > AvailableRegClasses;
1089 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1090 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1091 /// which sets a bit in this array.
1092 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)];
1094 /// PromoteToType - For operations that must be promoted to a specific type,
1095 /// this holds the destination type. This map should be sparse, so don't hold
1098 /// Targets add entries to this map with AddPromotedToType(..), clients access
1099 /// this with getTypeToPromoteTo(..).
1100 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType;
1102 /// LibcallRoutineNames - Stores the name each libcall.
1104 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1106 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1107 /// of each of the comparison libcall against zero.
1108 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1111 /// When lowering %llvm.memset this field specifies the maximum number of
1112 /// store operations that may be substituted for the call to memset. Targets
1113 /// must set this value based on the cost threshold for that target. Targets
1114 /// should assume that the memset will be done using as many of the largest
1115 /// store operations first, followed by smaller ones, if necessary, per
1116 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1117 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1118 /// store. This only applies to setting a constant array of a constant size.
1119 /// @brief Specify maximum number of store instructions per memset call.
1120 unsigned maxStoresPerMemset;
1122 /// When lowering %llvm.memcpy this field specifies the maximum number of
1123 /// store operations that may be substituted for a call to memcpy. Targets
1124 /// must set this value based on the cost threshold for that target. Targets
1125 /// should assume that the memcpy will be done using as many of the largest
1126 /// store operations first, followed by smaller ones, if necessary, per
1127 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1128 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1129 /// and one 1-byte store. This only applies to copying a constant array of
1131 /// @brief Specify maximum bytes of store instructions per memcpy call.
1132 unsigned maxStoresPerMemcpy;
1134 /// When lowering %llvm.memmove this field specifies the maximum number of
1135 /// store instructions that may be substituted for a call to memmove. Targets
1136 /// must set this value based on the cost threshold for that target. Targets
1137 /// should assume that the memmove will be done using as many of the largest
1138 /// store operations first, followed by smaller ones, if necessary, per
1139 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1140 /// with 8-bit alignment would result in nine 1-byte stores. This only
1141 /// applies to copying a constant array of constant size.
1142 /// @brief Specify maximum bytes of store instructions per memmove call.
1143 unsigned maxStoresPerMemmove;
1145 /// This field specifies whether the target machine permits unaligned memory
1146 /// accesses. This is used, for example, to determine the size of store
1147 /// operations when copying small arrays and other similar tasks.
1148 /// @brief Indicate whether the target permits unaligned memory accesses.
1149 bool allowUnalignedMemoryAccesses;
1151 } // end llvm namespace