1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Support/DataTypes.h"
27 class TargetRegisterClass;
29 class CalleeSavedInfo;
33 template<class T> class SmallVectorImpl;
35 //===----------------------------------------------------------------------===//
36 // Machine Operand Flags and Description
37 //===----------------------------------------------------------------------===//
40 // Operand constraints: only "tied_to" for now.
41 enum OperandConstraint {
42 TIED_TO = 0 // Must be allocated the same register as.
45 /// OperandFlags - These are flags set on operands, but should be considered
46 /// private, all access should go through the TargetOperandInfo accessors.
47 /// See the accessors for a description of what these are.
49 LookupPtrRegClass = 1 << 0,
55 /// TargetOperandInfo - This holds information about one operand of a machine
56 /// instruction, indicating the register class for register operands, etc.
58 class TargetOperandInfo {
60 /// RegClass - This specifies the register class enumeration of the operand
61 /// if the operand is a register. If not, this contains 0.
62 unsigned short RegClass;
64 /// Lower 16 bits are used to specify which constraints are set. The higher 16
65 /// bits are used to specify the value of constraints (4 bits each).
66 unsigned int Constraints;
67 /// Currently no other information.
69 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
70 /// requires a callback to look up its register class.
71 bool isLookupPtrRegClass() const { return Flags & TOI::LookupPtrRegClass; }
73 /// isPredicate - Set if this is one of the operands that made up of
74 /// the predicate operand that controls an M_PREDICATED instruction.
75 bool isPredicate() const { return Flags & TOI::Predicate; }
77 /// isOptionalDef - Set if this operand is a optional def.
79 bool isOptionalDef() const { return Flags & TOI::OptionalDef; }
83 //===----------------------------------------------------------------------===//
84 // Machine Instruction Flags and Description
85 //===----------------------------------------------------------------------===//
87 const unsigned M_BRANCH_FLAG = 1 << 0;
88 const unsigned M_CALL_FLAG = 1 << 1;
89 const unsigned M_RET_FLAG = 1 << 2;
90 const unsigned M_BARRIER_FLAG = 1 << 3;
91 const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
93 /// M_SIMPLE_LOAD_FLAG - This flag is set for instructions that are simple loads
94 /// from memory. This should only be set on instructions that load a value from
95 /// memory and return it in their only virtual register definition.
96 const unsigned M_SIMPLE_LOAD_FLAG = 1 << 5;
98 /// M_MAY_STORE_FLAG - This flag is set to any instruction that could possibly
99 /// modify memory. Instructions with this flag set are not necessarily simple
100 /// store instructions, they may store a modified value based on their operands,
101 /// or may not actually modify anything, for example.
102 const unsigned M_MAY_STORE_FLAG = 1 << 6;
104 const unsigned M_INDIRECT_FLAG = 1 << 7;
105 const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8;
107 // M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
108 // changed into a 3-address instruction if the first two operands cannot be
109 // assigned to the same register. The target must implement the
110 // TargetInstrInfo::convertToThreeAddress method for this instruction.
111 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 9;
113 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
114 // Z), which produces the same result if Y and Z are exchanged.
115 const unsigned M_COMMUTABLE = 1 << 10;
117 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
118 // block? Typically this is things like return and branch instructions.
119 // Various passes use this to insert code into the bottom of a basic block, but
120 // before control flow occurs.
121 const unsigned M_TERMINATOR_FLAG = 1 << 11;
123 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
124 // insertion support when the DAG scheduler is inserting it into a machine basic
126 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12;
128 // M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
129 // operands in addition to the minimum number operands specified.
130 const unsigned M_VARIABLE_OPS = 1 << 13;
132 // M_PREDICABLE - Set if this instruction has a predicate operand that
133 // controls execution. It may be set to 'always'.
134 const unsigned M_PREDICABLE = 1 << 14;
136 // M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized
137 // at any time, e.g. constant generation, load from constant pool.
138 const unsigned M_REMATERIALIZIBLE = 1 << 15;
140 // M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated.
141 // (e.g. instructions with unique labels attached).
142 const unsigned M_NOT_DUPLICABLE = 1 << 16;
144 // M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition, e.g.
145 // ARM instructions which can set condition code if 's' bit is set.
146 const unsigned M_HAS_OPTIONAL_DEF = 1 << 17;
148 // M_NEVER_HAS_SIDE_EFFECTS - Set if this instruction has no side effects that
149 // are not captured by any operands of the instruction or other flags, and when
150 // *all* instances of the instruction of that opcode have no side effects.
152 // Note: This and M_MAY_HAVE_SIDE_EFFECTS are mutually exclusive. You can't set
153 // both! If neither flag is set, then the instruction *always* has side effects.
154 const unsigned M_NEVER_HAS_SIDE_EFFECTS = 1 << 18;
156 // M_MAY_HAVE_SIDE_EFFECTS - Set if some instances of this instruction can have
157 // side effects. The virtual method "isReallySideEffectFree" is called to
158 // determine this. Load instructions are an example of where this is useful. In
159 // general, loads always have side effects. However, loads from constant pools
160 // don't. We let the specific back end make this determination.
162 // Note: This and M_NEVER_HAS_SIDE_EFFECTS are mutually exclusive. You can't set
163 // both! If neither flag is set, then the instruction *always* has side effects.
164 const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19;
168 class TargetInstrDescriptor {
170 unsigned short Opcode; // The opcode number.
171 unsigned short NumOperands; // Num of args (may be more if variable_ops)
172 unsigned short NumDefs; // Num of args that are definitions.
173 unsigned short SchedClass; // enum identifying instr sched class
174 const char * Name; // Name of the instruction record in td file.
175 unsigned Flags; // flags identifying machine instr class
176 unsigned TSFlags; // Target Specific Flag values
177 const unsigned *ImplicitUses; // Registers implicitly read by this instr
178 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
179 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
181 /// getOperandConstraint - Returns the value of the specific constraint if
182 /// it is set. Returns -1 if it is not set.
183 int getOperandConstraint(unsigned OpNum,
184 TOI::OperandConstraint Constraint) const {
185 assert((OpNum < NumOperands || hasVariableOperands()) &&
186 "Invalid operand # of TargetInstrInfo");
187 if (OpNum < NumOperands &&
188 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
189 unsigned Pos = 16 + Constraint * 4;
190 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
195 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
196 /// dest operand. Returns -1 if there isn't one.
197 int findTiedToSrcOperand(unsigned OpNum) const;
199 /// getName - Return the name of the record in the .td file for this
200 /// instruction, for example "ADD8ri".
201 const char *getName() const {
205 unsigned getNumOperands() const {
209 unsigned getNumDefs() const {
213 bool hasVariableOperands() const {
214 return Flags & M_VARIABLE_OPS;
217 bool hasOptionalDef() const {
218 return Flags & M_HAS_OPTIONAL_DEF;
221 const unsigned *getImplicitUses() const {
225 const unsigned *getImplicitDefs() const {
229 bool isReturn() const {
230 return Flags & M_RET_FLAG;
233 bool isCall() const {
234 return Flags & M_CALL_FLAG;
237 bool isTerminator() const {
238 return Flags & M_TERMINATOR_FLAG;
241 bool isBranch() const {
242 return Flags & M_BRANCH_FLAG;
245 bool isIndirectBranch() const {
246 return Flags & M_INDIRECT_FLAG;
249 bool isPredicable() const {
250 return Flags & M_PREDICABLE;
253 bool isNotDuplicable() const {
254 return Flags & M_NOT_DUPLICABLE;
257 bool isCommutableInstr() const {
258 return Flags & M_COMMUTABLE;
261 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
262 /// custom insertion support when the DAG scheduler is inserting it into a
263 /// machine basic block.
264 bool usesCustomDAGSchedInsertionHook() const {
265 return Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
268 /// isSimpleLoad - Return true for instructions that are simple loads from
269 /// memory. This should only be set on instructions that load a value from
270 /// memory and return it in their only virtual register definition.
271 /// Instructions that return a value loaded from memory and then modified in
272 /// some way should not return true for this.
273 bool isSimpleLoad() const {
274 return Flags & M_SIMPLE_LOAD_FLAG;
277 /// mayStore - Return true if this instruction could possibly modify memory.
278 /// Instructions with this flag set are not necessarily simple store
279 /// instructions, they may store a modified value based on their operands, or
280 /// may not actually modify anything, for example.
281 bool mayStore() const {
282 return Flags & M_MAY_STORE_FLAG;
285 /// isBarrier - Returns true if the specified instruction stops control flow
286 /// from executing the instruction immediately following it. Examples include
287 /// unconditional branches and return instructions.
288 bool isBarrier() const {
289 return Flags & M_BARRIER_FLAG;
292 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
293 /// which must be filled by the code generator.
294 bool hasDelaySlot() const {
295 return Flags & M_DELAY_SLOT_FLAG;
298 unsigned getSchedClass() const {
304 //---------------------------------------------------------------------------
306 /// TargetInstrInfo - Interface to description of machine instructions
308 class TargetInstrInfo {
309 const TargetInstrDescriptor* desc; // raw array to allow static init'n
310 unsigned NumOpcodes; // number of entries in the desc array
311 unsigned numRealOpCodes; // number of non-dummy op codes
313 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
314 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
316 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
317 virtual ~TargetInstrInfo();
319 // Invariant opcodes: All instruction sets have these as their low opcodes.
328 unsigned getNumOpcodes() const { return NumOpcodes; }
330 /// get - Return the machine instruction descriptor that corresponds to the
331 /// specified instruction opcode.
333 const TargetInstrDescriptor& get(unsigned Opcode) const {
334 assert(Opcode < NumOpcodes);
338 /// isTriviallyReMaterializable - Return true if the instruction is trivially
339 /// rematerializable, meaning it has no side effects and requires no operands
340 /// that aren't always available.
341 bool isTriviallyReMaterializable(MachineInstr *MI) const {
342 return (MI->getDesc()->Flags & M_REMATERIALIZIBLE) &&
343 isReallyTriviallyReMaterializable(MI);
346 /// hasUnmodelledSideEffects - Returns true if the instruction has side
347 /// effects that are not captured by any operands of the instruction or other
349 bool hasUnmodelledSideEffects(MachineInstr *MI) const {
350 const TargetInstrDescriptor *TID = MI->getDesc();
351 if (TID->Flags & M_NEVER_HAS_SIDE_EFFECTS) return false;
352 if (!(TID->Flags & M_MAY_HAVE_SIDE_EFFECTS)) return true;
353 return !isReallySideEffectFree(MI); // May have side effects
356 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
357 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
358 /// instruction itself is actually trivially rematerializable, considering
359 /// its operands. This is used for targets that have instructions that are
360 /// only trivially rematerializable for specific uses. This predicate must
361 /// return false if the instruction has any side effects other than
362 /// producing a value, or if it requres any address registers that are not
363 /// always available.
364 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
368 /// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this
369 /// method is called to determine if the specific instance of this
370 /// instruction has side effects. This is useful in cases of instructions,
371 /// like loads, which generally always have side effects. A load from a
372 /// constant pool doesn't have side effects, though. So we need to
373 /// differentiate it from the general case.
374 virtual bool isReallySideEffectFree(MachineInstr *MI) const {
378 /// getOperandConstraint - Returns the value of the specific constraint if
379 /// it is set. Returns -1 if it is not set.
380 int getOperandConstraint(unsigned Opcode, unsigned OpNum,
381 TOI::OperandConstraint Constraint) const {
382 return get(Opcode).getOperandConstraint(OpNum, Constraint);
385 /// Return true if the instruction is a register to register move
386 /// and leave the source and dest operands in the passed parameters.
387 virtual bool isMoveInstr(const MachineInstr& MI,
389 unsigned& destReg) const {
393 /// isLoadFromStackSlot - If the specified machine instruction is a direct
394 /// load from a stack slot, return the virtual or physical register number of
395 /// the destination along with the FrameIndex of the loaded stack slot. If
396 /// not, return 0. This predicate must return 0 if the instruction has
397 /// any side effects other than loading from the stack slot.
398 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
402 /// isStoreToStackSlot - If the specified machine instruction is a direct
403 /// store to a stack slot, return the virtual or physical register number of
404 /// the source reg along with the FrameIndex of the loaded stack slot. If
405 /// not, return 0. This predicate must return 0 if the instruction has
406 /// any side effects other than storing to the stack slot.
407 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
411 /// convertToThreeAddress - This method must be implemented by targets that
412 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
413 /// may be able to convert a two-address instruction into one or more true
414 /// three-address instructions on demand. This allows the X86 target (for
415 /// example) to convert ADD and SHL instructions into LEA instructions if they
416 /// would require register copies due to two-addressness.
418 /// This method returns a null pointer if the transformation cannot be
419 /// performed, otherwise it returns the last new instruction.
421 virtual MachineInstr *
422 convertToThreeAddress(MachineFunction::iterator &MFI,
423 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
427 /// commuteInstruction - If a target has any instructions that are commutable,
428 /// but require converting to a different instruction or making non-trivial
429 /// changes to commute them, this method can overloaded to do this. The
430 /// default implementation of this method simply swaps the first two operands
431 /// of MI and returns it.
433 /// If a target wants to make more aggressive changes, they can construct and
434 /// return a new machine instruction. If an instruction cannot commute, it
435 /// can also return null.
437 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0;
439 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
440 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
441 /// implemented for a target). Upon success, this returns false and returns
442 /// with the following information in various cases:
444 /// 1. If this block ends with no branches (it just falls through to its succ)
445 /// just return false, leaving TBB/FBB null.
446 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
447 /// the destination block.
448 /// 3. If this block ends with an conditional branch and it falls through to
449 /// an successor block, it sets TBB to be the branch destination block and a
450 /// list of operands that evaluate the condition. These
451 /// operands can be passed to other TargetInstrInfo methods to create new
453 /// 4. If this block ends with an conditional branch and an unconditional
454 /// block, it returns the 'true' destination in TBB, the 'false' destination
455 /// in FBB, and a list of operands that evaluate the condition. These
456 /// operands can be passed to other TargetInstrInfo methods to create new
459 /// Note that RemoveBranch and InsertBranch must be implemented to support
460 /// cases where this method returns success.
462 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
463 MachineBasicBlock *&FBB,
464 std::vector<MachineOperand> &Cond) const {
468 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
469 /// this is only invoked in cases where AnalyzeBranch returns success. It
470 /// returns the number of instructions that were removed.
471 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
472 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
476 /// InsertBranch - Insert a branch into the end of the specified
477 /// MachineBasicBlock. This operands to this method are the same as those
478 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
479 /// returns success and when an unconditional branch (TBB is non-null, FBB is
480 /// null, Cond is empty) needs to be inserted. It returns the number of
481 /// instructions inserted.
482 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
483 MachineBasicBlock *FBB,
484 const std::vector<MachineOperand> &Cond) const {
485 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
489 /// copyRegToReg - Add a copy between a pair of registers
490 virtual void copyRegToReg(MachineBasicBlock &MBB,
491 MachineBasicBlock::iterator MI,
492 unsigned DestReg, unsigned SrcReg,
493 const TargetRegisterClass *DestRC,
494 const TargetRegisterClass *SrcRC) const {
495 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
498 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
499 MachineBasicBlock::iterator MI,
500 unsigned SrcReg, bool isKill, int FrameIndex,
501 const TargetRegisterClass *RC) const {
502 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
505 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
506 SmallVectorImpl<MachineOperand> &Addr,
507 const TargetRegisterClass *RC,
508 SmallVectorImpl<MachineInstr*> &NewMIs) const {
509 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
512 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
513 MachineBasicBlock::iterator MI,
514 unsigned DestReg, int FrameIndex,
515 const TargetRegisterClass *RC) const {
516 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
519 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
520 SmallVectorImpl<MachineOperand> &Addr,
521 const TargetRegisterClass *RC,
522 SmallVectorImpl<MachineInstr*> &NewMIs) const {
523 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
526 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
527 /// saved registers and returns true if it isn't possible / profitable to do
528 /// so by issuing a series of store instructions via
529 /// storeRegToStackSlot(). Returns false otherwise.
530 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
531 MachineBasicBlock::iterator MI,
532 const std::vector<CalleeSavedInfo> &CSI) const {
536 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
537 /// saved registers and returns true if it isn't possible / profitable to do
538 /// so by issuing a series of load instructions via loadRegToStackSlot().
539 /// Returns false otherwise.
540 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
541 MachineBasicBlock::iterator MI,
542 const std::vector<CalleeSavedInfo> &CSI) const {
546 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
547 /// slot into the specified machine instruction for the specified operand(s).
548 /// If this is possible, a new instruction is returned with the specified
549 /// operand folded, otherwise NULL is returned. The client is responsible for
550 /// removing the old instruction and adding the new one in the instruction
552 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
553 SmallVectorImpl<unsigned> &Ops,
554 int FrameIndex) const {
558 /// foldMemoryOperand - Same as the previous version except it allows folding
559 /// of any load and store from / to any address, not just from a specific
561 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
562 SmallVectorImpl<unsigned> &Ops,
563 MachineInstr* LoadMI) const {
567 /// canFoldMemoryOperand - Returns true if the specified load / store is
568 /// folding is possible.
570 bool canFoldMemoryOperand(MachineInstr *MI,
571 SmallVectorImpl<unsigned> &Ops) const{
575 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
576 /// a store or a load and a store into two or more instruction. If this is
577 /// possible, returns true as well as the new instructions by reference.
578 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
579 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
580 SmallVectorImpl<MachineInstr*> &NewMIs) const{
584 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
585 SmallVectorImpl<SDNode*> &NewNodes) const {
589 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
590 /// instruction after load / store are unfolded from an instruction of the
591 /// specified opcode. It returns zero if the specified unfolding is not
593 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
594 bool UnfoldLoad, bool UnfoldStore) const {
598 /// BlockHasNoFallThrough - Return true if the specified block does not
599 /// fall-through into its successor block. This is primarily used when a
600 /// branch is unanalyzable. It is useful for things like unconditional
601 /// indirect branches (jump tables).
602 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
606 /// ReverseBranchCondition - Reverses the branch condition of the specified
607 /// condition list, returning false on success and true if it cannot be
609 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
613 /// insertNoop - Insert a noop into the instruction stream at the specified
615 virtual void insertNoop(MachineBasicBlock &MBB,
616 MachineBasicBlock::iterator MI) const {
617 assert(0 && "Target didn't implement insertNoop!");
621 /// isPredicated - Returns true if the instruction is already predicated.
623 virtual bool isPredicated(const MachineInstr *MI) const {
627 /// isUnpredicatedTerminator - Returns true if the instruction is a
628 /// terminator instruction that has not been predicated.
629 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
631 /// PredicateInstruction - Convert the instruction into a predicated
632 /// instruction. It returns true if the operation was successful.
634 bool PredicateInstruction(MachineInstr *MI,
635 const std::vector<MachineOperand> &Pred) const = 0;
637 /// SubsumesPredicate - Returns true if the first specified predicate
638 /// subsumes the second, e.g. GE subsumes GT.
640 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
641 const std::vector<MachineOperand> &Pred2) const {
645 /// DefinesPredicate - If the specified instruction defines any predicate
646 /// or condition code register(s) used for predication, returns true as well
647 /// as the definition predicate(s) by reference.
648 virtual bool DefinesPredicate(MachineInstr *MI,
649 std::vector<MachineOperand> &Pred) const {
653 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
655 virtual const TargetRegisterClass *getPointerRegClass() const {
656 assert(0 && "Target didn't implement getPointerRegClass!");
658 return 0; // Must return a value in order to compile with VS 2005
662 /// TargetInstrInfoImpl - This is the default implementation of
663 /// TargetInstrInfo, which just provides a couple of default implementations
664 /// for various methods. This separated out because it is implemented in
665 /// libcodegen, not in libtarget.
666 class TargetInstrInfoImpl : public TargetInstrInfo {
668 TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes)
669 : TargetInstrInfo(desc, NumOpcodes) {}
671 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
672 virtual bool PredicateInstruction(MachineInstr *MI,
673 const std::vector<MachineOperand> &Pred) const;
677 } // End llvm namespace