1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/DFAPacketizer.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineCombinerPattern.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
27 class InstrItineraryData;
30 class MachineMemOperand;
31 class MachineRegisterInfo;
35 class MCSymbolRefExpr;
37 class ScheduleHazardRecognizer;
40 class TargetRegisterClass;
41 class TargetRegisterInfo;
42 class BranchProbability;
43 class TargetSubtargetInfo;
45 template<class T> class SmallVectorImpl;
48 //---------------------------------------------------------------------------
50 /// TargetInstrInfo - Interface to description of machine instruction set
52 class TargetInstrInfo : public MCInstrInfo {
53 TargetInstrInfo(const TargetInstrInfo &) LLVM_DELETED_FUNCTION;
54 void operator=(const TargetInstrInfo &) LLVM_DELETED_FUNCTION;
56 TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1)
57 : CallFrameSetupOpcode(CFSetupOpcode),
58 CallFrameDestroyOpcode(CFDestroyOpcode) {
61 virtual ~TargetInstrInfo();
63 /// getRegClass - Givem a machine instruction descriptor, returns the register
64 /// class constraint for OpNum, or NULL.
65 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
67 const TargetRegisterInfo *TRI,
68 const MachineFunction &MF) const;
70 /// isTriviallyReMaterializable - Return true if the instruction is trivially
71 /// rematerializable, meaning it has no side effects and requires no operands
72 /// that aren't always available.
73 bool isTriviallyReMaterializable(const MachineInstr *MI,
74 AliasAnalysis *AA = nullptr) const {
75 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
76 (MI->getDesc().isRematerializable() &&
77 (isReallyTriviallyReMaterializable(MI, AA) ||
78 isReallyTriviallyReMaterializableGeneric(MI, AA)));
82 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
83 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
84 /// specify whether the instruction is actually trivially rematerializable,
85 /// taking into consideration its operands. This predicate must return false
86 /// if the instruction has any side effects other than producing a value, or
87 /// if it requres any address registers that are not always available.
88 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
89 AliasAnalysis *AA) const {
94 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
95 /// for which the M_REMATERIALIZABLE flag is set and the target hook
96 /// isReallyTriviallyReMaterializable returns false, this function does
97 /// target-independent tests to determine if the instruction is really
98 /// trivially rematerializable.
99 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
100 AliasAnalysis *AA) const;
103 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
104 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
105 /// targets use pseudo instructions in order to abstract away the difference
106 /// between operating with a frame pointer and operating without, through the
107 /// use of these two instructions.
109 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
110 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
112 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
113 /// extension instruction. That is, it's like a copy where it's legal for the
114 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
115 /// true, then it's expected the pre-extension value is available as a subreg
116 /// of the result register. This also returns the sub-register index in
118 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
119 unsigned &SrcReg, unsigned &DstReg,
120 unsigned &SubIdx) const {
124 /// isLoadFromStackSlot - If the specified machine instruction is a direct
125 /// load from a stack slot, return the virtual or physical register number of
126 /// the destination along with the FrameIndex of the loaded stack slot. If
127 /// not, return 0. This predicate must return 0 if the instruction has
128 /// any side effects other than loading from the stack slot.
129 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
130 int &FrameIndex) const {
134 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
135 /// stack locations as well. This uses a heuristic so it isn't
136 /// reliable for correctness.
137 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
138 int &FrameIndex) const {
142 /// hasLoadFromStackSlot - If the specified machine instruction has
143 /// a load from a stack slot, return true along with the FrameIndex
144 /// of the loaded stack slot and the machine mem operand containing
145 /// the reference. If not, return false. Unlike
146 /// isLoadFromStackSlot, this returns true for any instructions that
147 /// loads from the stack. This is just a hint, as some cases may be
149 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
150 const MachineMemOperand *&MMO,
151 int &FrameIndex) const;
153 /// isStoreToStackSlot - If the specified machine instruction is a direct
154 /// store to a stack slot, return the virtual or physical register number of
155 /// the source reg along with the FrameIndex of the loaded stack slot. If
156 /// not, return 0. This predicate must return 0 if the instruction has
157 /// any side effects other than storing to the stack slot.
158 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
159 int &FrameIndex) const {
163 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
164 /// stack locations as well. This uses a heuristic so it isn't
165 /// reliable for correctness.
166 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
167 int &FrameIndex) const {
171 /// hasStoreToStackSlot - If the specified machine instruction has a
172 /// store to a stack slot, return true along with the FrameIndex of
173 /// the loaded stack slot and the machine mem operand containing the
174 /// reference. If not, return false. Unlike isStoreToStackSlot,
175 /// this returns true for any instructions that stores to the
176 /// stack. This is just a hint, as some cases may be missed.
177 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
178 const MachineMemOperand *&MMO,
179 int &FrameIndex) const;
181 /// isStackSlotCopy - Return true if the specified machine instruction
182 /// is a copy of one stack slot to another and has no other effect.
183 /// Provide the identity of the two frame indices.
184 virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
185 int &SrcFrameIndex) const {
189 /// Compute the size in bytes and offset within a stack slot of a spilled
190 /// register or subregister.
192 /// \param [out] Size in bytes of the spilled value.
193 /// \param [out] Offset in bytes within the stack slot.
194 /// \returns true if both Size and Offset are successfully computed.
196 /// Not all subregisters have computable spill slots. For example,
197 /// subregisters registers may not be byte-sized, and a pair of discontiguous
198 /// subregisters has no single offset.
200 /// Targets with nontrivial bigendian implementations may need to override
201 /// this, particularly to support spilled vector registers.
202 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
203 unsigned &Size, unsigned &Offset,
204 const TargetMachine *TM) const;
206 /// isAsCheapAsAMove - Return true if the instruction is as cheap as a move
209 /// Targets for different archs need to override this, and different
210 /// micro-architectures can also be finely tuned inside.
211 virtual bool isAsCheapAsAMove(const MachineInstr *MI) const {
212 return MI->isAsCheapAsAMove();
215 /// reMaterialize - Re-issue the specified 'original' instruction at the
216 /// specific location targeting a new destination register.
217 /// The register in Orig->getOperand(0).getReg() will be substituted by
218 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
220 virtual void reMaterialize(MachineBasicBlock &MBB,
221 MachineBasicBlock::iterator MI,
222 unsigned DestReg, unsigned SubIdx,
223 const MachineInstr *Orig,
224 const TargetRegisterInfo &TRI) const;
226 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
227 /// MachineFunction::CloneMachineInstr(), but the target may update operands
228 /// that are required to be unique.
230 /// The instruction must be duplicable as indicated by isNotDuplicable().
231 virtual MachineInstr *duplicate(MachineInstr *Orig,
232 MachineFunction &MF) const;
234 /// convertToThreeAddress - This method must be implemented by targets that
235 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
236 /// may be able to convert a two-address instruction into one or more true
237 /// three-address instructions on demand. This allows the X86 target (for
238 /// example) to convert ADD and SHL instructions into LEA instructions if they
239 /// would require register copies due to two-addressness.
241 /// This method returns a null pointer if the transformation cannot be
242 /// performed, otherwise it returns the last new instruction.
244 virtual MachineInstr *
245 convertToThreeAddress(MachineFunction::iterator &MFI,
246 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
250 /// commuteInstruction - If a target has any instructions that are
251 /// commutable but require converting to different instructions or making
252 /// non-trivial changes to commute them, this method can overloaded to do
253 /// that. The default implementation simply swaps the commutable operands.
254 /// If NewMI is false, MI is modified in place and returned; otherwise, a
255 /// new machine instruction is created and returned. Do not call this
256 /// method for a non-commutable instruction, but there may be some cases
257 /// where this method fails and returns null.
258 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
259 bool NewMI = false) const;
261 /// findCommutedOpIndices - If specified MI is commutable, return the two
262 /// operand indices that would swap value. Return false if the instruction
263 /// is not in a form which this routine understands.
264 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
265 unsigned &SrcOpIdx2) const;
267 /// produceSameValue - Return true if two machine instructions would produce
268 /// identical values. By default, this is only true when the two instructions
269 /// are deemed identical except for defs. If this function is called when the
270 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
271 /// aggressive checks.
272 virtual bool produceSameValue(const MachineInstr *MI0,
273 const MachineInstr *MI1,
274 const MachineRegisterInfo *MRI = nullptr) const;
276 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
277 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
278 /// implemented for a target). Upon success, this returns false and returns
279 /// with the following information in various cases:
281 /// 1. If this block ends with no branches (it just falls through to its succ)
282 /// just return false, leaving TBB/FBB null.
283 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
284 /// the destination block.
285 /// 3. If this block ends with a conditional branch and it falls through to a
286 /// successor block, it sets TBB to be the branch destination block and a
287 /// list of operands that evaluate the condition. These operands can be
288 /// passed to other TargetInstrInfo methods to create new branches.
289 /// 4. If this block ends with a conditional branch followed by an
290 /// unconditional branch, it returns the 'true' destination in TBB, the
291 /// 'false' destination in FBB, and a list of operands that evaluate the
292 /// condition. These operands can be passed to other TargetInstrInfo
293 /// methods to create new branches.
295 /// Note that RemoveBranch and InsertBranch must be implemented to support
296 /// cases where this method returns success.
298 /// If AllowModify is true, then this routine is allowed to modify the basic
299 /// block (e.g. delete instructions after the unconditional branch).
301 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
302 MachineBasicBlock *&FBB,
303 SmallVectorImpl<MachineOperand> &Cond,
304 bool AllowModify = false) const {
308 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
309 /// This is only invoked in cases where AnalyzeBranch returns success. It
310 /// returns the number of instructions that were removed.
311 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
312 llvm_unreachable("Target didn't implement TargetInstrInfo::RemoveBranch!");
315 /// InsertBranch - Insert branch code into the end of the specified
316 /// MachineBasicBlock. The operands to this method are the same as those
317 /// returned by AnalyzeBranch. This is only invoked in cases where
318 /// AnalyzeBranch returns success. It returns the number of instructions
321 /// It is also invoked by tail merging to add unconditional branches in
322 /// cases where AnalyzeBranch doesn't apply because there was no original
323 /// branch to analyze. At least this much must be implemented, else tail
324 /// merging needs to be disabled.
325 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
326 MachineBasicBlock *FBB,
327 const SmallVectorImpl<MachineOperand> &Cond,
329 llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!");
332 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
333 /// after it, replacing it with an unconditional branch to NewDest. This is
334 /// used by the tail merging pass.
335 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
336 MachineBasicBlock *NewDest) const;
338 /// getUnconditionalBranch - Get an instruction that performs an unconditional
339 /// branch to the given symbol.
341 getUnconditionalBranch(MCInst &MI,
342 const MCSymbolRefExpr *BranchTarget) const {
343 llvm_unreachable("Target didn't implement "
344 "TargetInstrInfo::getUnconditionalBranch!");
347 /// getTrap - Get a machine trap instruction
348 virtual void getTrap(MCInst &MI) const {
349 llvm_unreachable("Target didn't implement TargetInstrInfo::getTrap!");
352 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic
353 /// block at the specified instruction (i.e. instruction would be the start
354 /// of a new basic block).
355 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
356 MachineBasicBlock::iterator MBBI) const {
360 /// isProfitableToIfCvt - Return true if it's profitable to predicate
361 /// instructions with accumulated instruction latency of "NumCycles"
362 /// of the specified basic block, where the probability of the instructions
363 /// being executed is given by Probability, and Confidence is a measure
364 /// of our confidence that it will be properly predicted.
366 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
367 unsigned ExtraPredCycles,
368 const BranchProbability &Probability) const {
372 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one
373 /// checks for the case where two basic blocks from true and false path
374 /// of a if-then-else (diamond) are predicated on mutally exclusive
375 /// predicates, where the probability of the true path being taken is given
376 /// by Probability, and Confidence is a measure of our confidence that it
377 /// will be properly predicted.
379 isProfitableToIfCvt(MachineBasicBlock &TMBB,
380 unsigned NumTCycles, unsigned ExtraTCycles,
381 MachineBasicBlock &FMBB,
382 unsigned NumFCycles, unsigned ExtraFCycles,
383 const BranchProbability &Probability) const {
387 /// isProfitableToDupForIfCvt - Return true if it's profitable for
388 /// if-converter to duplicate instructions of specified accumulated
389 /// instruction latencies in the specified MBB to enable if-conversion.
390 /// The probability of the instructions being executed is given by
391 /// Probability, and Confidence is a measure of our confidence that it
392 /// will be properly predicted.
394 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
395 const BranchProbability &Probability) const {
399 /// isProfitableToUnpredicate - Return true if it's profitable to unpredicate
400 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
401 /// exclusive predicates.
409 /// This may be profitable is conditional instructions are always executed.
410 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
411 MachineBasicBlock &FMBB) const {
415 /// canInsertSelect - Return true if it is possible to insert a select
416 /// instruction that chooses between TrueReg and FalseReg based on the
417 /// condition code in Cond.
419 /// When successful, also return the latency in cycles from TrueReg,
420 /// FalseReg, and Cond to the destination register. In most cases, a select
421 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
423 /// Some x86 implementations have 2-cycle cmov instructions.
425 /// @param MBB Block where select instruction would be inserted.
426 /// @param Cond Condition returned by AnalyzeBranch.
427 /// @param TrueReg Virtual register to select when Cond is true.
428 /// @param FalseReg Virtual register to select when Cond is false.
429 /// @param CondCycles Latency from Cond+Branch to select output.
430 /// @param TrueCycles Latency from TrueReg to select output.
431 /// @param FalseCycles Latency from FalseReg to select output.
432 virtual bool canInsertSelect(const MachineBasicBlock &MBB,
433 const SmallVectorImpl<MachineOperand> &Cond,
434 unsigned TrueReg, unsigned FalseReg,
436 int &TrueCycles, int &FalseCycles) const {
440 /// insertSelect - Insert a select instruction into MBB before I that will
441 /// copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when
444 /// This function can only be called after canInsertSelect() returned true.
445 /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
446 /// that the same flags or registers required by Cond are available at the
449 /// @param MBB Block where select instruction should be inserted.
450 /// @param I Insertion point.
451 /// @param DL Source location for debugging.
452 /// @param DstReg Virtual register to be defined by select instruction.
453 /// @param Cond Condition as computed by AnalyzeBranch.
454 /// @param TrueReg Virtual register to copy when Cond is true.
455 /// @param FalseReg Virtual register to copy when Cons is false.
456 virtual void insertSelect(MachineBasicBlock &MBB,
457 MachineBasicBlock::iterator I, DebugLoc DL,
459 const SmallVectorImpl<MachineOperand> &Cond,
460 unsigned TrueReg, unsigned FalseReg) const {
461 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
464 /// analyzeSelect - Analyze the given select instruction, returning true if
465 /// it cannot be understood. It is assumed that MI->isSelect() is true.
467 /// When successful, return the controlling condition and the operands that
468 /// determine the true and false result values.
470 /// Result = SELECT Cond, TrueOp, FalseOp
472 /// Some targets can optimize select instructions, for example by predicating
473 /// the instruction defining one of the operands. Such targets should set
476 /// @param MI Select instruction to analyze.
477 /// @param Cond Condition controlling the select.
478 /// @param TrueOp Operand number of the value selected when Cond is true.
479 /// @param FalseOp Operand number of the value selected when Cond is false.
480 /// @param Optimizable Returned as true if MI is optimizable.
481 /// @returns False on success.
482 virtual bool analyzeSelect(const MachineInstr *MI,
483 SmallVectorImpl<MachineOperand> &Cond,
484 unsigned &TrueOp, unsigned &FalseOp,
485 bool &Optimizable) const {
486 assert(MI && MI->getDesc().isSelect() && "MI must be a select instruction");
490 /// optimizeSelect - Given a select instruction that was understood by
491 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
492 /// merging it with one of its operands. Returns NULL on failure.
494 /// When successful, returns the new select instruction. The client is
495 /// responsible for deleting MI.
497 /// If both sides of the select can be optimized, PreferFalse is used to pick
500 /// @param MI Optimizable select instruction.
501 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
502 /// @returns Optimized instruction or NULL.
503 virtual MachineInstr *optimizeSelect(MachineInstr *MI,
504 bool PreferFalse = false) const {
505 // This function must be implemented if Optimizable is ever set.
506 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
509 /// copyPhysReg - Emit instructions to copy a pair of physical registers.
511 /// This function should support copies within any legal register class as
512 /// well as any cross-class copies created during instruction selection.
514 /// The source and destination registers may overlap, which may require a
515 /// careful implementation when multiple copy instructions are required for
516 /// large registers. See for example the ARM target.
517 virtual void copyPhysReg(MachineBasicBlock &MBB,
518 MachineBasicBlock::iterator MI, DebugLoc DL,
519 unsigned DestReg, unsigned SrcReg,
520 bool KillSrc) const {
521 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
524 /// storeRegToStackSlot - Store the specified register of the given register
525 /// class to the specified stack frame index. The store instruction is to be
526 /// added to the given machine basic block before the specified machine
527 /// instruction. If isKill is true, the register operand is the last use and
528 /// must be marked kill.
529 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
530 MachineBasicBlock::iterator MI,
531 unsigned SrcReg, bool isKill, int FrameIndex,
532 const TargetRegisterClass *RC,
533 const TargetRegisterInfo *TRI) const {
534 llvm_unreachable("Target didn't implement "
535 "TargetInstrInfo::storeRegToStackSlot!");
538 /// loadRegFromStackSlot - Load the specified register of the given register
539 /// class from the specified stack frame index. The load instruction is to be
540 /// added to the given machine basic block before the specified machine
542 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
543 MachineBasicBlock::iterator MI,
544 unsigned DestReg, int FrameIndex,
545 const TargetRegisterClass *RC,
546 const TargetRegisterInfo *TRI) const {
547 llvm_unreachable("Target didn't implement "
548 "TargetInstrInfo::loadRegFromStackSlot!");
551 /// expandPostRAPseudo - This function is called for all pseudo instructions
552 /// that remain after register allocation. Many pseudo instructions are
553 /// created to help register allocation. This is the place to convert them
554 /// into real instructions. The target can edit MI in place, or it can insert
555 /// new instructions and erase MI. The function should return true if
556 /// anything was changed.
557 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
561 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
562 /// slot into the specified machine instruction for the specified operand(s).
563 /// If this is possible, a new instruction is returned with the specified
564 /// operand folded, otherwise NULL is returned.
565 /// The new instruction is inserted before MI, and the client is responsible
566 /// for removing the old instruction.
567 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
568 const SmallVectorImpl<unsigned> &Ops,
569 int FrameIndex) const;
571 /// foldMemoryOperand - Same as the previous version except it allows folding
572 /// of any load and store from / to any address, not just from a specific
574 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
575 const SmallVectorImpl<unsigned> &Ops,
576 MachineInstr* LoadMI) const;
578 /// hasPattern - return true when there is potentially a faster code sequence
579 /// for an instruction chain ending in \p Root. All potential pattern are
580 /// returned in the \p Pattern vector. Pattern should be sorted in priority
581 /// order since the pattern evaluator stops checking as soon as it finds a
583 /// \param Root - Instruction that could be combined with one of its operands
584 /// \param Pattern - Vector of possible combination pattern
586 virtual bool hasPattern(
588 SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Pattern) const {
592 /// genAlternativeCodeSequence - when hasPattern() finds a pattern this
593 /// function generates the instructions that could replace the original code
594 /// sequence. The client has to decide whether the actual replacementment is
595 /// beneficial or not.
596 /// \param Root - Instruction that could be combined with one of its operands
597 /// \param P - Combination pattern for Root
598 /// \param InsInstrs - Vector of new instructions that implement P
599 /// \param DelInstrs - Old instructions, including Root, that could be replaced
601 /// \param InstrIdxForVirtReg - map of virtual register to instruction in
602 /// InsInstr that defines it
603 virtual void genAlternativeCodeSequence(
604 MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P,
605 SmallVectorImpl<MachineInstr *> &InsInstrs,
606 SmallVectorImpl<MachineInstr *> &DelInstrs,
607 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
611 /// useMachineCombiner - return true when a target supports MachineCombiner
612 virtual bool useMachineCombiner(void) const { return false; }
615 /// foldMemoryOperandImpl - Target-dependent implementation for
616 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
617 /// take care of adding a MachineMemOperand to the newly created instruction.
618 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
620 const SmallVectorImpl<unsigned> &Ops,
621 int FrameIndex) const {
625 /// foldMemoryOperandImpl - Target-dependent implementation for
626 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
627 /// take care of adding a MachineMemOperand to the newly created instruction.
628 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
630 const SmallVectorImpl<unsigned> &Ops,
631 MachineInstr* LoadMI) const {
636 /// canFoldMemoryOperand - Returns true for the specified load / store if
637 /// folding is possible.
639 bool canFoldMemoryOperand(const MachineInstr *MI,
640 const SmallVectorImpl<unsigned> &Ops) const;
642 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
643 /// a store or a load and a store into two or more instruction. If this is
644 /// possible, returns true as well as the new instructions by reference.
645 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
646 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
647 SmallVectorImpl<MachineInstr*> &NewMIs) const{
651 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
652 SmallVectorImpl<SDNode*> &NewNodes) const {
656 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
657 /// instruction after load / store are unfolded from an instruction of the
658 /// specified opcode. It returns zero if the specified unfolding is not
659 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
660 /// index of the operand which will hold the register holding the loaded
662 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
663 bool UnfoldLoad, bool UnfoldStore,
664 unsigned *LoadRegIndex = nullptr) const {
668 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
669 /// to determine if two loads are loading from the same base address. It
670 /// should only return true if the base pointers are the same and the
671 /// only differences between the two addresses are the offset. It also returns
672 /// the offsets by reference.
673 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
674 int64_t &Offset1, int64_t &Offset2) const {
678 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
679 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
680 /// be scheduled togther. On some targets if two loads are loading from
681 /// addresses in the same cache line, it's better if they are scheduled
682 /// together. This function takes two integers that represent the load offsets
683 /// from the common base address. It returns true if it decides it's desirable
684 /// to schedule the two loads together. "NumLoads" is the number of loads that
685 /// have already been scheduled after Load1.
686 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
687 int64_t Offset1, int64_t Offset2,
688 unsigned NumLoads) const {
692 /// \brief Get the base register and byte offset of a load/store instr.
693 virtual bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
694 unsigned &BaseReg, unsigned &Offset,
695 const TargetRegisterInfo *TRI) const {
699 virtual bool enableClusterLoads() const { return false; }
701 virtual bool shouldClusterLoads(MachineInstr *FirstLdSt,
702 MachineInstr *SecondLdSt,
703 unsigned NumLoads) const {
707 /// \brief Can this target fuse the given instructions if they are scheduled
709 virtual bool shouldScheduleAdjacent(MachineInstr* First,
710 MachineInstr *Second) const {
714 /// ReverseBranchCondition - Reverses the branch condition of the specified
715 /// condition list, returning false on success and true if it cannot be
718 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
722 /// insertNoop - Insert a noop into the instruction stream at the specified
724 virtual void insertNoop(MachineBasicBlock &MBB,
725 MachineBasicBlock::iterator MI) const;
728 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
729 virtual void getNoopForMachoTarget(MCInst &NopInst) const {
730 // Default to just using 'nop' string.
734 /// isPredicated - Returns true if the instruction is already predicated.
736 virtual bool isPredicated(const MachineInstr *MI) const {
740 /// isUnpredicatedTerminator - Returns true if the instruction is a
741 /// terminator instruction that has not been predicated.
742 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
744 /// PredicateInstruction - Convert the instruction into a predicated
745 /// instruction. It returns true if the operation was successful.
747 bool PredicateInstruction(MachineInstr *MI,
748 const SmallVectorImpl<MachineOperand> &Pred) const;
750 /// SubsumesPredicate - Returns true if the first specified predicate
751 /// subsumes the second, e.g. GE subsumes GT.
753 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
754 const SmallVectorImpl<MachineOperand> &Pred2) const {
758 /// DefinesPredicate - If the specified instruction defines any predicate
759 /// or condition code register(s) used for predication, returns true as well
760 /// as the definition predicate(s) by reference.
761 virtual bool DefinesPredicate(MachineInstr *MI,
762 std::vector<MachineOperand> &Pred) const {
766 /// isPredicable - Return true if the specified instruction can be predicated.
767 /// By default, this returns true for every instruction with a
768 /// PredicateOperand.
769 virtual bool isPredicable(MachineInstr *MI) const {
770 return MI->getDesc().isPredicable();
773 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
774 /// instruction that defines the specified register class.
775 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
779 /// isSchedulingBoundary - Test if the given instruction should be
780 /// considered a scheduling boundary. This primarily includes labels and
782 virtual bool isSchedulingBoundary(const MachineInstr *MI,
783 const MachineBasicBlock *MBB,
784 const MachineFunction &MF) const;
786 /// Measure the specified inline asm to determine an approximation of its
788 virtual unsigned getInlineAsmLength(const char *Str,
789 const MCAsmInfo &MAI) const;
791 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to
792 /// use for this target when scheduling the machine instructions before
793 /// register allocation.
794 virtual ScheduleHazardRecognizer*
795 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
796 const ScheduleDAG *DAG) const;
798 /// CreateTargetMIHazardRecognizer - Allocate and return a hazard recognizer
799 /// to use for this target when scheduling the machine instructions before
800 /// register allocation.
801 virtual ScheduleHazardRecognizer*
802 CreateTargetMIHazardRecognizer(const InstrItineraryData*,
803 const ScheduleDAG *DAG) const;
805 /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard
806 /// recognizer to use for this target when scheduling the machine instructions
807 /// after register allocation.
808 virtual ScheduleHazardRecognizer*
809 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
810 const ScheduleDAG *DAG) const;
812 /// Provide a global flag for disabling the PreRA hazard recognizer that
813 /// targets may choose to honor.
814 bool usePreRAHazardRecognizer() const;
816 /// analyzeCompare - For a comparison instruction, return the source registers
817 /// in SrcReg and SrcReg2 if having two register operands, and the value it
818 /// compares against in CmpValue. Return true if the comparison instruction
820 virtual bool analyzeCompare(const MachineInstr *MI,
821 unsigned &SrcReg, unsigned &SrcReg2,
822 int &Mask, int &Value) const {
826 /// optimizeCompareInstr - See if the comparison instruction can be converted
827 /// into something more efficient. E.g., on ARM most instructions can set the
828 /// flags register, obviating the need for a separate CMP.
829 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr,
830 unsigned SrcReg, unsigned SrcReg2,
832 const MachineRegisterInfo *MRI) const {
836 /// optimizeLoadInstr - Try to remove the load by folding it to a register
837 /// operand at the use. We fold the load instructions if and only if the
838 /// def and use are in the same BB. We only look at one load and see
839 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
840 /// defined by the load we are trying to fold. DefMI returns the machine
841 /// instruction that defines FoldAsLoadDefReg, and the function returns
842 /// the machine instruction generated due to folding.
843 virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,
844 const MachineRegisterInfo *MRI,
845 unsigned &FoldAsLoadDefReg,
846 MachineInstr *&DefMI) const {
850 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
851 /// instruction, try to fold the immediate into the use instruction.
852 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
853 /// then the caller may assume that DefMI has been erased from its parent
854 /// block. The caller may assume that it will not be erased by this
855 /// function otherwise.
856 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
857 unsigned Reg, MachineRegisterInfo *MRI) const {
861 /// getNumMicroOps - Return the number of u-operations the given machine
862 /// instruction will be decoded to on the target cpu. The itinerary's
863 /// IssueWidth is the number of microops that can be dispatched each
864 /// cycle. An instruction with zero microops takes no dispatch resources.
865 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
866 const MachineInstr *MI) const;
868 /// isZeroCost - Return true for pseudo instructions that don't consume any
869 /// machine resources in their current form. These are common cases that the
870 /// scheduler should consider free, rather than conservatively handling them
871 /// as instructions with no itinerary.
872 bool isZeroCost(unsigned Opcode) const {
873 return Opcode <= TargetOpcode::COPY;
876 virtual int getOperandLatency(const InstrItineraryData *ItinData,
877 SDNode *DefNode, unsigned DefIdx,
878 SDNode *UseNode, unsigned UseIdx) const;
880 /// getOperandLatency - Compute and return the use operand latency of a given
881 /// pair of def and use.
882 /// In most cases, the static scheduling itinerary was enough to determine the
883 /// operand latency. But it may not be possible for instructions with variable
884 /// number of defs / uses.
886 /// This is a raw interface to the itinerary that may be directly overriden by
887 /// a target. Use computeOperandLatency to get the best estimate of latency.
888 virtual int getOperandLatency(const InstrItineraryData *ItinData,
889 const MachineInstr *DefMI, unsigned DefIdx,
890 const MachineInstr *UseMI,
891 unsigned UseIdx) const;
893 /// computeOperandLatency - Compute and return the latency of the given data
894 /// dependent def and use when the operand indices are already known.
895 unsigned computeOperandLatency(const InstrItineraryData *ItinData,
896 const MachineInstr *DefMI, unsigned DefIdx,
897 const MachineInstr *UseMI, unsigned UseIdx)
900 /// getInstrLatency - Compute the instruction latency of a given instruction.
901 /// If the instruction has higher cost when predicated, it's returned via
903 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
904 const MachineInstr *MI,
905 unsigned *PredCost = nullptr) const;
907 virtual unsigned getPredicationCost(const MachineInstr *MI) const;
909 virtual int getInstrLatency(const InstrItineraryData *ItinData,
912 /// Return the default expected latency for a def based on it's opcode.
913 unsigned defaultDefLatency(const MCSchedModel *SchedModel,
914 const MachineInstr *DefMI) const;
916 int computeDefOperandLatency(const InstrItineraryData *ItinData,
917 const MachineInstr *DefMI) const;
919 /// isHighLatencyDef - Return true if this opcode has high latency to its
921 virtual bool isHighLatencyDef(int opc) const { return false; }
923 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg'
924 /// and an use in the current loop, return true if the target considered
925 /// it 'high'. This is used by optimization passes such as machine LICM to
926 /// determine whether it makes sense to hoist an instruction out even in
927 /// high register pressure situation.
929 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
930 const MachineRegisterInfo *MRI,
931 const MachineInstr *DefMI, unsigned DefIdx,
932 const MachineInstr *UseMI, unsigned UseIdx) const {
936 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true
937 /// if the target considered it 'low'.
939 bool hasLowDefLatency(const InstrItineraryData *ItinData,
940 const MachineInstr *DefMI, unsigned DefIdx) const;
942 /// verifyInstruction - Perform target specific instruction verification.
944 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const {
948 /// getExecutionDomain - Return the current execution domain and bit mask of
949 /// possible domains for instruction.
951 /// Some micro-architectures have multiple execution domains, and multiple
952 /// opcodes that perform the same operation in different domains. For
953 /// example, the x86 architecture provides the por, orps, and orpd
954 /// instructions that all do the same thing. There is a latency penalty if a
955 /// register is written in one domain and read in another.
957 /// This function returns a pair (domain, mask) containing the execution
958 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
959 /// function can be used to change the opcode to one of the domains in the
960 /// bit mask. Instructions whose execution domain can't be changed should
963 /// The execution domain numbers don't have any special meaning except domain
964 /// 0 is used for instructions that are not associated with any interesting
965 /// execution domain.
967 virtual std::pair<uint16_t, uint16_t>
968 getExecutionDomain(const MachineInstr *MI) const {
969 return std::make_pair(0, 0);
972 /// setExecutionDomain - Change the opcode of MI to execute in Domain.
974 /// The bit (1 << Domain) must be set in the mask returned from
975 /// getExecutionDomain(MI).
977 virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {}
980 /// getPartialRegUpdateClearance - Returns the preferred minimum clearance
981 /// before an instruction with an unwanted partial register update.
983 /// Some instructions only write part of a register, and implicitly need to
984 /// read the other parts of the register. This may cause unwanted stalls
985 /// preventing otherwise unrelated instructions from executing in parallel in
986 /// an out-of-order CPU.
988 /// For example, the x86 instruction cvtsi2ss writes its result to bits
989 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
990 /// the instruction needs to wait for the old value of the register to become
993 /// addps %xmm1, %xmm0
994 /// movaps %xmm0, (%rax)
995 /// cvtsi2ss %rbx, %xmm0
997 /// In the code above, the cvtsi2ss instruction needs to wait for the addps
998 /// instruction before it can issue, even though the high bits of %xmm0
999 /// probably aren't needed.
1001 /// This hook returns the preferred clearance before MI, measured in
1002 /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1003 /// instructions before MI. It should only return a positive value for
1004 /// unwanted dependencies. If the old bits of the defined register have
1005 /// useful values, or if MI is determined to otherwise read the dependency,
1006 /// the hook should return 0.
1008 /// The unwanted dependency may be handled by:
1010 /// 1. Allocating the same register for an MI def and use. That makes the
1011 /// unwanted dependency identical to a required dependency.
1013 /// 2. Allocating a register for the def that has no defs in the previous N
1016 /// 3. Calling breakPartialRegDependency() with the same arguments. This
1017 /// allows the target to insert a dependency breaking instruction.
1020 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
1021 const TargetRegisterInfo *TRI) const {
1022 // The default implementation returns 0 for no partial register dependency.
1026 /// \brief Return the minimum clearance before an instruction that reads an
1027 /// unused register.
1029 /// For example, AVX instructions may copy part of an register operand into
1030 /// the unused high bits of the destination register.
1032 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
1034 /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1035 /// false dependence on any previous write to %xmm0.
1037 /// This hook works similarly to getPartialRegUpdateClearance, except that it
1038 /// does not take an operand index. Instead sets \p OpNum to the index of the
1039 /// unused register.
1040 virtual unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
1041 const TargetRegisterInfo *TRI) const {
1042 // The default implementation returns 0 for no undef register dependency.
1046 /// breakPartialRegDependency - Insert a dependency-breaking instruction
1047 /// before MI to eliminate an unwanted dependency on OpNum.
1049 /// If it wasn't possible to avoid a def in the last N instructions before MI
1050 /// (see getPartialRegUpdateClearance), this hook will be called to break the
1051 /// unwanted dependency.
1053 /// On x86, an xorps instruction can be used as a dependency breaker:
1055 /// addps %xmm1, %xmm0
1056 /// movaps %xmm0, (%rax)
1057 /// xorps %xmm0, %xmm0
1058 /// cvtsi2ss %rbx, %xmm0
1060 /// An <imp-kill> operand should be added to MI if an instruction was
1061 /// inserted. This ties the instructions together in the post-ra scheduler.
1064 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
1065 const TargetRegisterInfo *TRI) const {}
1067 /// Create machine specific model for scheduling.
1068 virtual DFAPacketizer*
1069 CreateTargetScheduleState(const TargetMachine*, const ScheduleDAG*) const {
1074 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
1077 } // End llvm namespace