1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
22 class CalleeSavedInfo;
25 class MachineMemOperand;
30 class TargetRegisterClass;
31 class TargetRegisterInfo;
33 template<class T> class SmallVectorImpl;
36 //---------------------------------------------------------------------------
38 /// TargetInstrInfo - Interface to description of machine instruction set
40 class TargetInstrInfo {
41 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
42 unsigned NumOpcodes; // Number of entries in the desc array
44 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
45 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
47 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
48 virtual ~TargetInstrInfo();
50 unsigned getNumOpcodes() const { return NumOpcodes; }
52 /// get - Return the machine instruction descriptor that corresponds to the
53 /// specified instruction opcode.
55 const TargetInstrDesc &get(unsigned Opcode) const {
56 assert(Opcode < NumOpcodes && "Invalid opcode!");
57 return Descriptors[Opcode];
60 /// isTriviallyReMaterializable - Return true if the instruction is trivially
61 /// rematerializable, meaning it has no side effects and requires no operands
62 /// that aren't always available.
63 bool isTriviallyReMaterializable(const MachineInstr *MI,
64 AliasAnalysis *AA = 0) const {
65 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
66 (MI->getDesc().isRematerializable() &&
67 (isReallyTriviallyReMaterializable(MI, AA) ||
68 isReallyTriviallyReMaterializableGeneric(MI, AA)));
72 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
73 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
74 /// specify whether the instruction is actually trivially rematerializable,
75 /// taking into consideration its operands. This predicate must return false
76 /// if the instruction has any side effects other than producing a value, or
77 /// if it requres any address registers that are not always available.
78 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
79 AliasAnalysis *AA) const {
84 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
85 /// for which the M_REMATERIALIZABLE flag is set and the target hook
86 /// isReallyTriviallyReMaterializable returns false, this function does
87 /// target-independent tests to determine if the instruction is really
88 /// trivially rematerializable.
89 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
90 AliasAnalysis *AA) const;
93 /// isMoveInstr - Return true if the instruction is a register to register
94 /// move and return the source and dest operands and their sub-register
95 /// indices by reference.
96 virtual bool isMoveInstr(const MachineInstr& MI,
97 unsigned& SrcReg, unsigned& DstReg,
98 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
102 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
103 /// extension instruction. That is, it's like a copy where it's legal for the
104 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
105 /// true, then it's expected the pre-extension value is available as a subreg
106 /// of the result register. This also returns the sub-register index in
108 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
109 unsigned &SrcReg, unsigned &DstReg,
110 unsigned &SubIdx) const {
114 /// isIdentityCopy - Return true if the instruction is a copy (or
115 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and
116 /// destination registers are the same.
117 bool isIdentityCopy(const MachineInstr &MI) const {
118 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
119 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
123 if (MI.getOpcode() == TargetOpcode::EXTRACT_SUBREG &&
124 MI.getOperand(0).getReg() == MI.getOperand(1).getReg())
127 if ((MI.getOpcode() == TargetOpcode::INSERT_SUBREG ||
128 MI.getOpcode() == TargetOpcode::SUBREG_TO_REG) &&
129 MI.getOperand(0).getReg() == MI.getOperand(2).getReg())
134 /// isLoadFromStackSlot - If the specified machine instruction is a direct
135 /// load from a stack slot, return the virtual or physical register number of
136 /// the destination along with the FrameIndex of the loaded stack slot. If
137 /// not, return 0. This predicate must return 0 if the instruction has
138 /// any side effects other than loading from the stack slot.
139 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
140 int &FrameIndex) const {
144 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
145 /// stack locations as well. This uses a heuristic so it isn't
146 /// reliable for correctness.
147 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
148 int &FrameIndex) const {
152 /// hasLoadFromStackSlot - If the specified machine instruction has
153 /// a load from a stack slot, return true along with the FrameIndex
154 /// of the loaded stack slot and the machine mem operand containing
155 /// the reference. If not, return false. Unlike
156 /// isLoadFromStackSlot, this returns true for any instructions that
157 /// loads from the stack. This is just a hint, as some cases may be
159 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
160 const MachineMemOperand *&MMO,
161 int &FrameIndex) const {
165 /// isStoreToStackSlot - If the specified machine instruction is a direct
166 /// store to a stack slot, return the virtual or physical register number of
167 /// the source reg along with the FrameIndex of the loaded stack slot. If
168 /// not, return 0. This predicate must return 0 if the instruction has
169 /// any side effects other than storing to the stack slot.
170 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
171 int &FrameIndex) const {
175 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
176 /// stack locations as well. This uses a heuristic so it isn't
177 /// reliable for correctness.
178 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
179 int &FrameIndex) const {
183 /// hasStoreToStackSlot - If the specified machine instruction has a
184 /// store to a stack slot, return true along with the FrameIndex of
185 /// the loaded stack slot and the machine mem operand containing the
186 /// reference. If not, return false. Unlike isStoreToStackSlot,
187 /// this returns true for any instructions that stores to the
188 /// stack. This is just a hint, as some cases may be missed.
189 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
190 const MachineMemOperand *&MMO,
191 int &FrameIndex) const {
195 /// reMaterialize - Re-issue the specified 'original' instruction at the
196 /// specific location targeting a new destination register.
197 /// The register in Orig->getOperand(0).getReg() will be substituted by
198 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
200 virtual void reMaterialize(MachineBasicBlock &MBB,
201 MachineBasicBlock::iterator MI,
202 unsigned DestReg, unsigned SubIdx,
203 const MachineInstr *Orig,
204 const TargetRegisterInfo &TRI) const = 0;
206 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
207 /// MachineFunction::CloneMachineInstr(), but the target may update operands
208 /// that are required to be unique.
210 /// The instruction must be duplicable as indicated by isNotDuplicable().
211 virtual MachineInstr *duplicate(MachineInstr *Orig,
212 MachineFunction &MF) const = 0;
214 /// convertToThreeAddress - This method must be implemented by targets that
215 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
216 /// may be able to convert a two-address instruction into one or more true
217 /// three-address instructions on demand. This allows the X86 target (for
218 /// example) to convert ADD and SHL instructions into LEA instructions if they
219 /// would require register copies due to two-addressness.
221 /// This method returns a null pointer if the transformation cannot be
222 /// performed, otherwise it returns the last new instruction.
224 virtual MachineInstr *
225 convertToThreeAddress(MachineFunction::iterator &MFI,
226 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
230 /// commuteInstruction - If a target has any instructions that are commutable,
231 /// but require converting to a different instruction or making non-trivial
232 /// changes to commute them, this method can overloaded to do this. The
233 /// default implementation of this method simply swaps the first two operands
234 /// of MI and returns it.
236 /// If a target wants to make more aggressive changes, they can construct and
237 /// return a new machine instruction. If an instruction cannot commute, it
238 /// can also return null.
240 /// If NewMI is true, then a new machine instruction must be created.
242 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
243 bool NewMI = false) const = 0;
245 /// findCommutedOpIndices - If specified MI is commutable, return the two
246 /// operand indices that would swap value. Return true if the instruction
247 /// is not in a form which this routine understands.
248 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
249 unsigned &SrcOpIdx2) const = 0;
251 /// produceSameValue - Return true if two machine instructions would produce
252 /// identical values. By default, this is only true when the two instructions
253 /// are deemed identical except for defs.
254 virtual bool produceSameValue(const MachineInstr *MI0,
255 const MachineInstr *MI1) const = 0;
257 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
258 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
259 /// implemented for a target). Upon success, this returns false and returns
260 /// with the following information in various cases:
262 /// 1. If this block ends with no branches (it just falls through to its succ)
263 /// just return false, leaving TBB/FBB null.
264 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
265 /// the destination block.
266 /// 3. If this block ends with a conditional branch and it falls through to a
267 /// successor block, it sets TBB to be the branch destination block and a
268 /// list of operands that evaluate the condition. These operands can be
269 /// passed to other TargetInstrInfo methods to create new branches.
270 /// 4. If this block ends with a conditional branch followed by an
271 /// unconditional branch, it returns the 'true' destination in TBB, the
272 /// 'false' destination in FBB, and a list of operands that evaluate the
273 /// condition. These operands can be passed to other TargetInstrInfo
274 /// methods to create new branches.
276 /// Note that RemoveBranch and InsertBranch must be implemented to support
277 /// cases where this method returns success.
279 /// If AllowModify is true, then this routine is allowed to modify the basic
280 /// block (e.g. delete instructions after the unconditional branch).
282 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
283 MachineBasicBlock *&FBB,
284 SmallVectorImpl<MachineOperand> &Cond,
285 bool AllowModify = false) const {
289 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
290 /// This is only invoked in cases where AnalyzeBranch returns success. It
291 /// returns the number of instructions that were removed.
292 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
293 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
297 /// InsertBranch - Insert branch code into the end of the specified
298 /// MachineBasicBlock. The operands to this method are the same as those
299 /// returned by AnalyzeBranch. This is only invoked in cases where
300 /// AnalyzeBranch returns success. It returns the number of instructions
303 /// It is also invoked by tail merging to add unconditional branches in
304 /// cases where AnalyzeBranch doesn't apply because there was no original
305 /// branch to analyze. At least this much must be implemented, else tail
306 /// merging needs to be disabled.
307 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
308 MachineBasicBlock *FBB,
309 const SmallVectorImpl<MachineOperand> &Cond) const {
310 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
314 /// copyRegToReg - Emit instructions to copy between a pair of registers. It
315 /// returns false if the target does not how to copy between the specified
317 virtual bool copyRegToReg(MachineBasicBlock &MBB,
318 MachineBasicBlock::iterator MI,
319 unsigned DestReg, unsigned SrcReg,
320 const TargetRegisterClass *DestRC,
321 const TargetRegisterClass *SrcRC,
323 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
327 /// storeRegToStackSlot - Store the specified register of the given register
328 /// class to the specified stack frame index. The store instruction is to be
329 /// added to the given machine basic block before the specified machine
330 /// instruction. If isKill is true, the register operand is the last use and
331 /// must be marked kill.
332 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
333 MachineBasicBlock::iterator MI,
334 unsigned SrcReg, bool isKill, int FrameIndex,
335 const TargetRegisterClass *RC,
336 const TargetRegisterInfo *TRI) const {
337 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
340 /// loadRegFromStackSlot - Load the specified register of the given register
341 /// class from the specified stack frame index. The load instruction is to be
342 /// added to the given machine basic block before the specified machine
344 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
345 MachineBasicBlock::iterator MI,
346 unsigned DestReg, int FrameIndex,
347 const TargetRegisterClass *RC,
348 const TargetRegisterInfo *TRI) const {
349 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
352 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
353 /// saved registers and returns true if it isn't possible / profitable to do
354 /// so by issuing a series of store instructions via
355 /// storeRegToStackSlot(). Returns false otherwise.
356 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
357 MachineBasicBlock::iterator MI,
358 const std::vector<CalleeSavedInfo> &CSI,
359 const TargetRegisterInfo *TRI) const {
363 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
364 /// saved registers and returns true if it isn't possible / profitable to do
365 /// so by issuing a series of load instructions via loadRegToStackSlot().
366 /// Returns false otherwise.
367 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
368 MachineBasicBlock::iterator MI,
369 const std::vector<CalleeSavedInfo> &CSI,
370 const TargetRegisterInfo *TRI) const {
374 /// emitFrameIndexDebugValue - Emit a target-dependent form of
375 /// DBG_VALUE encoding the address of a frame index. Addresses would
376 /// normally be lowered the same way as other addresses on the target,
377 /// e.g. in load instructions. For targets that do not support this
378 /// the debug info is simply lost.
379 /// If you add this for a target you should handle this DBG_VALUE in the
380 /// target-specific AsmPrinter code as well; you will probably get invalid
381 /// assembly output if you don't.
382 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
390 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
391 /// slot into the specified machine instruction for the specified operand(s).
392 /// If this is possible, a new instruction is returned with the specified
393 /// operand folded, otherwise NULL is returned. The client is responsible for
394 /// removing the old instruction and adding the new one in the instruction
396 MachineInstr* foldMemoryOperand(MachineFunction &MF,
398 const SmallVectorImpl<unsigned> &Ops,
399 int FrameIndex) const;
401 /// foldMemoryOperand - Same as the previous version except it allows folding
402 /// of any load and store from / to any address, not just from a specific
404 MachineInstr* foldMemoryOperand(MachineFunction &MF,
406 const SmallVectorImpl<unsigned> &Ops,
407 MachineInstr* LoadMI) const;
410 /// foldMemoryOperandImpl - Target-dependent implementation for
411 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
412 /// take care of adding a MachineMemOperand to the newly created instruction.
413 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
415 const SmallVectorImpl<unsigned> &Ops,
416 int FrameIndex) const {
420 /// foldMemoryOperandImpl - Target-dependent implementation for
421 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
422 /// take care of adding a MachineMemOperand to the newly created instruction.
423 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
425 const SmallVectorImpl<unsigned> &Ops,
426 MachineInstr* LoadMI) const {
431 /// canFoldMemoryOperand - Returns true for the specified load / store if
432 /// folding is possible.
434 bool canFoldMemoryOperand(const MachineInstr *MI,
435 const SmallVectorImpl<unsigned> &Ops) const {
439 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
440 /// a store or a load and a store into two or more instruction. If this is
441 /// possible, returns true as well as the new instructions by reference.
442 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
443 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
444 SmallVectorImpl<MachineInstr*> &NewMIs) const{
448 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
449 SmallVectorImpl<SDNode*> &NewNodes) const {
453 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
454 /// instruction after load / store are unfolded from an instruction of the
455 /// specified opcode. It returns zero if the specified unfolding is not
456 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
457 /// index of the operand which will hold the register holding the loaded
459 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
460 bool UnfoldLoad, bool UnfoldStore,
461 unsigned *LoadRegIndex = 0) const {
465 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
466 /// to determine if two loads are loading from the same base address. It
467 /// should only return true if the base pointers are the same and the
468 /// only differences between the two addresses are the offset. It also returns
469 /// the offsets by reference.
470 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
471 int64_t &Offset1, int64_t &Offset2) const {
475 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
476 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
477 /// be scheduled togther. On some targets if two loads are loading from
478 /// addresses in the same cache line, it's better if they are scheduled
479 /// together. This function takes two integers that represent the load offsets
480 /// from the common base address. It returns true if it decides it's desirable
481 /// to schedule the two loads together. "NumLoads" is the number of loads that
482 /// have already been scheduled after Load1.
483 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
484 int64_t Offset1, int64_t Offset2,
485 unsigned NumLoads) const {
489 /// ReverseBranchCondition - Reverses the branch condition of the specified
490 /// condition list, returning false on success and true if it cannot be
493 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
497 /// insertNoop - Insert a noop into the instruction stream at the specified
499 virtual void insertNoop(MachineBasicBlock &MBB,
500 MachineBasicBlock::iterator MI) const;
503 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
504 virtual void getNoopForMachoTarget(MCInst &NopInst) const {
505 // Default to just using 'nop' string.
509 /// isPredicated - Returns true if the instruction is already predicated.
511 virtual bool isPredicated(const MachineInstr *MI) const {
515 /// isUnpredicatedTerminator - Returns true if the instruction is a
516 /// terminator instruction that has not been predicated.
517 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
519 /// PredicateInstruction - Convert the instruction into a predicated
520 /// instruction. It returns true if the operation was successful.
522 bool PredicateInstruction(MachineInstr *MI,
523 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
525 /// SubsumesPredicate - Returns true if the first specified predicate
526 /// subsumes the second, e.g. GE subsumes GT.
528 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
529 const SmallVectorImpl<MachineOperand> &Pred2) const {
533 /// DefinesPredicate - If the specified instruction defines any predicate
534 /// or condition code register(s) used for predication, returns true as well
535 /// as the definition predicate(s) by reference.
536 virtual bool DefinesPredicate(MachineInstr *MI,
537 std::vector<MachineOperand> &Pred) const {
541 /// isPredicable - Return true if the specified instruction can be predicated.
542 /// By default, this returns true for every instruction with a
543 /// PredicateOperand.
544 virtual bool isPredicable(MachineInstr *MI) const {
545 return MI->getDesc().isPredicable();
548 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
549 /// instruction that defines the specified register class.
550 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
554 /// GetInstSize - Returns the size of the specified Instruction.
556 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
557 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
561 /// GetFunctionSizeInBytes - Returns the size of the specified
564 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
566 /// Measure the specified inline asm to determine an approximation of its
568 virtual unsigned getInlineAsmLength(const char *Str,
569 const MCAsmInfo &MAI) const;
572 /// TargetInstrInfoImpl - This is the default implementation of
573 /// TargetInstrInfo, which just provides a couple of default implementations
574 /// for various methods. This separated out because it is implemented in
575 /// libcodegen, not in libtarget.
576 class TargetInstrInfoImpl : public TargetInstrInfo {
578 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
579 : TargetInstrInfo(desc, NumOpcodes) {}
581 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
582 bool NewMI = false) const;
583 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
584 unsigned &SrcOpIdx2) const;
585 virtual bool PredicateInstruction(MachineInstr *MI,
586 const SmallVectorImpl<MachineOperand> &Pred) const;
587 virtual void reMaterialize(MachineBasicBlock &MBB,
588 MachineBasicBlock::iterator MI,
589 unsigned DestReg, unsigned SubReg,
590 const MachineInstr *Orig,
591 const TargetRegisterInfo &TRI) const;
592 virtual MachineInstr *duplicate(MachineInstr *Orig,
593 MachineFunction &MF) const;
594 virtual bool produceSameValue(const MachineInstr *MI0,
595 const MachineInstr *MI1) const;
596 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
599 } // End llvm namespace