1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/MC/MCInstrInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
22 class InstrItineraryData;
25 class MachineMemOperand;
26 class MachineRegisterInfo;
30 class ScheduleHazardRecognizer;
33 class TargetRegisterClass;
34 class TargetRegisterInfo;
36 template<class T> class SmallVectorImpl;
39 //---------------------------------------------------------------------------
41 /// TargetInstrInfo - Interface to description of machine instruction set
43 class TargetInstrInfo : public MCInstrInfo {
44 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
45 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
47 TargetInstrInfo(const MCInstrDesc *desc, unsigned NumOpcodes,
48 int CallFrameSetupOpcode = -1,
49 int CallFrameDestroyOpcode = -1);
50 virtual ~TargetInstrInfo();
52 /// getRegClass - Givem a machine instruction descriptor, returns the register
53 /// class constraint for OpNum, or NULL.
54 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
56 const TargetRegisterInfo *TRI) const;
58 /// isTriviallyReMaterializable - Return true if the instruction is trivially
59 /// rematerializable, meaning it has no side effects and requires no operands
60 /// that aren't always available.
61 bool isTriviallyReMaterializable(const MachineInstr *MI,
62 AliasAnalysis *AA = 0) const {
63 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
64 (MI->getDesc().isRematerializable() &&
65 (isReallyTriviallyReMaterializable(MI, AA) ||
66 isReallyTriviallyReMaterializableGeneric(MI, AA)));
70 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
71 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
72 /// specify whether the instruction is actually trivially rematerializable,
73 /// taking into consideration its operands. This predicate must return false
74 /// if the instruction has any side effects other than producing a value, or
75 /// if it requres any address registers that are not always available.
76 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
77 AliasAnalysis *AA) const {
82 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
83 /// for which the M_REMATERIALIZABLE flag is set and the target hook
84 /// isReallyTriviallyReMaterializable returns false, this function does
85 /// target-independent tests to determine if the instruction is really
86 /// trivially rematerializable.
87 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
88 AliasAnalysis *AA) const;
91 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
92 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
93 /// targets use pseudo instructions in order to abstract away the difference
94 /// between operating with a frame pointer and operating without, through the
95 /// use of these two instructions.
97 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
98 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
100 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
101 /// extension instruction. That is, it's like a copy where it's legal for the
102 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
103 /// true, then it's expected the pre-extension value is available as a subreg
104 /// of the result register. This also returns the sub-register index in
106 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
107 unsigned &SrcReg, unsigned &DstReg,
108 unsigned &SubIdx) const {
112 /// isLoadFromStackSlot - If the specified machine instruction is a direct
113 /// load from a stack slot, return the virtual or physical register number of
114 /// the destination along with the FrameIndex of the loaded stack slot. If
115 /// not, return 0. This predicate must return 0 if the instruction has
116 /// any side effects other than loading from the stack slot.
117 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
118 int &FrameIndex) const {
122 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
123 /// stack locations as well. This uses a heuristic so it isn't
124 /// reliable for correctness.
125 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
126 int &FrameIndex) const {
130 /// hasLoadFromStackSlot - If the specified machine instruction has
131 /// a load from a stack slot, return true along with the FrameIndex
132 /// of the loaded stack slot and the machine mem operand containing
133 /// the reference. If not, return false. Unlike
134 /// isLoadFromStackSlot, this returns true for any instructions that
135 /// loads from the stack. This is just a hint, as some cases may be
137 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
138 const MachineMemOperand *&MMO,
139 int &FrameIndex) const {
143 /// isStoreToStackSlot - If the specified machine instruction is a direct
144 /// store to a stack slot, return the virtual or physical register number of
145 /// the source reg along with the FrameIndex of the loaded stack slot. If
146 /// not, return 0. This predicate must return 0 if the instruction has
147 /// any side effects other than storing to the stack slot.
148 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
149 int &FrameIndex) const {
153 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
154 /// stack locations as well. This uses a heuristic so it isn't
155 /// reliable for correctness.
156 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
157 int &FrameIndex) const {
161 /// hasStoreToStackSlot - If the specified machine instruction has a
162 /// store to a stack slot, return true along with the FrameIndex of
163 /// the loaded stack slot and the machine mem operand containing the
164 /// reference. If not, return false. Unlike isStoreToStackSlot,
165 /// this returns true for any instructions that stores to the
166 /// stack. This is just a hint, as some cases may be missed.
167 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
168 const MachineMemOperand *&MMO,
169 int &FrameIndex) const {
173 /// reMaterialize - Re-issue the specified 'original' instruction at the
174 /// specific location targeting a new destination register.
175 /// The register in Orig->getOperand(0).getReg() will be substituted by
176 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
178 virtual void reMaterialize(MachineBasicBlock &MBB,
179 MachineBasicBlock::iterator MI,
180 unsigned DestReg, unsigned SubIdx,
181 const MachineInstr *Orig,
182 const TargetRegisterInfo &TRI) const = 0;
184 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
185 /// two-addrss instruction inserted by two-address pass.
186 virtual void scheduleTwoAddrSource(MachineInstr *SrcMI,
188 const TargetRegisterInfo &TRI) const {
192 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
193 /// MachineFunction::CloneMachineInstr(), but the target may update operands
194 /// that are required to be unique.
196 /// The instruction must be duplicable as indicated by isNotDuplicable().
197 virtual MachineInstr *duplicate(MachineInstr *Orig,
198 MachineFunction &MF) const = 0;
200 /// convertToThreeAddress - This method must be implemented by targets that
201 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
202 /// may be able to convert a two-address instruction into one or more true
203 /// three-address instructions on demand. This allows the X86 target (for
204 /// example) to convert ADD and SHL instructions into LEA instructions if they
205 /// would require register copies due to two-addressness.
207 /// This method returns a null pointer if the transformation cannot be
208 /// performed, otherwise it returns the last new instruction.
210 virtual MachineInstr *
211 convertToThreeAddress(MachineFunction::iterator &MFI,
212 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
216 /// commuteInstruction - If a target has any instructions that are
217 /// commutable but require converting to different instructions or making
218 /// non-trivial changes to commute them, this method can overloaded to do
219 /// that. The default implementation simply swaps the commutable operands.
220 /// If NewMI is false, MI is modified in place and returned; otherwise, a
221 /// new machine instruction is created and returned. Do not call this
222 /// method for a non-commutable instruction, but there may be some cases
223 /// where this method fails and returns null.
224 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
225 bool NewMI = false) const = 0;
227 /// findCommutedOpIndices - If specified MI is commutable, return the two
228 /// operand indices that would swap value. Return false if the instruction
229 /// is not in a form which this routine understands.
230 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
231 unsigned &SrcOpIdx2) const = 0;
233 /// produceSameValue - Return true if two machine instructions would produce
234 /// identical values. By default, this is only true when the two instructions
235 /// are deemed identical except for defs. If this function is called when the
236 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
237 /// aggressive checks.
238 virtual bool produceSameValue(const MachineInstr *MI0,
239 const MachineInstr *MI1,
240 const MachineRegisterInfo *MRI = 0) const = 0;
242 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
243 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
244 /// implemented for a target). Upon success, this returns false and returns
245 /// with the following information in various cases:
247 /// 1. If this block ends with no branches (it just falls through to its succ)
248 /// just return false, leaving TBB/FBB null.
249 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
250 /// the destination block.
251 /// 3. If this block ends with a conditional branch and it falls through to a
252 /// successor block, it sets TBB to be the branch destination block and a
253 /// list of operands that evaluate the condition. These operands can be
254 /// passed to other TargetInstrInfo methods to create new branches.
255 /// 4. If this block ends with a conditional branch followed by an
256 /// unconditional branch, it returns the 'true' destination in TBB, the
257 /// 'false' destination in FBB, and a list of operands that evaluate the
258 /// condition. These operands can be passed to other TargetInstrInfo
259 /// methods to create new branches.
261 /// Note that RemoveBranch and InsertBranch must be implemented to support
262 /// cases where this method returns success.
264 /// If AllowModify is true, then this routine is allowed to modify the basic
265 /// block (e.g. delete instructions after the unconditional branch).
267 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
268 MachineBasicBlock *&FBB,
269 SmallVectorImpl<MachineOperand> &Cond,
270 bool AllowModify = false) const {
274 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
275 /// This is only invoked in cases where AnalyzeBranch returns success. It
276 /// returns the number of instructions that were removed.
277 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
278 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
282 /// InsertBranch - Insert branch code into the end of the specified
283 /// MachineBasicBlock. The operands to this method are the same as those
284 /// returned by AnalyzeBranch. This is only invoked in cases where
285 /// AnalyzeBranch returns success. It returns the number of instructions
288 /// It is also invoked by tail merging to add unconditional branches in
289 /// cases where AnalyzeBranch doesn't apply because there was no original
290 /// branch to analyze. At least this much must be implemented, else tail
291 /// merging needs to be disabled.
292 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
293 MachineBasicBlock *FBB,
294 const SmallVectorImpl<MachineOperand> &Cond,
296 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
300 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
301 /// after it, replacing it with an unconditional branch to NewDest. This is
302 /// used by the tail merging pass.
303 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
304 MachineBasicBlock *NewDest) const = 0;
306 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic
307 /// block at the specified instruction (i.e. instruction would be the start
308 /// of a new basic block).
309 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
310 MachineBasicBlock::iterator MBBI) const {
314 /// isProfitableToIfCvt - Return true if it's profitable to predicate
315 /// instructions with accumulated instruction latency of "NumCycles"
316 /// of the specified basic block, where the probability of the instructions
317 /// being executed is given by Probability, and Confidence is a measure
318 /// of our confidence that it will be properly predicted.
320 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
321 unsigned ExtraPredCycles,
322 float Probability, float Confidence) const {
326 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one
327 /// checks for the case where two basic blocks from true and false path
328 /// of a if-then-else (diamond) are predicated on mutally exclusive
329 /// predicates, where the probability of the true path being taken is given
330 /// by Probability, and Confidence is a measure of our confidence that it
331 /// will be properly predicted.
333 isProfitableToIfCvt(MachineBasicBlock &TMBB,
334 unsigned NumTCycles, unsigned ExtraTCycles,
335 MachineBasicBlock &FMBB,
336 unsigned NumFCycles, unsigned ExtraFCycles,
337 float Probability, float Confidence) const {
341 /// isProfitableToDupForIfCvt - Return true if it's profitable for
342 /// if-converter to duplicate instructions of specified accumulated
343 /// instruction latencies in the specified MBB to enable if-conversion.
344 /// The probability of the instructions being executed is given by
345 /// Probability, and Confidence is a measure of our confidence that it
346 /// will be properly predicted.
348 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
349 float Probability, float Confidence) const {
353 /// copyPhysReg - Emit instructions to copy a pair of physical registers.
354 virtual void copyPhysReg(MachineBasicBlock &MBB,
355 MachineBasicBlock::iterator MI, DebugLoc DL,
356 unsigned DestReg, unsigned SrcReg,
357 bool KillSrc) const {
358 assert(0 && "Target didn't implement TargetInstrInfo::copyPhysReg!");
361 /// storeRegToStackSlot - Store the specified register of the given register
362 /// class to the specified stack frame index. The store instruction is to be
363 /// added to the given machine basic block before the specified machine
364 /// instruction. If isKill is true, the register operand is the last use and
365 /// must be marked kill.
366 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
367 MachineBasicBlock::iterator MI,
368 unsigned SrcReg, bool isKill, int FrameIndex,
369 const TargetRegisterClass *RC,
370 const TargetRegisterInfo *TRI) const {
371 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
374 /// loadRegFromStackSlot - Load the specified register of the given register
375 /// class from the specified stack frame index. The load instruction is to be
376 /// added to the given machine basic block before the specified machine
378 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
379 MachineBasicBlock::iterator MI,
380 unsigned DestReg, int FrameIndex,
381 const TargetRegisterClass *RC,
382 const TargetRegisterInfo *TRI) const {
383 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
386 /// emitFrameIndexDebugValue - Emit a target-dependent form of
387 /// DBG_VALUE encoding the address of a frame index. Addresses would
388 /// normally be lowered the same way as other addresses on the target,
389 /// e.g. in load instructions. For targets that do not support this
390 /// the debug info is simply lost.
391 /// If you add this for a target you should handle this DBG_VALUE in the
392 /// target-specific AsmPrinter code as well; you will probably get invalid
393 /// assembly output if you don't.
394 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
402 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
403 /// slot into the specified machine instruction for the specified operand(s).
404 /// If this is possible, a new instruction is returned with the specified
405 /// operand folded, otherwise NULL is returned.
406 /// The new instruction is inserted before MI, and the client is responsible
407 /// for removing the old instruction.
408 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
409 const SmallVectorImpl<unsigned> &Ops,
410 int FrameIndex) const;
412 /// foldMemoryOperand - Same as the previous version except it allows folding
413 /// of any load and store from / to any address, not just from a specific
415 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
416 const SmallVectorImpl<unsigned> &Ops,
417 MachineInstr* LoadMI) const;
420 /// foldMemoryOperandImpl - Target-dependent implementation for
421 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
422 /// take care of adding a MachineMemOperand to the newly created instruction.
423 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
425 const SmallVectorImpl<unsigned> &Ops,
426 int FrameIndex) const {
430 /// foldMemoryOperandImpl - Target-dependent implementation for
431 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
432 /// take care of adding a MachineMemOperand to the newly created instruction.
433 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
435 const SmallVectorImpl<unsigned> &Ops,
436 MachineInstr* LoadMI) const {
441 /// canFoldMemoryOperand - Returns true for the specified load / store if
442 /// folding is possible.
444 bool canFoldMemoryOperand(const MachineInstr *MI,
445 const SmallVectorImpl<unsigned> &Ops) const =0;
447 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
448 /// a store or a load and a store into two or more instruction. If this is
449 /// possible, returns true as well as the new instructions by reference.
450 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
451 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
452 SmallVectorImpl<MachineInstr*> &NewMIs) const{
456 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
457 SmallVectorImpl<SDNode*> &NewNodes) const {
461 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
462 /// instruction after load / store are unfolded from an instruction of the
463 /// specified opcode. It returns zero if the specified unfolding is not
464 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
465 /// index of the operand which will hold the register holding the loaded
467 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
468 bool UnfoldLoad, bool UnfoldStore,
469 unsigned *LoadRegIndex = 0) const {
473 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
474 /// to determine if two loads are loading from the same base address. It
475 /// should only return true if the base pointers are the same and the
476 /// only differences between the two addresses are the offset. It also returns
477 /// the offsets by reference.
478 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
479 int64_t &Offset1, int64_t &Offset2) const {
483 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
484 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
485 /// be scheduled togther. On some targets if two loads are loading from
486 /// addresses in the same cache line, it's better if they are scheduled
487 /// together. This function takes two integers that represent the load offsets
488 /// from the common base address. It returns true if it decides it's desirable
489 /// to schedule the two loads together. "NumLoads" is the number of loads that
490 /// have already been scheduled after Load1.
491 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
492 int64_t Offset1, int64_t Offset2,
493 unsigned NumLoads) const {
497 /// ReverseBranchCondition - Reverses the branch condition of the specified
498 /// condition list, returning false on success and true if it cannot be
501 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
505 /// insertNoop - Insert a noop into the instruction stream at the specified
507 virtual void insertNoop(MachineBasicBlock &MBB,
508 MachineBasicBlock::iterator MI) const;
511 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
512 virtual void getNoopForMachoTarget(MCInst &NopInst) const {
513 // Default to just using 'nop' string.
517 /// isPredicated - Returns true if the instruction is already predicated.
519 virtual bool isPredicated(const MachineInstr *MI) const {
523 /// isUnpredicatedTerminator - Returns true if the instruction is a
524 /// terminator instruction that has not been predicated.
525 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
527 /// PredicateInstruction - Convert the instruction into a predicated
528 /// instruction. It returns true if the operation was successful.
530 bool PredicateInstruction(MachineInstr *MI,
531 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
533 /// SubsumesPredicate - Returns true if the first specified predicate
534 /// subsumes the second, e.g. GE subsumes GT.
536 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
537 const SmallVectorImpl<MachineOperand> &Pred2) const {
541 /// DefinesPredicate - If the specified instruction defines any predicate
542 /// or condition code register(s) used for predication, returns true as well
543 /// as the definition predicate(s) by reference.
544 virtual bool DefinesPredicate(MachineInstr *MI,
545 std::vector<MachineOperand> &Pred) const {
549 /// isPredicable - Return true if the specified instruction can be predicated.
550 /// By default, this returns true for every instruction with a
551 /// PredicateOperand.
552 virtual bool isPredicable(MachineInstr *MI) const {
553 return MI->getDesc().isPredicable();
556 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
557 /// instruction that defines the specified register class.
558 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
562 /// isSchedulingBoundary - Test if the given instruction should be
563 /// considered a scheduling boundary. This primarily includes labels and
565 virtual bool isSchedulingBoundary(const MachineInstr *MI,
566 const MachineBasicBlock *MBB,
567 const MachineFunction &MF) const = 0;
569 /// Measure the specified inline asm to determine an approximation of its
571 virtual unsigned getInlineAsmLength(const char *Str,
572 const MCAsmInfo &MAI) const;
574 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to
575 /// use for this target when scheduling the machine instructions before
576 /// register allocation.
577 virtual ScheduleHazardRecognizer*
578 CreateTargetHazardRecognizer(const TargetMachine *TM,
579 const ScheduleDAG *DAG) const = 0;
581 /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard
582 /// recognizer to use for this target when scheduling the machine instructions
583 /// after register allocation.
584 virtual ScheduleHazardRecognizer*
585 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
586 const ScheduleDAG *DAG) const = 0;
588 /// AnalyzeCompare - For a comparison instruction, return the source register
589 /// in SrcReg and the value it compares against in CmpValue. Return true if
590 /// the comparison instruction can be analyzed.
591 virtual bool AnalyzeCompare(const MachineInstr *MI,
592 unsigned &SrcReg, int &Mask, int &Value) const {
596 /// OptimizeCompareInstr - See if the comparison instruction can be converted
597 /// into something more efficient. E.g., on ARM most instructions can set the
598 /// flags register, obviating the need for a separate CMP.
599 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr,
600 unsigned SrcReg, int Mask, int Value,
601 const MachineRegisterInfo *MRI) const {
605 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
606 /// instruction, try to fold the immediate into the use instruction.
607 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
608 unsigned Reg, MachineRegisterInfo *MRI) const {
612 /// getNumMicroOps - Return the number of u-operations the given machine
613 /// instruction will be decoded to on the target cpu.
614 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
615 const MachineInstr *MI) const;
617 /// isZeroCost - Return true for pseudo instructions that don't consume any
618 /// machine resources in their current form. These are common cases that the
619 /// scheduler should consider free, rather than conservatively handling them
620 /// as instructions with no itinerary.
621 bool isZeroCost(unsigned Opcode) const {
622 return Opcode <= TargetOpcode::COPY;
625 /// getOperandLatency - Compute and return the use operand latency of a given
626 /// pair of def and use.
627 /// In most cases, the static scheduling itinerary was enough to determine the
628 /// operand latency. But it may not be possible for instructions with variable
629 /// number of defs / uses.
630 virtual int getOperandLatency(const InstrItineraryData *ItinData,
631 const MachineInstr *DefMI, unsigned DefIdx,
632 const MachineInstr *UseMI, unsigned UseIdx) const;
634 virtual int getOperandLatency(const InstrItineraryData *ItinData,
635 SDNode *DefNode, unsigned DefIdx,
636 SDNode *UseNode, unsigned UseIdx) const;
638 /// getInstrLatency - Compute the instruction latency of a given instruction.
639 /// If the instruction has higher cost when predicated, it's returned via
641 virtual int getInstrLatency(const InstrItineraryData *ItinData,
642 const MachineInstr *MI,
643 unsigned *PredCost = 0) const;
645 virtual int getInstrLatency(const InstrItineraryData *ItinData,
648 /// isHighLatencyDef - Return true if this opcode has high latency to its
650 virtual bool isHighLatencyDef(int opc) const { return false; }
652 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg'
653 /// and an use in the current loop, return true if the target considered
654 /// it 'high'. This is used by optimization passes such as machine LICM to
655 /// determine whether it makes sense to hoist an instruction out even in
656 /// high register pressure situation.
658 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
659 const MachineRegisterInfo *MRI,
660 const MachineInstr *DefMI, unsigned DefIdx,
661 const MachineInstr *UseMI, unsigned UseIdx) const {
665 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true
666 /// if the target considered it 'low'.
668 bool hasLowDefLatency(const InstrItineraryData *ItinData,
669 const MachineInstr *DefMI, unsigned DefIdx) const;
672 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
675 /// TargetInstrInfoImpl - This is the default implementation of
676 /// TargetInstrInfo, which just provides a couple of default implementations
677 /// for various methods. This separated out because it is implemented in
678 /// libcodegen, not in libtarget.
679 class TargetInstrInfoImpl : public TargetInstrInfo {
681 TargetInstrInfoImpl(const MCInstrDesc *desc, unsigned NumOpcodes,
682 int CallFrameSetupOpcode = -1,
683 int CallFrameDestroyOpcode = -1)
684 : TargetInstrInfo(desc, NumOpcodes) {}
686 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
687 MachineBasicBlock *NewDest) const;
688 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
689 bool NewMI = false) const;
690 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
691 unsigned &SrcOpIdx2) const;
692 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
693 const SmallVectorImpl<unsigned> &Ops) const;
694 virtual bool PredicateInstruction(MachineInstr *MI,
695 const SmallVectorImpl<MachineOperand> &Pred) const;
696 virtual void reMaterialize(MachineBasicBlock &MBB,
697 MachineBasicBlock::iterator MI,
698 unsigned DestReg, unsigned SubReg,
699 const MachineInstr *Orig,
700 const TargetRegisterInfo &TRI) const;
701 virtual MachineInstr *duplicate(MachineInstr *Orig,
702 MachineFunction &MF) const;
703 virtual bool produceSameValue(const MachineInstr *MI0,
704 const MachineInstr *MI1,
705 const MachineRegisterInfo *MRI) const;
706 virtual bool isSchedulingBoundary(const MachineInstr *MI,
707 const MachineBasicBlock *MBB,
708 const MachineFunction &MF) const;
710 bool usePreRAHazardRecognizer() const;
712 virtual ScheduleHazardRecognizer *
713 CreateTargetHazardRecognizer(const TargetMachine*, const ScheduleDAG*) const;
715 virtual ScheduleHazardRecognizer *
716 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
717 const ScheduleDAG*) const;
720 } // End llvm namespace