1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/DFAPacketizer.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineCombinerPattern.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
27 class InstrItineraryData;
30 class MachineMemOperand;
31 class MachineRegisterInfo;
35 class MCSymbolRefExpr;
37 class ScheduleHazardRecognizer;
40 class TargetRegisterClass;
41 class TargetRegisterInfo;
42 class BranchProbability;
43 class TargetSubtargetInfo;
45 template<class T> class SmallVectorImpl;
48 //---------------------------------------------------------------------------
50 /// TargetInstrInfo - Interface to description of machine instruction set
52 class TargetInstrInfo : public MCInstrInfo {
53 TargetInstrInfo(const TargetInstrInfo &) LLVM_DELETED_FUNCTION;
54 void operator=(const TargetInstrInfo &) LLVM_DELETED_FUNCTION;
56 TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1)
57 : CallFrameSetupOpcode(CFSetupOpcode),
58 CallFrameDestroyOpcode(CFDestroyOpcode) {
61 virtual ~TargetInstrInfo();
63 /// getRegClass - Givem a machine instruction descriptor, returns the register
64 /// class constraint for OpNum, or NULL.
65 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
67 const TargetRegisterInfo *TRI,
68 const MachineFunction &MF) const;
70 /// isTriviallyReMaterializable - Return true if the instruction is trivially
71 /// rematerializable, meaning it has no side effects and requires no operands
72 /// that aren't always available.
73 bool isTriviallyReMaterializable(const MachineInstr *MI,
74 AliasAnalysis *AA = nullptr) const {
75 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
76 (MI->getDesc().isRematerializable() &&
77 (isReallyTriviallyReMaterializable(MI, AA) ||
78 isReallyTriviallyReMaterializableGeneric(MI, AA)));
82 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
83 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
84 /// specify whether the instruction is actually trivially rematerializable,
85 /// taking into consideration its operands. This predicate must return false
86 /// if the instruction has any side effects other than producing a value, or
87 /// if it requres any address registers that are not always available.
88 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
89 AliasAnalysis *AA) const {
94 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
95 /// for which the M_REMATERIALIZABLE flag is set and the target hook
96 /// isReallyTriviallyReMaterializable returns false, this function does
97 /// target-independent tests to determine if the instruction is really
98 /// trivially rematerializable.
99 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
100 AliasAnalysis *AA) const;
103 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
104 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
105 /// targets use pseudo instructions in order to abstract away the difference
106 /// between operating with a frame pointer and operating without, through the
107 /// use of these two instructions.
109 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
110 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
112 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
113 /// extension instruction. That is, it's like a copy where it's legal for the
114 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
115 /// true, then it's expected the pre-extension value is available as a subreg
116 /// of the result register. This also returns the sub-register index in
118 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
119 unsigned &SrcReg, unsigned &DstReg,
120 unsigned &SubIdx) const {
124 /// isLoadFromStackSlot - If the specified machine instruction is a direct
125 /// load from a stack slot, return the virtual or physical register number of
126 /// the destination along with the FrameIndex of the loaded stack slot. If
127 /// not, return 0. This predicate must return 0 if the instruction has
128 /// any side effects other than loading from the stack slot.
129 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
130 int &FrameIndex) const {
134 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
135 /// stack locations as well. This uses a heuristic so it isn't
136 /// reliable for correctness.
137 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
138 int &FrameIndex) const {
142 /// hasLoadFromStackSlot - If the specified machine instruction has
143 /// a load from a stack slot, return true along with the FrameIndex
144 /// of the loaded stack slot and the machine mem operand containing
145 /// the reference. If not, return false. Unlike
146 /// isLoadFromStackSlot, this returns true for any instructions that
147 /// loads from the stack. This is just a hint, as some cases may be
149 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
150 const MachineMemOperand *&MMO,
151 int &FrameIndex) const;
153 /// isStoreToStackSlot - If the specified machine instruction is a direct
154 /// store to a stack slot, return the virtual or physical register number of
155 /// the source reg along with the FrameIndex of the loaded stack slot. If
156 /// not, return 0. This predicate must return 0 if the instruction has
157 /// any side effects other than storing to the stack slot.
158 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
159 int &FrameIndex) const {
163 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
164 /// stack locations as well. This uses a heuristic so it isn't
165 /// reliable for correctness.
166 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
167 int &FrameIndex) const {
171 /// hasStoreToStackSlot - If the specified machine instruction has a
172 /// store to a stack slot, return true along with the FrameIndex of
173 /// the loaded stack slot and the machine mem operand containing the
174 /// reference. If not, return false. Unlike isStoreToStackSlot,
175 /// this returns true for any instructions that stores to the
176 /// stack. This is just a hint, as some cases may be missed.
177 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
178 const MachineMemOperand *&MMO,
179 int &FrameIndex) const;
181 /// isStackSlotCopy - Return true if the specified machine instruction
182 /// is a copy of one stack slot to another and has no other effect.
183 /// Provide the identity of the two frame indices.
184 virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
185 int &SrcFrameIndex) const {
189 /// Compute the size in bytes and offset within a stack slot of a spilled
190 /// register or subregister.
192 /// \param [out] Size in bytes of the spilled value.
193 /// \param [out] Offset in bytes within the stack slot.
194 /// \returns true if both Size and Offset are successfully computed.
196 /// Not all subregisters have computable spill slots. For example,
197 /// subregisters registers may not be byte-sized, and a pair of discontiguous
198 /// subregisters has no single offset.
200 /// Targets with nontrivial bigendian implementations may need to override
201 /// this, particularly to support spilled vector registers.
202 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
203 unsigned &Size, unsigned &Offset,
204 const TargetMachine *TM) const;
206 /// isAsCheapAsAMove - Return true if the instruction is as cheap as a move
209 /// Targets for different archs need to override this, and different
210 /// micro-architectures can also be finely tuned inside.
211 virtual bool isAsCheapAsAMove(const MachineInstr *MI) const {
212 return MI->isAsCheapAsAMove();
215 /// reMaterialize - Re-issue the specified 'original' instruction at the
216 /// specific location targeting a new destination register.
217 /// The register in Orig->getOperand(0).getReg() will be substituted by
218 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
220 virtual void reMaterialize(MachineBasicBlock &MBB,
221 MachineBasicBlock::iterator MI,
222 unsigned DestReg, unsigned SubIdx,
223 const MachineInstr *Orig,
224 const TargetRegisterInfo &TRI) const;
226 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
227 /// MachineFunction::CloneMachineInstr(), but the target may update operands
228 /// that are required to be unique.
230 /// The instruction must be duplicable as indicated by isNotDuplicable().
231 virtual MachineInstr *duplicate(MachineInstr *Orig,
232 MachineFunction &MF) const;
234 /// convertToThreeAddress - This method must be implemented by targets that
235 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
236 /// may be able to convert a two-address instruction into one or more true
237 /// three-address instructions on demand. This allows the X86 target (for
238 /// example) to convert ADD and SHL instructions into LEA instructions if they
239 /// would require register copies due to two-addressness.
241 /// This method returns a null pointer if the transformation cannot be
242 /// performed, otherwise it returns the last new instruction.
244 virtual MachineInstr *
245 convertToThreeAddress(MachineFunction::iterator &MFI,
246 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
250 /// commuteInstruction - If a target has any instructions that are
251 /// commutable but require converting to different instructions or making
252 /// non-trivial changes to commute them, this method can overloaded to do
253 /// that. The default implementation simply swaps the commutable operands.
254 /// If NewMI is false, MI is modified in place and returned; otherwise, a
255 /// new machine instruction is created and returned. Do not call this
256 /// method for a non-commutable instruction, but there may be some cases
257 /// where this method fails and returns null.
258 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
259 bool NewMI = false) const;
261 /// findCommutedOpIndices - If specified MI is commutable, return the two
262 /// operand indices that would swap value. Return false if the instruction
263 /// is not in a form which this routine understands.
264 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
265 unsigned &SrcOpIdx2) const;
267 /// A pair composed of a register and a sub-register index.
268 /// Used to give some type checking when modeling Reg:SubReg.
269 struct RegSubRegPair {
272 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
273 : Reg(Reg), SubReg(SubReg) {}
275 /// A pair composed of a pair of a register and a sub-register index,
276 /// and another sub-register index.
277 /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
278 struct RegSubRegPairAndIdx : RegSubRegPair {
280 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
282 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
285 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
287 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
288 /// the list is modeled as <Reg:SubReg, SubIdx>.
289 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
291 /// - vreg1:sub1, sub0
292 /// - vreg2<:0>, sub1
294 /// \returns true if it is possible to build such an input sequence
295 /// with the pair \p MI, \p DefIdx. False otherwise.
297 /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
299 /// \note The generic implementation does not provide any support for
300 /// MI.isRegSequenceLike(). In other words, one has to override
301 /// getRegSequenceLikeInputs for target specific instructions.
303 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
304 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
306 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
308 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
309 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
310 /// - vreg1:sub1, sub0
312 /// \returns true if it is possible to build such an input sequence
313 /// with the pair \p MI, \p DefIdx. False otherwise.
315 /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
317 /// \note The generic implementation does not provide any support for
318 /// MI.isExtractSubregLike(). In other words, one has to override
319 /// getExtractSubregLikeInputs for target specific instructions.
321 getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
322 RegSubRegPairAndIdx &InputReg) const;
324 /// produceSameValue - Return true if two machine instructions would produce
325 /// identical values. By default, this is only true when the two instructions
326 /// are deemed identical except for defs. If this function is called when the
327 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
328 /// aggressive checks.
329 virtual bool produceSameValue(const MachineInstr *MI0,
330 const MachineInstr *MI1,
331 const MachineRegisterInfo *MRI = nullptr) const;
333 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
334 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
335 /// implemented for a target). Upon success, this returns false and returns
336 /// with the following information in various cases:
338 /// 1. If this block ends with no branches (it just falls through to its succ)
339 /// just return false, leaving TBB/FBB null.
340 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
341 /// the destination block.
342 /// 3. If this block ends with a conditional branch and it falls through to a
343 /// successor block, it sets TBB to be the branch destination block and a
344 /// list of operands that evaluate the condition. These operands can be
345 /// passed to other TargetInstrInfo methods to create new branches.
346 /// 4. If this block ends with a conditional branch followed by an
347 /// unconditional branch, it returns the 'true' destination in TBB, the
348 /// 'false' destination in FBB, and a list of operands that evaluate the
349 /// condition. These operands can be passed to other TargetInstrInfo
350 /// methods to create new branches.
352 /// Note that RemoveBranch and InsertBranch must be implemented to support
353 /// cases where this method returns success.
355 /// If AllowModify is true, then this routine is allowed to modify the basic
356 /// block (e.g. delete instructions after the unconditional branch).
358 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
359 MachineBasicBlock *&FBB,
360 SmallVectorImpl<MachineOperand> &Cond,
361 bool AllowModify = false) const {
365 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
366 /// This is only invoked in cases where AnalyzeBranch returns success. It
367 /// returns the number of instructions that were removed.
368 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
369 llvm_unreachable("Target didn't implement TargetInstrInfo::RemoveBranch!");
372 /// InsertBranch - Insert branch code into the end of the specified
373 /// MachineBasicBlock. The operands to this method are the same as those
374 /// returned by AnalyzeBranch. This is only invoked in cases where
375 /// AnalyzeBranch returns success. It returns the number of instructions
378 /// It is also invoked by tail merging to add unconditional branches in
379 /// cases where AnalyzeBranch doesn't apply because there was no original
380 /// branch to analyze. At least this much must be implemented, else tail
381 /// merging needs to be disabled.
382 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
383 MachineBasicBlock *FBB,
384 const SmallVectorImpl<MachineOperand> &Cond,
386 llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!");
389 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
390 /// after it, replacing it with an unconditional branch to NewDest. This is
391 /// used by the tail merging pass.
392 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
393 MachineBasicBlock *NewDest) const;
395 /// getUnconditionalBranch - Get an instruction that performs an unconditional
396 /// branch to the given symbol.
398 getUnconditionalBranch(MCInst &MI,
399 const MCSymbolRefExpr *BranchTarget) const {
400 llvm_unreachable("Target didn't implement "
401 "TargetInstrInfo::getUnconditionalBranch!");
404 /// getTrap - Get a machine trap instruction
405 virtual void getTrap(MCInst &MI) const {
406 llvm_unreachable("Target didn't implement TargetInstrInfo::getTrap!");
409 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic
410 /// block at the specified instruction (i.e. instruction would be the start
411 /// of a new basic block).
412 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
413 MachineBasicBlock::iterator MBBI) const {
417 /// isProfitableToIfCvt - Return true if it's profitable to predicate
418 /// instructions with accumulated instruction latency of "NumCycles"
419 /// of the specified basic block, where the probability of the instructions
420 /// being executed is given by Probability, and Confidence is a measure
421 /// of our confidence that it will be properly predicted.
423 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
424 unsigned ExtraPredCycles,
425 const BranchProbability &Probability) const {
429 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one
430 /// checks for the case where two basic blocks from true and false path
431 /// of a if-then-else (diamond) are predicated on mutally exclusive
432 /// predicates, where the probability of the true path being taken is given
433 /// by Probability, and Confidence is a measure of our confidence that it
434 /// will be properly predicted.
436 isProfitableToIfCvt(MachineBasicBlock &TMBB,
437 unsigned NumTCycles, unsigned ExtraTCycles,
438 MachineBasicBlock &FMBB,
439 unsigned NumFCycles, unsigned ExtraFCycles,
440 const BranchProbability &Probability) const {
444 /// isProfitableToDupForIfCvt - Return true if it's profitable for
445 /// if-converter to duplicate instructions of specified accumulated
446 /// instruction latencies in the specified MBB to enable if-conversion.
447 /// The probability of the instructions being executed is given by
448 /// Probability, and Confidence is a measure of our confidence that it
449 /// will be properly predicted.
451 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
452 const BranchProbability &Probability) const {
456 /// isProfitableToUnpredicate - Return true if it's profitable to unpredicate
457 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
458 /// exclusive predicates.
466 /// This may be profitable is conditional instructions are always executed.
467 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
468 MachineBasicBlock &FMBB) const {
472 /// canInsertSelect - Return true if it is possible to insert a select
473 /// instruction that chooses between TrueReg and FalseReg based on the
474 /// condition code in Cond.
476 /// When successful, also return the latency in cycles from TrueReg,
477 /// FalseReg, and Cond to the destination register. In most cases, a select
478 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
480 /// Some x86 implementations have 2-cycle cmov instructions.
482 /// @param MBB Block where select instruction would be inserted.
483 /// @param Cond Condition returned by AnalyzeBranch.
484 /// @param TrueReg Virtual register to select when Cond is true.
485 /// @param FalseReg Virtual register to select when Cond is false.
486 /// @param CondCycles Latency from Cond+Branch to select output.
487 /// @param TrueCycles Latency from TrueReg to select output.
488 /// @param FalseCycles Latency from FalseReg to select output.
489 virtual bool canInsertSelect(const MachineBasicBlock &MBB,
490 const SmallVectorImpl<MachineOperand> &Cond,
491 unsigned TrueReg, unsigned FalseReg,
493 int &TrueCycles, int &FalseCycles) const {
497 /// insertSelect - Insert a select instruction into MBB before I that will
498 /// copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when
501 /// This function can only be called after canInsertSelect() returned true.
502 /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
503 /// that the same flags or registers required by Cond are available at the
506 /// @param MBB Block where select instruction should be inserted.
507 /// @param I Insertion point.
508 /// @param DL Source location for debugging.
509 /// @param DstReg Virtual register to be defined by select instruction.
510 /// @param Cond Condition as computed by AnalyzeBranch.
511 /// @param TrueReg Virtual register to copy when Cond is true.
512 /// @param FalseReg Virtual register to copy when Cons is false.
513 virtual void insertSelect(MachineBasicBlock &MBB,
514 MachineBasicBlock::iterator I, DebugLoc DL,
516 const SmallVectorImpl<MachineOperand> &Cond,
517 unsigned TrueReg, unsigned FalseReg) const {
518 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
521 /// analyzeSelect - Analyze the given select instruction, returning true if
522 /// it cannot be understood. It is assumed that MI->isSelect() is true.
524 /// When successful, return the controlling condition and the operands that
525 /// determine the true and false result values.
527 /// Result = SELECT Cond, TrueOp, FalseOp
529 /// Some targets can optimize select instructions, for example by predicating
530 /// the instruction defining one of the operands. Such targets should set
533 /// @param MI Select instruction to analyze.
534 /// @param Cond Condition controlling the select.
535 /// @param TrueOp Operand number of the value selected when Cond is true.
536 /// @param FalseOp Operand number of the value selected when Cond is false.
537 /// @param Optimizable Returned as true if MI is optimizable.
538 /// @returns False on success.
539 virtual bool analyzeSelect(const MachineInstr *MI,
540 SmallVectorImpl<MachineOperand> &Cond,
541 unsigned &TrueOp, unsigned &FalseOp,
542 bool &Optimizable) const {
543 assert(MI && MI->getDesc().isSelect() && "MI must be a select instruction");
547 /// optimizeSelect - Given a select instruction that was understood by
548 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
549 /// merging it with one of its operands. Returns NULL on failure.
551 /// When successful, returns the new select instruction. The client is
552 /// responsible for deleting MI.
554 /// If both sides of the select can be optimized, PreferFalse is used to pick
557 /// @param MI Optimizable select instruction.
558 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
559 /// @returns Optimized instruction or NULL.
560 virtual MachineInstr *optimizeSelect(MachineInstr *MI,
561 bool PreferFalse = false) const {
562 // This function must be implemented if Optimizable is ever set.
563 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
566 /// copyPhysReg - Emit instructions to copy a pair of physical registers.
568 /// This function should support copies within any legal register class as
569 /// well as any cross-class copies created during instruction selection.
571 /// The source and destination registers may overlap, which may require a
572 /// careful implementation when multiple copy instructions are required for
573 /// large registers. See for example the ARM target.
574 virtual void copyPhysReg(MachineBasicBlock &MBB,
575 MachineBasicBlock::iterator MI, DebugLoc DL,
576 unsigned DestReg, unsigned SrcReg,
577 bool KillSrc) const {
578 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
581 /// storeRegToStackSlot - Store the specified register of the given register
582 /// class to the specified stack frame index. The store instruction is to be
583 /// added to the given machine basic block before the specified machine
584 /// instruction. If isKill is true, the register operand is the last use and
585 /// must be marked kill.
586 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
587 MachineBasicBlock::iterator MI,
588 unsigned SrcReg, bool isKill, int FrameIndex,
589 const TargetRegisterClass *RC,
590 const TargetRegisterInfo *TRI) const {
591 llvm_unreachable("Target didn't implement "
592 "TargetInstrInfo::storeRegToStackSlot!");
595 /// loadRegFromStackSlot - Load the specified register of the given register
596 /// class from the specified stack frame index. The load instruction is to be
597 /// added to the given machine basic block before the specified machine
599 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
600 MachineBasicBlock::iterator MI,
601 unsigned DestReg, int FrameIndex,
602 const TargetRegisterClass *RC,
603 const TargetRegisterInfo *TRI) const {
604 llvm_unreachable("Target didn't implement "
605 "TargetInstrInfo::loadRegFromStackSlot!");
608 /// expandPostRAPseudo - This function is called for all pseudo instructions
609 /// that remain after register allocation. Many pseudo instructions are
610 /// created to help register allocation. This is the place to convert them
611 /// into real instructions. The target can edit MI in place, or it can insert
612 /// new instructions and erase MI. The function should return true if
613 /// anything was changed.
614 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
618 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
619 /// slot into the specified machine instruction for the specified operand(s).
620 /// If this is possible, a new instruction is returned with the specified
621 /// operand folded, otherwise NULL is returned.
622 /// The new instruction is inserted before MI, and the client is responsible
623 /// for removing the old instruction.
624 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
625 const SmallVectorImpl<unsigned> &Ops,
626 int FrameIndex) const;
628 /// foldMemoryOperand - Same as the previous version except it allows folding
629 /// of any load and store from / to any address, not just from a specific
631 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
632 const SmallVectorImpl<unsigned> &Ops,
633 MachineInstr* LoadMI) const;
635 /// hasPattern - return true when there is potentially a faster code sequence
636 /// for an instruction chain ending in \p Root. All potential pattern are
637 /// returned in the \p Pattern vector. Pattern should be sorted in priority
638 /// order since the pattern evaluator stops checking as soon as it finds a
640 /// \param Root - Instruction that could be combined with one of its operands
641 /// \param Pattern - Vector of possible combination pattern
643 virtual bool hasPattern(
645 SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Pattern) const {
649 /// genAlternativeCodeSequence - when hasPattern() finds a pattern this
650 /// function generates the instructions that could replace the original code
651 /// sequence. The client has to decide whether the actual replacementment is
652 /// beneficial or not.
653 /// \param Root - Instruction that could be combined with one of its operands
654 /// \param P - Combination pattern for Root
655 /// \param InsInstrs - Vector of new instructions that implement P
656 /// \param DelInstrs - Old instructions, including Root, that could be replaced
658 /// \param InstrIdxForVirtReg - map of virtual register to instruction in
659 /// InsInstr that defines it
660 virtual void genAlternativeCodeSequence(
661 MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P,
662 SmallVectorImpl<MachineInstr *> &InsInstrs,
663 SmallVectorImpl<MachineInstr *> &DelInstrs,
664 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
668 /// useMachineCombiner - return true when a target supports MachineCombiner
669 virtual bool useMachineCombiner(void) const { return false; }
672 /// foldMemoryOperandImpl - Target-dependent implementation for
673 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
674 /// take care of adding a MachineMemOperand to the newly created instruction.
675 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
677 const SmallVectorImpl<unsigned> &Ops,
678 int FrameIndex) const {
682 /// foldMemoryOperandImpl - Target-dependent implementation for
683 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
684 /// take care of adding a MachineMemOperand to the newly created instruction.
685 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
687 const SmallVectorImpl<unsigned> &Ops,
688 MachineInstr* LoadMI) const {
692 /// \brief Target-dependent implementation of getRegSequenceInputs.
694 /// \returns true if it is possible to build the equivalent
695 /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
697 /// \pre MI.isRegSequenceLike().
699 /// \see TargetInstrInfo::getRegSequenceInputs.
700 virtual bool getRegSequenceLikeInputs(
701 const MachineInstr &MI, unsigned DefIdx,
702 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
706 /// \brief Target-dependent implementation of getExtractSubregInputs.
708 /// \returns true if it is possible to build the equivalent
709 /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
711 /// \pre MI.isExtractSubregLike().
713 /// \see TargetInstrInfo::getExtractSubregInputs.
714 virtual bool getExtractSubregLikeInputs(
715 const MachineInstr &MI, unsigned DefIdx,
716 RegSubRegPairAndIdx &InputReg) const {
721 /// canFoldMemoryOperand - Returns true for the specified load / store if
722 /// folding is possible.
724 bool canFoldMemoryOperand(const MachineInstr *MI,
725 const SmallVectorImpl<unsigned> &Ops) const;
727 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
728 /// a store or a load and a store into two or more instruction. If this is
729 /// possible, returns true as well as the new instructions by reference.
730 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
731 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
732 SmallVectorImpl<MachineInstr*> &NewMIs) const{
736 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
737 SmallVectorImpl<SDNode*> &NewNodes) const {
741 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
742 /// instruction after load / store are unfolded from an instruction of the
743 /// specified opcode. It returns zero if the specified unfolding is not
744 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
745 /// index of the operand which will hold the register holding the loaded
747 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
748 bool UnfoldLoad, bool UnfoldStore,
749 unsigned *LoadRegIndex = nullptr) const {
753 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
754 /// to determine if two loads are loading from the same base address. It
755 /// should only return true if the base pointers are the same and the
756 /// only differences between the two addresses are the offset. It also returns
757 /// the offsets by reference.
758 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
759 int64_t &Offset1, int64_t &Offset2) const {
763 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
764 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
765 /// be scheduled togther. On some targets if two loads are loading from
766 /// addresses in the same cache line, it's better if they are scheduled
767 /// together. This function takes two integers that represent the load offsets
768 /// from the common base address. It returns true if it decides it's desirable
769 /// to schedule the two loads together. "NumLoads" is the number of loads that
770 /// have already been scheduled after Load1.
771 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
772 int64_t Offset1, int64_t Offset2,
773 unsigned NumLoads) const {
777 /// \brief Get the base register and byte offset of a load/store instr.
778 virtual bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
779 unsigned &BaseReg, unsigned &Offset,
780 const TargetRegisterInfo *TRI) const {
784 virtual bool enableClusterLoads() const { return false; }
786 virtual bool shouldClusterLoads(MachineInstr *FirstLdSt,
787 MachineInstr *SecondLdSt,
788 unsigned NumLoads) const {
792 /// \brief Can this target fuse the given instructions if they are scheduled
794 virtual bool shouldScheduleAdjacent(MachineInstr* First,
795 MachineInstr *Second) const {
799 /// ReverseBranchCondition - Reverses the branch condition of the specified
800 /// condition list, returning false on success and true if it cannot be
803 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
807 /// insertNoop - Insert a noop into the instruction stream at the specified
809 virtual void insertNoop(MachineBasicBlock &MBB,
810 MachineBasicBlock::iterator MI) const;
813 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
814 virtual void getNoopForMachoTarget(MCInst &NopInst) const {
815 // Default to just using 'nop' string.
819 /// isPredicated - Returns true if the instruction is already predicated.
821 virtual bool isPredicated(const MachineInstr *MI) const {
825 /// isUnpredicatedTerminator - Returns true if the instruction is a
826 /// terminator instruction that has not been predicated.
827 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
829 /// PredicateInstruction - Convert the instruction into a predicated
830 /// instruction. It returns true if the operation was successful.
832 bool PredicateInstruction(MachineInstr *MI,
833 const SmallVectorImpl<MachineOperand> &Pred) const;
835 /// SubsumesPredicate - Returns true if the first specified predicate
836 /// subsumes the second, e.g. GE subsumes GT.
838 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
839 const SmallVectorImpl<MachineOperand> &Pred2) const {
843 /// DefinesPredicate - If the specified instruction defines any predicate
844 /// or condition code register(s) used for predication, returns true as well
845 /// as the definition predicate(s) by reference.
846 virtual bool DefinesPredicate(MachineInstr *MI,
847 std::vector<MachineOperand> &Pred) const {
851 /// isPredicable - Return true if the specified instruction can be predicated.
852 /// By default, this returns true for every instruction with a
853 /// PredicateOperand.
854 virtual bool isPredicable(MachineInstr *MI) const {
855 return MI->getDesc().isPredicable();
858 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
859 /// instruction that defines the specified register class.
860 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
864 /// isSchedulingBoundary - Test if the given instruction should be
865 /// considered a scheduling boundary. This primarily includes labels and
867 virtual bool isSchedulingBoundary(const MachineInstr *MI,
868 const MachineBasicBlock *MBB,
869 const MachineFunction &MF) const;
871 /// Measure the specified inline asm to determine an approximation of its
873 virtual unsigned getInlineAsmLength(const char *Str,
874 const MCAsmInfo &MAI) const;
876 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to
877 /// use for this target when scheduling the machine instructions before
878 /// register allocation.
879 virtual ScheduleHazardRecognizer*
880 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
881 const ScheduleDAG *DAG) const;
883 /// CreateTargetMIHazardRecognizer - Allocate and return a hazard recognizer
884 /// to use for this target when scheduling the machine instructions before
885 /// register allocation.
886 virtual ScheduleHazardRecognizer*
887 CreateTargetMIHazardRecognizer(const InstrItineraryData*,
888 const ScheduleDAG *DAG) const;
890 /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard
891 /// recognizer to use for this target when scheduling the machine instructions
892 /// after register allocation.
893 virtual ScheduleHazardRecognizer*
894 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
895 const ScheduleDAG *DAG) const;
897 /// Provide a global flag for disabling the PreRA hazard recognizer that
898 /// targets may choose to honor.
899 bool usePreRAHazardRecognizer() const;
901 /// analyzeCompare - For a comparison instruction, return the source registers
902 /// in SrcReg and SrcReg2 if having two register operands, and the value it
903 /// compares against in CmpValue. Return true if the comparison instruction
905 virtual bool analyzeCompare(const MachineInstr *MI,
906 unsigned &SrcReg, unsigned &SrcReg2,
907 int &Mask, int &Value) const {
911 /// optimizeCompareInstr - See if the comparison instruction can be converted
912 /// into something more efficient. E.g., on ARM most instructions can set the
913 /// flags register, obviating the need for a separate CMP.
914 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr,
915 unsigned SrcReg, unsigned SrcReg2,
917 const MachineRegisterInfo *MRI) const {
921 /// optimizeLoadInstr - Try to remove the load by folding it to a register
922 /// operand at the use. We fold the load instructions if and only if the
923 /// def and use are in the same BB. We only look at one load and see
924 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
925 /// defined by the load we are trying to fold. DefMI returns the machine
926 /// instruction that defines FoldAsLoadDefReg, and the function returns
927 /// the machine instruction generated due to folding.
928 virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,
929 const MachineRegisterInfo *MRI,
930 unsigned &FoldAsLoadDefReg,
931 MachineInstr *&DefMI) const {
935 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
936 /// instruction, try to fold the immediate into the use instruction.
937 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
938 /// then the caller may assume that DefMI has been erased from its parent
939 /// block. The caller may assume that it will not be erased by this
940 /// function otherwise.
941 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
942 unsigned Reg, MachineRegisterInfo *MRI) const {
946 /// getNumMicroOps - Return the number of u-operations the given machine
947 /// instruction will be decoded to on the target cpu. The itinerary's
948 /// IssueWidth is the number of microops that can be dispatched each
949 /// cycle. An instruction with zero microops takes no dispatch resources.
950 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
951 const MachineInstr *MI) const;
953 /// isZeroCost - Return true for pseudo instructions that don't consume any
954 /// machine resources in their current form. These are common cases that the
955 /// scheduler should consider free, rather than conservatively handling them
956 /// as instructions with no itinerary.
957 bool isZeroCost(unsigned Opcode) const {
958 return Opcode <= TargetOpcode::COPY;
961 virtual int getOperandLatency(const InstrItineraryData *ItinData,
962 SDNode *DefNode, unsigned DefIdx,
963 SDNode *UseNode, unsigned UseIdx) const;
965 /// getOperandLatency - Compute and return the use operand latency of a given
966 /// pair of def and use.
967 /// In most cases, the static scheduling itinerary was enough to determine the
968 /// operand latency. But it may not be possible for instructions with variable
969 /// number of defs / uses.
971 /// This is a raw interface to the itinerary that may be directly overriden by
972 /// a target. Use computeOperandLatency to get the best estimate of latency.
973 virtual int getOperandLatency(const InstrItineraryData *ItinData,
974 const MachineInstr *DefMI, unsigned DefIdx,
975 const MachineInstr *UseMI,
976 unsigned UseIdx) const;
978 /// computeOperandLatency - Compute and return the latency of the given data
979 /// dependent def and use when the operand indices are already known.
980 unsigned computeOperandLatency(const InstrItineraryData *ItinData,
981 const MachineInstr *DefMI, unsigned DefIdx,
982 const MachineInstr *UseMI, unsigned UseIdx)
985 /// getInstrLatency - Compute the instruction latency of a given instruction.
986 /// If the instruction has higher cost when predicated, it's returned via
988 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
989 const MachineInstr *MI,
990 unsigned *PredCost = nullptr) const;
992 virtual unsigned getPredicationCost(const MachineInstr *MI) const;
994 virtual int getInstrLatency(const InstrItineraryData *ItinData,
997 /// Return the default expected latency for a def based on it's opcode.
998 unsigned defaultDefLatency(const MCSchedModel *SchedModel,
999 const MachineInstr *DefMI) const;
1001 int computeDefOperandLatency(const InstrItineraryData *ItinData,
1002 const MachineInstr *DefMI) const;
1004 /// isHighLatencyDef - Return true if this opcode has high latency to its
1006 virtual bool isHighLatencyDef(int opc) const { return false; }
1008 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg'
1009 /// and an use in the current loop, return true if the target considered
1010 /// it 'high'. This is used by optimization passes such as machine LICM to
1011 /// determine whether it makes sense to hoist an instruction out even in
1012 /// high register pressure situation.
1014 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
1015 const MachineRegisterInfo *MRI,
1016 const MachineInstr *DefMI, unsigned DefIdx,
1017 const MachineInstr *UseMI, unsigned UseIdx) const {
1021 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true
1022 /// if the target considered it 'low'.
1024 bool hasLowDefLatency(const InstrItineraryData *ItinData,
1025 const MachineInstr *DefMI, unsigned DefIdx) const;
1027 /// verifyInstruction - Perform target specific instruction verification.
1029 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const {
1033 /// getExecutionDomain - Return the current execution domain and bit mask of
1034 /// possible domains for instruction.
1036 /// Some micro-architectures have multiple execution domains, and multiple
1037 /// opcodes that perform the same operation in different domains. For
1038 /// example, the x86 architecture provides the por, orps, and orpd
1039 /// instructions that all do the same thing. There is a latency penalty if a
1040 /// register is written in one domain and read in another.
1042 /// This function returns a pair (domain, mask) containing the execution
1043 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1044 /// function can be used to change the opcode to one of the domains in the
1045 /// bit mask. Instructions whose execution domain can't be changed should
1046 /// return a 0 mask.
1048 /// The execution domain numbers don't have any special meaning except domain
1049 /// 0 is used for instructions that are not associated with any interesting
1050 /// execution domain.
1052 virtual std::pair<uint16_t, uint16_t>
1053 getExecutionDomain(const MachineInstr *MI) const {
1054 return std::make_pair(0, 0);
1057 /// setExecutionDomain - Change the opcode of MI to execute in Domain.
1059 /// The bit (1 << Domain) must be set in the mask returned from
1060 /// getExecutionDomain(MI).
1062 virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {}
1065 /// getPartialRegUpdateClearance - Returns the preferred minimum clearance
1066 /// before an instruction with an unwanted partial register update.
1068 /// Some instructions only write part of a register, and implicitly need to
1069 /// read the other parts of the register. This may cause unwanted stalls
1070 /// preventing otherwise unrelated instructions from executing in parallel in
1071 /// an out-of-order CPU.
1073 /// For example, the x86 instruction cvtsi2ss writes its result to bits
1074 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1075 /// the instruction needs to wait for the old value of the register to become
1078 /// addps %xmm1, %xmm0
1079 /// movaps %xmm0, (%rax)
1080 /// cvtsi2ss %rbx, %xmm0
1082 /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1083 /// instruction before it can issue, even though the high bits of %xmm0
1084 /// probably aren't needed.
1086 /// This hook returns the preferred clearance before MI, measured in
1087 /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1088 /// instructions before MI. It should only return a positive value for
1089 /// unwanted dependencies. If the old bits of the defined register have
1090 /// useful values, or if MI is determined to otherwise read the dependency,
1091 /// the hook should return 0.
1093 /// The unwanted dependency may be handled by:
1095 /// 1. Allocating the same register for an MI def and use. That makes the
1096 /// unwanted dependency identical to a required dependency.
1098 /// 2. Allocating a register for the def that has no defs in the previous N
1101 /// 3. Calling breakPartialRegDependency() with the same arguments. This
1102 /// allows the target to insert a dependency breaking instruction.
1105 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
1106 const TargetRegisterInfo *TRI) const {
1107 // The default implementation returns 0 for no partial register dependency.
1111 /// \brief Return the minimum clearance before an instruction that reads an
1112 /// unused register.
1114 /// For example, AVX instructions may copy part of an register operand into
1115 /// the unused high bits of the destination register.
1117 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
1119 /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1120 /// false dependence on any previous write to %xmm0.
1122 /// This hook works similarly to getPartialRegUpdateClearance, except that it
1123 /// does not take an operand index. Instead sets \p OpNum to the index of the
1124 /// unused register.
1125 virtual unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
1126 const TargetRegisterInfo *TRI) const {
1127 // The default implementation returns 0 for no undef register dependency.
1131 /// breakPartialRegDependency - Insert a dependency-breaking instruction
1132 /// before MI to eliminate an unwanted dependency on OpNum.
1134 /// If it wasn't possible to avoid a def in the last N instructions before MI
1135 /// (see getPartialRegUpdateClearance), this hook will be called to break the
1136 /// unwanted dependency.
1138 /// On x86, an xorps instruction can be used as a dependency breaker:
1140 /// addps %xmm1, %xmm0
1141 /// movaps %xmm0, (%rax)
1142 /// xorps %xmm0, %xmm0
1143 /// cvtsi2ss %rbx, %xmm0
1145 /// An <imp-kill> operand should be added to MI if an instruction was
1146 /// inserted. This ties the instructions together in the post-ra scheduler.
1149 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
1150 const TargetRegisterInfo *TRI) const {}
1152 /// Create machine specific model for scheduling.
1153 virtual DFAPacketizer*
1154 CreateTargetScheduleState(const TargetMachine*, const ScheduleDAG*) const {
1159 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
1162 } // End llvm namespace