1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
22 class CalleeSavedInfo;
25 class MachineMemOperand;
28 class TargetRegisterClass;
29 class TargetRegisterInfo;
31 template<class T> class SmallVectorImpl;
34 //---------------------------------------------------------------------------
36 /// TargetInstrInfo - Interface to description of machine instruction set
38 class TargetInstrInfo {
39 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
40 unsigned NumOpcodes; // Number of entries in the desc array
42 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
43 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
45 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
46 virtual ~TargetInstrInfo();
48 unsigned getNumOpcodes() const { return NumOpcodes; }
50 /// get - Return the machine instruction descriptor that corresponds to the
51 /// specified instruction opcode.
53 const TargetInstrDesc &get(unsigned Opcode) const {
54 assert(Opcode < NumOpcodes && "Invalid opcode!");
55 return Descriptors[Opcode];
58 /// isTriviallyReMaterializable - Return true if the instruction is trivially
59 /// rematerializable, meaning it has no side effects and requires no operands
60 /// that aren't always available.
61 bool isTriviallyReMaterializable(const MachineInstr *MI,
62 AliasAnalysis *AA = 0) const {
63 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
64 (MI->getDesc().isRematerializable() &&
65 (isReallyTriviallyReMaterializable(MI, AA) ||
66 isReallyTriviallyReMaterializableGeneric(MI, AA)));
70 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
71 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
72 /// specify whether the instruction is actually trivially rematerializable,
73 /// taking into consideration its operands. This predicate must return false
74 /// if the instruction has any side effects other than producing a value, or
75 /// if it requres any address registers that are not always available.
76 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
77 AliasAnalysis *AA) const {
82 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
83 /// for which the M_REMATERIALIZABLE flag is set and the target hook
84 /// isReallyTriviallyReMaterializable returns false, this function does
85 /// target-independent tests to determine if the instruction is really
86 /// trivially rematerializable.
87 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
88 AliasAnalysis *AA) const;
91 /// isMoveInstr - Return true if the instruction is a register to register
92 /// move and return the source and dest operands and their sub-register
93 /// indices by reference.
94 virtual bool isMoveInstr(const MachineInstr& MI,
95 unsigned& SrcReg, unsigned& DstReg,
96 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
100 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
101 /// extension instruction. That is, it's like a copy where it's legal for the
102 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
103 /// true, then it's expected the pre-extension value is available as a subreg
104 /// of the result register. This also returns the sub-register index in
106 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
107 unsigned &SrcReg, unsigned &DstReg,
108 unsigned &SubIdx) const {
112 /// isIdentityCopy - Return true if the instruction is a copy (or
113 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and
114 /// destination registers are the same.
115 bool isIdentityCopy(const MachineInstr &MI) const {
116 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
117 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
121 if (MI.getOpcode() == TargetOpcode::EXTRACT_SUBREG &&
122 MI.getOperand(0).getReg() == MI.getOperand(1).getReg())
125 if ((MI.getOpcode() == TargetOpcode::INSERT_SUBREG ||
126 MI.getOpcode() == TargetOpcode::SUBREG_TO_REG) &&
127 MI.getOperand(0).getReg() == MI.getOperand(2).getReg())
132 /// isLoadFromStackSlot - If the specified machine instruction is a direct
133 /// load from a stack slot, return the virtual or physical register number of
134 /// the destination along with the FrameIndex of the loaded stack slot. If
135 /// not, return 0. This predicate must return 0 if the instruction has
136 /// any side effects other than loading from the stack slot.
137 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
138 int &FrameIndex) const {
142 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
143 /// stack locations as well. This uses a heuristic so it isn't
144 /// reliable for correctness.
145 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
146 int &FrameIndex) const {
150 /// hasLoadFromStackSlot - If the specified machine instruction has
151 /// a load from a stack slot, return true along with the FrameIndex
152 /// of the loaded stack slot and the machine mem operand containing
153 /// the reference. If not, return false. Unlike
154 /// isLoadFromStackSlot, this returns true for any instructions that
155 /// loads from the stack. This is just a hint, as some cases may be
157 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
158 const MachineMemOperand *&MMO,
159 int &FrameIndex) const {
163 /// isStoreToStackSlot - If the specified machine instruction is a direct
164 /// store to a stack slot, return the virtual or physical register number of
165 /// the source reg along with the FrameIndex of the loaded stack slot. If
166 /// not, return 0. This predicate must return 0 if the instruction has
167 /// any side effects other than storing to the stack slot.
168 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
169 int &FrameIndex) const {
173 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
174 /// stack locations as well. This uses a heuristic so it isn't
175 /// reliable for correctness.
176 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
177 int &FrameIndex) const {
181 /// hasStoreToStackSlot - If the specified machine instruction has a
182 /// store to a stack slot, return true along with the FrameIndex of
183 /// the loaded stack slot and the machine mem operand containing the
184 /// reference. If not, return false. Unlike isStoreToStackSlot,
185 /// this returns true for any instructions that loads from the
186 /// stack. This is just a hint, as some cases may be missed.
187 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
188 const MachineMemOperand *&MMO,
189 int &FrameIndex) const {
193 /// reMaterialize - Re-issue the specified 'original' instruction at the
194 /// specific location targeting a new destination register.
195 virtual void reMaterialize(MachineBasicBlock &MBB,
196 MachineBasicBlock::iterator MI,
197 unsigned DestReg, unsigned SubIdx,
198 const MachineInstr *Orig,
199 const TargetRegisterInfo *TRI) const = 0;
201 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
202 /// MachineFunction::CloneMachineInstr(), but the target may update operands
203 /// that are required to be unique.
205 /// The instruction must be duplicable as indicated by isNotDuplicable().
206 virtual MachineInstr *duplicate(MachineInstr *Orig,
207 MachineFunction &MF) const = 0;
209 /// convertToThreeAddress - This method must be implemented by targets that
210 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
211 /// may be able to convert a two-address instruction into one or more true
212 /// three-address instructions on demand. This allows the X86 target (for
213 /// example) to convert ADD and SHL instructions into LEA instructions if they
214 /// would require register copies due to two-addressness.
216 /// This method returns a null pointer if the transformation cannot be
217 /// performed, otherwise it returns the last new instruction.
219 virtual MachineInstr *
220 convertToThreeAddress(MachineFunction::iterator &MFI,
221 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
225 /// commuteInstruction - If a target has any instructions that are commutable,
226 /// but require converting to a different instruction or making non-trivial
227 /// changes to commute them, this method can overloaded to do this. The
228 /// default implementation of this method simply swaps the first two operands
229 /// of MI and returns it.
231 /// If a target wants to make more aggressive changes, they can construct and
232 /// return a new machine instruction. If an instruction cannot commute, it
233 /// can also return null.
235 /// If NewMI is true, then a new machine instruction must be created.
237 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
238 bool NewMI = false) const = 0;
240 /// findCommutedOpIndices - If specified MI is commutable, return the two
241 /// operand indices that would swap value. Return true if the instruction
242 /// is not in a form which this routine understands.
243 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
244 unsigned &SrcOpIdx2) const = 0;
246 /// produceSameValue - Return true if two machine instructions would produce
247 /// identical values. By default, this is only true when the two instructions
248 /// are deemed identical except for defs.
249 virtual bool produceSameValue(const MachineInstr *MI0,
250 const MachineInstr *MI1) const = 0;
252 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
253 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
254 /// implemented for a target). Upon success, this returns false and returns
255 /// with the following information in various cases:
257 /// 1. If this block ends with no branches (it just falls through to its succ)
258 /// just return false, leaving TBB/FBB null.
259 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
260 /// the destination block.
261 /// 3. If this block ends with a conditional branch and it falls through to a
262 /// successor block, it sets TBB to be the branch destination block and a
263 /// list of operands that evaluate the condition. These operands can be
264 /// passed to other TargetInstrInfo methods to create new branches.
265 /// 4. If this block ends with a conditional branch followed by an
266 /// unconditional branch, it returns the 'true' destination in TBB, the
267 /// 'false' destination in FBB, and a list of operands that evaluate the
268 /// condition. These operands can be passed to other TargetInstrInfo
269 /// methods to create new branches.
271 /// Note that RemoveBranch and InsertBranch must be implemented to support
272 /// cases where this method returns success.
274 /// If AllowModify is true, then this routine is allowed to modify the basic
275 /// block (e.g. delete instructions after the unconditional branch).
277 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
278 MachineBasicBlock *&FBB,
279 SmallVectorImpl<MachineOperand> &Cond,
280 bool AllowModify = false) const {
284 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
285 /// This is only invoked in cases where AnalyzeBranch returns success. It
286 /// returns the number of instructions that were removed.
287 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
288 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
292 /// InsertBranch - Insert branch code into the end of the specified
293 /// MachineBasicBlock. The operands to this method are the same as those
294 /// returned by AnalyzeBranch. This is only invoked in cases where
295 /// AnalyzeBranch returns success. It returns the number of instructions
298 /// It is also invoked by tail merging to add unconditional branches in
299 /// cases where AnalyzeBranch doesn't apply because there was no original
300 /// branch to analyze. At least this much must be implemented, else tail
301 /// merging needs to be disabled.
302 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
303 MachineBasicBlock *FBB,
304 const SmallVectorImpl<MachineOperand> &Cond) const {
305 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
309 /// copyRegToReg - Emit instructions to copy between a pair of registers. It
310 /// returns false if the target does not how to copy between the specified
312 virtual bool copyRegToReg(MachineBasicBlock &MBB,
313 MachineBasicBlock::iterator MI,
314 unsigned DestReg, unsigned SrcReg,
315 const TargetRegisterClass *DestRC,
316 const TargetRegisterClass *SrcRC) const {
317 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
321 /// storeRegToStackSlot - Store the specified register of the given register
322 /// class to the specified stack frame index. The store instruction is to be
323 /// added to the given machine basic block before the specified machine
324 /// instruction. If isKill is true, the register operand is the last use and
325 /// must be marked kill.
326 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
327 MachineBasicBlock::iterator MI,
328 unsigned SrcReg, bool isKill, int FrameIndex,
329 const TargetRegisterClass *RC) const {
330 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
333 /// loadRegFromStackSlot - Load the specified register of the given register
334 /// class from the specified stack frame index. The load instruction is to be
335 /// added to the given machine basic block before the specified machine
337 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
338 MachineBasicBlock::iterator MI,
339 unsigned DestReg, int FrameIndex,
340 const TargetRegisterClass *RC) const {
341 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
344 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
345 /// saved registers and returns true if it isn't possible / profitable to do
346 /// so by issuing a series of store instructions via
347 /// storeRegToStackSlot(). Returns false otherwise.
348 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
349 MachineBasicBlock::iterator MI,
350 const std::vector<CalleeSavedInfo> &CSI) const {
354 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
355 /// saved registers and returns true if it isn't possible / profitable to do
356 /// so by issuing a series of load instructions via loadRegToStackSlot().
357 /// Returns false otherwise.
358 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
359 MachineBasicBlock::iterator MI,
360 const std::vector<CalleeSavedInfo> &CSI) const {
364 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
365 /// slot into the specified machine instruction for the specified operand(s).
366 /// If this is possible, a new instruction is returned with the specified
367 /// operand folded, otherwise NULL is returned. The client is responsible for
368 /// removing the old instruction and adding the new one in the instruction
370 MachineInstr* foldMemoryOperand(MachineFunction &MF,
372 const SmallVectorImpl<unsigned> &Ops,
373 int FrameIndex) const;
375 /// foldMemoryOperand - Same as the previous version except it allows folding
376 /// of any load and store from / to any address, not just from a specific
378 MachineInstr* foldMemoryOperand(MachineFunction &MF,
380 const SmallVectorImpl<unsigned> &Ops,
381 MachineInstr* LoadMI) const;
384 /// foldMemoryOperandImpl - Target-dependent implementation for
385 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
386 /// take care of adding a MachineMemOperand to the newly created instruction.
387 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
389 const SmallVectorImpl<unsigned> &Ops,
390 int FrameIndex) const {
394 /// foldMemoryOperandImpl - Target-dependent implementation for
395 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
396 /// take care of adding a MachineMemOperand to the newly created instruction.
397 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
399 const SmallVectorImpl<unsigned> &Ops,
400 MachineInstr* LoadMI) const {
405 /// canFoldMemoryOperand - Returns true for the specified load / store if
406 /// folding is possible.
408 bool canFoldMemoryOperand(const MachineInstr *MI,
409 const SmallVectorImpl<unsigned> &Ops) const {
413 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
414 /// a store or a load and a store into two or more instruction. If this is
415 /// possible, returns true as well as the new instructions by reference.
416 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
417 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
418 SmallVectorImpl<MachineInstr*> &NewMIs) const{
422 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
423 SmallVectorImpl<SDNode*> &NewNodes) const {
427 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
428 /// instruction after load / store are unfolded from an instruction of the
429 /// specified opcode. It returns zero if the specified unfolding is not
430 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
431 /// index of the operand which will hold the register holding the loaded
433 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
434 bool UnfoldLoad, bool UnfoldStore,
435 unsigned *LoadRegIndex = 0) const {
439 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
440 /// to determine if two loads are loading from the same base address. It
441 /// should only return true if the base pointers are the same and the
442 /// only differences between the two addresses are the offset. It also returns
443 /// the offsets by reference.
444 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
445 int64_t &Offset1, int64_t &Offset2) const {
449 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
450 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
451 /// be scheduled togther. On some targets if two loads are loading from
452 /// addresses in the same cache line, it's better if they are scheduled
453 /// together. This function takes two integers that represent the load offsets
454 /// from the common base address. It returns true if it decides it's desirable
455 /// to schedule the two loads together. "NumLoads" is the number of loads that
456 /// have already been scheduled after Load1.
457 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
458 int64_t Offset1, int64_t Offset2,
459 unsigned NumLoads) const {
463 /// ReverseBranchCondition - Reverses the branch condition of the specified
464 /// condition list, returning false on success and true if it cannot be
467 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
471 /// insertNoop - Insert a noop into the instruction stream at the specified
473 virtual void insertNoop(MachineBasicBlock &MBB,
474 MachineBasicBlock::iterator MI) const;
476 /// isPredicated - Returns true if the instruction is already predicated.
478 virtual bool isPredicated(const MachineInstr *MI) const {
482 /// isUnpredicatedTerminator - Returns true if the instruction is a
483 /// terminator instruction that has not been predicated.
484 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
486 /// PredicateInstruction - Convert the instruction into a predicated
487 /// instruction. It returns true if the operation was successful.
489 bool PredicateInstruction(MachineInstr *MI,
490 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
492 /// SubsumesPredicate - Returns true if the first specified predicate
493 /// subsumes the second, e.g. GE subsumes GT.
495 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
496 const SmallVectorImpl<MachineOperand> &Pred2) const {
500 /// DefinesPredicate - If the specified instruction defines any predicate
501 /// or condition code register(s) used for predication, returns true as well
502 /// as the definition predicate(s) by reference.
503 virtual bool DefinesPredicate(MachineInstr *MI,
504 std::vector<MachineOperand> &Pred) const {
508 /// isPredicable - Return true if the specified instruction can be predicated.
509 /// By default, this returns true for every instruction with a
510 /// PredicateOperand.
511 virtual bool isPredicable(MachineInstr *MI) const {
512 return MI->getDesc().isPredicable();
515 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
516 /// instruction that defines the specified register class.
517 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
521 /// GetInstSize - Returns the size of the specified Instruction.
523 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
524 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
528 /// GetFunctionSizeInBytes - Returns the size of the specified
531 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
533 /// Measure the specified inline asm to determine an approximation of its
535 virtual unsigned getInlineAsmLength(const char *Str,
536 const MCAsmInfo &MAI) const;
539 /// TargetInstrInfoImpl - This is the default implementation of
540 /// TargetInstrInfo, which just provides a couple of default implementations
541 /// for various methods. This separated out because it is implemented in
542 /// libcodegen, not in libtarget.
543 class TargetInstrInfoImpl : public TargetInstrInfo {
545 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
546 : TargetInstrInfo(desc, NumOpcodes) {}
548 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
549 bool NewMI = false) const;
550 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
551 unsigned &SrcOpIdx2) const;
552 virtual bool PredicateInstruction(MachineInstr *MI,
553 const SmallVectorImpl<MachineOperand> &Pred) const;
554 virtual void reMaterialize(MachineBasicBlock &MBB,
555 MachineBasicBlock::iterator MI,
556 unsigned DestReg, unsigned SubReg,
557 const MachineInstr *Orig,
558 const TargetRegisterInfo *TRI) const;
559 virtual MachineInstr *duplicate(MachineInstr *Orig,
560 MachineFunction &MF) const;
561 virtual bool produceSameValue(const MachineInstr *MI0,
562 const MachineInstr *MI1) const;
563 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
566 } // End llvm namespace