1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // This file describes the target machine instructions to the code generator.
5 //===----------------------------------------------------------------------===//
7 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
8 #define LLVM_TARGET_TARGETINSTRINFO_H
10 #include "Support/DataTypes.h"
19 class MachineCodeForInstruction;
21 //---------------------------------------------------------------------------
22 // Data types used to define information about a single machine instruction
23 //---------------------------------------------------------------------------
25 typedef int MachineOpCode;
26 typedef unsigned InstrSchedClass;
28 const MachineOpCode INVALID_MACHINE_OPCODE = -1;
31 //---------------------------------------------------------------------------
32 // struct TargetInstrDescriptor:
33 // Predefined information about each machine instruction.
34 // Designed to initialized statically.
37 const unsigned M_NOP_FLAG = 1 << 0;
38 const unsigned M_BRANCH_FLAG = 1 << 1;
39 const unsigned M_CALL_FLAG = 1 << 2;
40 const unsigned M_RET_FLAG = 1 << 3;
41 const unsigned M_ARITH_FLAG = 1 << 4;
42 const unsigned M_CC_FLAG = 1 << 6;
43 const unsigned M_LOGICAL_FLAG = 1 << 6;
44 const unsigned M_INT_FLAG = 1 << 7;
45 const unsigned M_FLOAT_FLAG = 1 << 8;
46 const unsigned M_CONDL_FLAG = 1 << 9;
47 const unsigned M_LOAD_FLAG = 1 << 10;
48 const unsigned M_PREFETCH_FLAG = 1 << 11;
49 const unsigned M_STORE_FLAG = 1 << 12;
50 const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
51 const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction
52 // 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub
53 const unsigned M_2_ADDR_FLAG = 1 << 15;
55 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
56 // block? Typically this is things like return and branch instructions.
57 // Various passes use this to insert code into the bottom of a basic block, but
58 // before control flow occurs.
59 const unsigned M_TERMINATOR_FLAG = 1 << 16;
61 struct TargetInstrDescriptor {
62 const char * Name; // Assembly language mnemonic for the opcode.
63 int numOperands; // Number of args; -1 if variable #args
64 int resultPos; // Position of the result; -1 if no result
65 unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0.
66 bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
67 // smallest -ve value is -(maxImmedConst+1).
68 unsigned numDelaySlots; // Number of delay slots after instruction
69 unsigned latency; // Latency in machine cycles
70 InstrSchedClass schedClass; // enum identifying instr sched class
71 unsigned Flags; // flags identifying machine instr class
72 unsigned TSFlags; // Target Specific Flag values
73 const unsigned *ImplicitUses; // Registers implicitly read by this instr
74 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
78 //---------------------------------------------------------------------------
80 /// TargetInstrInfo - Interface to description of machine instructions
82 class TargetInstrInfo {
83 const TargetInstrDescriptor* desc; // raw array to allow static init'n
84 unsigned descSize; // number of entries in the desc array
85 unsigned numRealOpCodes; // number of non-dummy op codes
87 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
88 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
90 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned descSize,
91 unsigned numRealOpCodes);
92 virtual ~TargetInstrInfo();
94 // Invariant: All instruction sets use opcode #0 as the PHI instruction and
95 // opcode #1 as the noop instruction.
100 unsigned getNumRealOpCodes() const { return numRealOpCodes; }
101 unsigned getNumTotalOpCodes() const { return descSize; }
103 /// get - Return the machine instruction descriptor that corresponds to the
104 /// specified instruction opcode.
106 const TargetInstrDescriptor& get(MachineOpCode opCode) const {
107 assert(opCode >= 0 && opCode < (int)descSize);
111 /// print - Print out the specified machine instruction in the appropriate
112 /// target specific assembly language. If this method is not overridden, the
113 /// default implementation uses the crummy machine independant printer.
115 virtual void print(const MachineInstr *MI, std::ostream &O,
116 const TargetMachine &TM) const;
118 const char *getName(MachineOpCode opCode) const {
119 return get(opCode).Name;
122 int getNumOperands(MachineOpCode opCode) const {
123 return get(opCode).numOperands;
126 int getResultPos(MachineOpCode opCode) const {
127 return get(opCode).resultPos;
130 unsigned getNumDelaySlots(MachineOpCode opCode) const {
131 return get(opCode).numDelaySlots;
134 InstrSchedClass getSchedClass(MachineOpCode opCode) const {
135 return get(opCode).schedClass;
139 // Query instruction class flags according to the machine-independent
140 // flags listed above.
142 bool isNop(MachineOpCode opCode) const {
143 return get(opCode).Flags & M_NOP_FLAG;
145 bool isBranch(MachineOpCode opCode) const {
146 return get(opCode).Flags & M_BRANCH_FLAG;
148 bool isCall(MachineOpCode opCode) const {
149 return get(opCode).Flags & M_CALL_FLAG;
151 bool isReturn(MachineOpCode opCode) const {
152 return get(opCode).Flags & M_RET_FLAG;
154 bool isControlFlow(MachineOpCode opCode) const {
155 return get(opCode).Flags & M_BRANCH_FLAG
156 || get(opCode).Flags & M_CALL_FLAG
157 || get(opCode).Flags & M_RET_FLAG;
159 bool isArith(MachineOpCode opCode) const {
160 return get(opCode).Flags & M_ARITH_FLAG;
162 bool isCCInstr(MachineOpCode opCode) const {
163 return get(opCode).Flags & M_CC_FLAG;
165 bool isLogical(MachineOpCode opCode) const {
166 return get(opCode).Flags & M_LOGICAL_FLAG;
168 bool isIntInstr(MachineOpCode opCode) const {
169 return get(opCode).Flags & M_INT_FLAG;
171 bool isFloatInstr(MachineOpCode opCode) const {
172 return get(opCode).Flags & M_FLOAT_FLAG;
174 bool isConditional(MachineOpCode opCode) const {
175 return get(opCode).Flags & M_CONDL_FLAG;
177 bool isLoad(MachineOpCode opCode) const {
178 return get(opCode).Flags & M_LOAD_FLAG;
180 bool isPrefetch(MachineOpCode opCode) const {
181 return get(opCode).Flags & M_PREFETCH_FLAG;
183 bool isLoadOrPrefetch(MachineOpCode opCode) const {
184 return get(opCode).Flags & M_LOAD_FLAG
185 || get(opCode).Flags & M_PREFETCH_FLAG;
187 bool isStore(MachineOpCode opCode) const {
188 return get(opCode).Flags & M_STORE_FLAG;
190 bool isMemoryAccess(MachineOpCode opCode) const {
191 return get(opCode).Flags & M_LOAD_FLAG
192 || get(opCode).Flags & M_PREFETCH_FLAG
193 || get(opCode).Flags & M_STORE_FLAG;
195 bool isDummyPhiInstr(MachineOpCode opCode) const {
196 return get(opCode).Flags & M_DUMMY_PHI_FLAG;
198 bool isPseudoInstr(MachineOpCode opCode) const {
199 return get(opCode).Flags & M_PSEUDO_FLAG;
201 bool isTwoAddrInstr(MachineOpCode opCode) const {
202 return get(opCode).Flags & M_2_ADDR_FLAG;
204 bool isTerminatorInstr(unsigned Opcode) const {
205 return get(Opcode).Flags & M_TERMINATOR_FLAG;
208 // Check if an instruction can be issued before its operands are ready,
209 // or if a subsequent instruction that uses its result can be issued
210 // before the results are ready.
211 // Default to true since most instructions on many architectures allow this.
213 virtual bool hasOperandInterlock(MachineOpCode opCode) const {
217 virtual bool hasResultInterlock(MachineOpCode opCode) const {
222 // Latencies for individual instructions and instruction pairs
224 virtual int minLatency(MachineOpCode opCode) const {
225 return get(opCode).latency;
228 virtual int maxLatency(MachineOpCode opCode) const {
229 return get(opCode).latency;
233 // Which operand holds an immediate constant? Returns -1 if none
235 virtual int getImmedConstantPos(MachineOpCode opCode) const {
236 return -1; // immediate position is machine specific, so say -1 == "none"
239 // Check if the specified constant fits in the immediate field
240 // of this machine instruction
242 virtual bool constantFitsInImmedField(MachineOpCode opCode,
243 int64_t intValue) const;
245 // Return the largest +ve constant that can be held in the IMMMED field
246 // of this machine instruction.
247 // isSignExtended is set to true if the value is sign-extended before use
248 // (this is true for all immediate fields in SPARC instructions).
249 // Return 0 if the instruction has no IMMED field.
251 virtual uint64_t maxImmedConstant(MachineOpCode opCode,
252 bool &isSignExtended) const {
253 isSignExtended = get(opCode).immedIsSignExtended;
254 return get(opCode).maxImmedConst;
257 //-------------------------------------------------------------------------
258 // Queries about representation of LLVM quantities (e.g., constants)
259 //-------------------------------------------------------------------------
261 /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded
262 /// from memory into a register, i.e., cannot be set bitwise in register and
263 /// cannot use immediate fields of instructions. Note that this only makes
264 /// sense for primitive types.
266 virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const;
268 // Test if this constant may not fit in the immediate field of the
269 // machine instructions (probably) generated for this instruction.
271 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
272 const Instruction* I) const {
273 return true; // safe but very conservative
276 //-------------------------------------------------------------------------
277 // Code generation support for creating individual machine instructions
279 // WARNING: These methods are Sparc specific
281 //-------------------------------------------------------------------------
283 // Get certain common op codes for the current target. this and all the
284 // Create* methods below should be moved to a machine code generation class
286 virtual MachineOpCode getNOPOpCode() const { abort(); }
288 // Create an instruction sequence to put the constant `val' into
289 // the virtual register `dest'. `val' may be a Constant or a
290 // GlobalValue, viz., the constant address of a global variable or function.
291 // The generated instructions are returned in `mvec'.
292 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
293 // Symbolic constants or constants that must be accessed from memory
294 // are added to the constant pool via MachineFunction::get(F).
296 virtual void CreateCodeToLoadConst(const TargetMachine& target,
300 std::vector<MachineInstr*>& mvec,
301 MachineCodeForInstruction& mcfi) const {
305 // Create an instruction sequence to copy an integer value `val'
306 // to a floating point value `dest' by copying to memory and back.
307 // val must be an integral type. dest must be a Float or Double.
308 // The generated instructions are returned in `mvec'.
309 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
310 // Any stack space required is allocated via mcff.
312 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
316 std::vector<MachineInstr*>& mvec,
317 MachineCodeForInstruction& MI) const {
321 // Similarly, create an instruction sequence to copy an FP value
322 // `val' to an integer value `dest' by copying to memory and back.
323 // The generated instructions are returned in `mvec'.
324 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
325 // Any stack space required is allocated via mcff.
327 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
331 std::vector<MachineInstr*>& mvec,
332 MachineCodeForInstruction& MI) const {
336 // Create instruction(s) to copy src to dest, for arbitrary types
337 // The generated instructions are returned in `mvec'.
338 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
339 // Any stack space required is allocated via mcff.
341 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
345 std::vector<MachineInstr*>& mvec,
346 MachineCodeForInstruction& MI) const {
350 // Create instruction sequence to produce a sign-extended register value
351 // from an arbitrary sized value (sized in bits, not bytes).
352 // The generated instructions are appended to `mvec'.
353 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
354 // Any stack space required is allocated via mcff.
356 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
361 std::vector<MachineInstr*>& mvec,
362 MachineCodeForInstruction& MI) const {
366 // Create instruction sequence to produce a zero-extended register value
367 // from an arbitrary sized value (sized in bits, not bytes).
368 // The generated instructions are appended to `mvec'.
369 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
370 // Any stack space required is allocated via mcff.
372 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
376 unsigned srcSizeInBits,
377 std::vector<MachineInstr*>& mvec,
378 MachineCodeForInstruction& mcfi) const {