1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Support/DataTypes.h"
27 class MachineCodeForInstruction;
28 class TargetRegisterClass;
31 //---------------------------------------------------------------------------
32 // Data types used to define information about a single machine instruction
33 //---------------------------------------------------------------------------
35 typedef short MachineOpCode;
36 typedef unsigned InstrSchedClass;
38 //---------------------------------------------------------------------------
39 // struct TargetInstrDescriptor:
40 // Predefined information about each machine instruction.
41 // Designed to initialized statically.
44 const unsigned M_BRANCH_FLAG = 1 << 0;
45 const unsigned M_CALL_FLAG = 1 << 1;
46 const unsigned M_RET_FLAG = 1 << 2;
47 const unsigned M_BARRIER_FLAG = 1 << 3;
48 const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
49 const unsigned M_LOAD_FLAG = 1 << 5;
50 const unsigned M_STORE_FLAG = 1 << 6;
52 // M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
53 // changed into a 3-address instruction if the first two operands cannot be
54 // assigned to the same register. The target must implement the
55 // TargetInstrInfo::convertToThreeAddress method for this instruction.
56 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 7;
58 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
59 // Z), which produces the same result if Y and Z are exchanged.
60 const unsigned M_COMMUTABLE = 1 << 8;
62 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
63 // block? Typically this is things like return and branch instructions.
64 // Various passes use this to insert code into the bottom of a basic block, but
65 // before control flow occurs.
66 const unsigned M_TERMINATOR_FLAG = 1 << 9;
68 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
69 // insertion support when the DAG scheduler is inserting it into a machine basic
71 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10;
73 // M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
74 // operands in addition to the minimum number operands specified.
75 const unsigned M_VARIABLE_OPS = 1 << 11;
77 // M_PREDICABLE - Set if this instruction has a predicate operand that
78 // controls execution. It may be set to 'always'.
79 const unsigned M_PREDICABLE = 1 << 12;
81 // M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized
82 // at any time, e.g. constant generation, load from constant pool.
83 const unsigned M_REMATERIALIZIBLE = 1 << 13;
85 // M_CLOBBERS_PRED - Set if this instruction may clobbers the condition code
86 // register and / or registers that are used to predicate instructions.
87 const unsigned M_CLOBBERS_PRED = 1 << 14;
89 // Machine operand flags
90 // M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
91 // requires a callback to look up its register class.
92 const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
94 /// M_PREDICATE_OPERAND - Set if this is one of the operands that made up of the
95 /// predicate operand that controls an M_PREDICATED instruction.
96 const unsigned M_PREDICATE_OPERAND = 1 << 1;
99 // Operand constraints: only "tied_to" for now.
100 enum OperandConstraint {
101 TIED_TO = 0 // Must be allocated the same register as.
105 /// TargetOperandInfo - This holds information about one operand of a machine
106 /// instruction, indicating the register class for register operands, etc.
108 class TargetOperandInfo {
110 /// RegClass - This specifies the register class enumeration of the operand
111 /// if the operand is a register. If not, this contains 0.
112 unsigned short RegClass;
113 unsigned short Flags;
114 /// Lower 16 bits are used to specify which constraints are set. The higher 16
115 /// bits are used to specify the value of constraints (4 bits each).
116 unsigned int Constraints;
117 /// Currently no other information.
121 class TargetInstrDescriptor {
123 MachineOpCode Opcode; // The opcode.
124 unsigned short numOperands; // Num of args (may be more if variable_ops).
125 const char * Name; // Assembly language mnemonic for the opcode.
126 InstrSchedClass schedClass; // enum identifying instr sched class
127 unsigned Flags; // flags identifying machine instr class
128 unsigned TSFlags; // Target Specific Flag values
129 const unsigned *ImplicitUses; // Registers implicitly read by this instr
130 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
131 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
133 /// getOperandConstraint - Returns the value of the specific constraint if
134 /// it is set. Returns -1 if it is not set.
135 int getOperandConstraint(unsigned OpNum,
136 TOI::OperandConstraint Constraint) const {
137 assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) &&
138 "Invalid operand # of TargetInstrInfo");
139 if (OpNum < numOperands &&
140 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
141 unsigned Pos = 16 + Constraint * 4;
142 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
147 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
148 /// dest operand. Returns -1 if there isn't one.
149 int findTiedToSrcOperand(unsigned OpNum) const;
153 //---------------------------------------------------------------------------
155 /// TargetInstrInfo - Interface to description of machine instructions
157 class TargetInstrInfo {
158 const TargetInstrDescriptor* desc; // raw array to allow static init'n
159 unsigned NumOpcodes; // number of entries in the desc array
160 unsigned numRealOpCodes; // number of non-dummy op codes
162 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
163 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
165 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
166 virtual ~TargetInstrInfo();
168 // Invariant opcodes: All instruction sets have these as their low opcodes.
175 unsigned getNumOpcodes() const { return NumOpcodes; }
177 /// get - Return the machine instruction descriptor that corresponds to the
178 /// specified instruction opcode.
180 const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
181 assert((unsigned)Opcode < NumOpcodes);
185 const char *getName(MachineOpCode Opcode) const {
186 return get(Opcode).Name;
189 int getNumOperands(MachineOpCode Opcode) const {
190 return get(Opcode).numOperands;
193 InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
194 return get(Opcode).schedClass;
197 const unsigned *getImplicitUses(MachineOpCode Opcode) const {
198 return get(Opcode).ImplicitUses;
201 const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
202 return get(Opcode).ImplicitDefs;
207 // Query instruction class flags according to the machine-independent
208 // flags listed above.
210 bool isReturn(MachineOpCode Opcode) const {
211 return get(Opcode).Flags & M_RET_FLAG;
214 bool isPredicable(MachineOpCode Opcode) const {
215 return get(Opcode).Flags & M_PREDICABLE;
217 bool clobbersPredicate(MachineOpCode Opcode) const {
218 return get(Opcode).Flags & M_CLOBBERS_PRED;
220 bool isReMaterializable(MachineOpCode Opcode) const {
221 return get(Opcode).Flags & M_REMATERIALIZIBLE;
223 bool isCommutableInstr(MachineOpCode Opcode) const {
224 return get(Opcode).Flags & M_COMMUTABLE;
226 bool isTerminatorInstr(MachineOpCode Opcode) const {
227 return get(Opcode).Flags & M_TERMINATOR_FLAG;
230 bool isBranch(MachineOpCode Opcode) const {
231 return get(Opcode).Flags & M_BRANCH_FLAG;
234 /// isBarrier - Returns true if the specified instruction stops control flow
235 /// from executing the instruction immediately following it. Examples include
236 /// unconditional branches and return instructions.
237 bool isBarrier(MachineOpCode Opcode) const {
238 return get(Opcode).Flags & M_BARRIER_FLAG;
241 bool isCall(MachineOpCode Opcode) const {
242 return get(Opcode).Flags & M_CALL_FLAG;
244 bool isLoad(MachineOpCode Opcode) const {
245 return get(Opcode).Flags & M_LOAD_FLAG;
247 bool isStore(MachineOpCode Opcode) const {
248 return get(Opcode).Flags & M_STORE_FLAG;
251 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
252 /// which must be filled by the code generator.
253 bool hasDelaySlot(MachineOpCode Opcode) const {
254 return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
257 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
258 /// custom insertion support when the DAG scheduler is inserting it into a
259 /// machine basic block.
260 bool usesCustomDAGSchedInsertionHook(MachineOpCode Opcode) const {
261 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
264 bool hasVariableOperands(MachineOpCode Opcode) const {
265 return get(Opcode).Flags & M_VARIABLE_OPS;
268 /// getOperandConstraint - Returns the value of the specific constraint if
269 /// it is set. Returns -1 if it is not set.
270 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum,
271 TOI::OperandConstraint Constraint) const {
272 return get(Opcode).getOperandConstraint(OpNum, Constraint);
275 /// Return true if the instruction is a register to register move
276 /// and leave the source and dest operands in the passed parameters.
277 virtual bool isMoveInstr(const MachineInstr& MI,
279 unsigned& destReg) const {
283 /// isLoadFromStackSlot - If the specified machine instruction is a direct
284 /// load from a stack slot, return the virtual or physical register number of
285 /// the destination along with the FrameIndex of the loaded stack slot. If
286 /// not, return 0. This predicate must return 0 if the instruction has
287 /// any side effects other than loading from the stack slot.
288 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
292 /// isStoreToStackSlot - If the specified machine instruction is a direct
293 /// store to a stack slot, return the virtual or physical register number of
294 /// the source reg along with the FrameIndex of the loaded stack slot. If
295 /// not, return 0. This predicate must return 0 if the instruction has
296 /// any side effects other than storing to the stack slot.
297 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
301 /// isOtherReMaterializableLoad - If the specified machine instruction is a
302 /// direct load that is trivially rematerializable, not counting loads from
303 /// stack slots, return true. If not, return false. This predicate must
304 /// return false if the instruction has any side effects other than
305 /// producing the value from the load, or if it requres any address
306 /// registers that are not always available.
307 virtual bool isOtherReMaterializableLoad(MachineInstr *MI) const {
311 /// convertToThreeAddress - This method must be implemented by targets that
312 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
313 /// may be able to convert a two-address instruction into one or moretrue
314 /// three-address instructions on demand. This allows the X86 target (for
315 /// example) to convert ADD and SHL instructions into LEA instructions if they
316 /// would require register copies due to two-addressness.
318 /// This method returns a null pointer if the transformation cannot be
319 /// performed, otherwise it returns the last new instruction.
321 virtual MachineInstr *
322 convertToThreeAddress(MachineFunction::iterator &MFI,
323 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
327 /// commuteInstruction - If a target has any instructions that are commutable,
328 /// but require converting to a different instruction or making non-trivial
329 /// changes to commute them, this method can overloaded to do this. The
330 /// default implementation of this method simply swaps the first two operands
331 /// of MI and returns it.
333 /// If a target wants to make more aggressive changes, they can construct and
334 /// return a new machine instruction. If an instruction cannot commute, it
335 /// can also return null.
337 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
339 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
340 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
341 /// implemented for a target). Upon success, this returns false and returns
342 /// with the following information in various cases:
344 /// 1. If this block ends with no branches (it just falls through to its succ)
345 /// just return false, leaving TBB/FBB null.
346 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
347 /// the destination block.
348 /// 3. If this block ends with an conditional branch and it falls through to
349 /// an successor block, it sets TBB to be the branch destination block and a
350 /// list of operands that evaluate the condition. These
351 /// operands can be passed to other TargetInstrInfo methods to create new
353 /// 4. If this block ends with an conditional branch and an unconditional
354 /// block, it returns the 'true' destination in TBB, the 'false' destination
355 /// in FBB, and a list of operands that evaluate the condition. These
356 /// operands can be passed to other TargetInstrInfo methods to create new
359 /// Note that RemoveBranch and InsertBranch must be implemented to support
360 /// cases where this method returns success.
362 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
363 MachineBasicBlock *&FBB,
364 std::vector<MachineOperand> &Cond) const {
368 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
369 /// this is only invoked in cases where AnalyzeBranch returns success. It
370 /// returns the number of instructions that were removed.
371 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
372 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
376 /// InsertBranch - Insert a branch into the end of the specified
377 /// MachineBasicBlock. This operands to this method are the same as those
378 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
379 /// returns success and when an unconditional branch (TBB is non-null, FBB is
380 /// null, Cond is empty) needs to be inserted. It returns the number of
381 /// instructions inserted.
382 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
383 MachineBasicBlock *FBB,
384 const std::vector<MachineOperand> &Cond) const {
385 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
389 /// BlockHasNoFallThrough - Return true if the specified block does not
390 /// fall-through into its successor block. This is primarily used when a
391 /// branch is unanalyzable. It is useful for things like unconditional
392 /// indirect branches (jump tables).
393 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
397 /// ReverseBranchCondition - Reverses the branch condition of the specified
398 /// condition list, returning false on success and true if it cannot be
400 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
404 /// insertNoop - Insert a noop into the instruction stream at the specified
406 virtual void insertNoop(MachineBasicBlock &MBB,
407 MachineBasicBlock::iterator MI) const {
408 assert(0 && "Target didn't implement insertNoop!");
412 /// isPredicated - Returns true if the instruction is already predicated.
414 virtual bool isPredicated(const MachineInstr *MI) const {
418 /// isUnpredicatedTerminator - Returns true if the instruction is a
419 /// terminator instruction that has not been predicated.
420 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
422 /// PredicateInstruction - Convert the instruction into a predicated
423 /// instruction. It returns true if the operation was successful.
425 bool PredicateInstruction(MachineInstr *MI,
426 const std::vector<MachineOperand> &Pred) const;
428 /// SubsumesPredicate - Returns true if the first specified predicate
429 /// subsumes the second, e.g. GE subsumes GT.
431 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
432 const std::vector<MachineOperand> &Pred2) const {
436 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
438 virtual const TargetRegisterClass *getPointerRegClass() const {
439 assert(0 && "Target didn't implement getPointerRegClass!");
441 return 0; // Must return a value in order to compile with VS 2005
445 } // End llvm namespace