1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
26 string Namespace = "";
29 // Register - You should define one instance of this class for each register
30 // in the target machine. String n will become the "name" of the register.
31 class Register<string n> {
32 string Namespace = "";
35 // SpillSize - If this value is set to a non-zero value, it is the size in
36 // bits of the spill slot required to hold this register. If this value is
37 // set to zero, the information is inferred from any register classes the
38 // register belongs to.
41 // SpillAlignment - This value is used to specify the alignment required for
42 // spilling the register. Like SpillSize, this should only be explicitly
43 // specified if the register is not in a register class.
44 int SpillAlignment = 0;
46 // Aliases - A list of registers that this register overlaps with. A read or
47 // modification of this register can potentially read or modify the aliased
49 list<Register> Aliases = [];
51 // SubRegs - A list of registers that are parts of this register. Note these
52 // are "immediate" sub-registers and the registers within the list do not
53 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
55 list<Register> SubRegs = [];
57 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
58 // to address it. Sub-sub-register indices are automatically inherited from
60 list<SubRegIndex> SubRegIndices = [];
62 // CompositeIndices - Specify subreg indices that don't correspond directly to
63 // a register in SubRegs and are not inherited. The following formats are
66 // (a) Identity - Reg:a == Reg
67 // (a b) Alias - Reg:a == Reg:b
68 // (a b,c) Composite - Reg:a == (Reg:b):c
70 // This can be used to disambiguate a sub-sub-register that exists in more
71 // than one subregister and other weird stuff.
72 list<dag> CompositeIndices = [];
74 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
75 // These values can be determined by locating the <target>.h file in the
76 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
77 // order of these names correspond to the enumeration used by gcc. A value of
78 // -1 indicates that the gcc number is undefined and -2 that register number
79 // is invalid for this mode/flavour.
80 list<int> DwarfNumbers = [];
82 // CostPerUse - Additional cost of instructions using this register compared
83 // to other registers in its class. The register allocator will try to
84 // minimize the number of instructions using a register with a CostPerUse.
85 // This is used by the x86-64 and ARM Thumb targets where some registers
86 // require larger instruction encodings.
90 // RegisterWithSubRegs - This can be used to define instances of Register which
91 // need to specify sub-registers.
92 // List "subregs" specifies which registers are sub-registers to this one. This
93 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
94 // This allows the code generator to be careful not to put two values with
95 // overlapping live ranges into registers which alias.
96 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
97 let SubRegs = subregs;
100 // RegisterClass - Now that all of the registers are defined, and aliases
101 // between registers are defined, specify which registers belong to which
102 // register classes. This also defines the default allocation order of
103 // registers by register allocators.
105 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
106 list<Register> regList> {
107 string Namespace = namespace;
109 // RegType - Specify the list ValueType of the registers in this register
110 // class. Note that all registers in a register class must have the same
111 // ValueTypes. This is a list because some targets permit storing different
112 // types in same register, for example vector values with 128-bit total size,
113 // but different count/size of items, like SSE on x86.
115 list<ValueType> RegTypes = regTypes;
117 // Size - Specify the spill size in bits of the registers. A default value of
118 // zero lets tablgen pick an appropriate size.
121 // Alignment - Specify the alignment required of the registers when they are
122 // stored or loaded to memory.
124 int Alignment = alignment;
126 // CopyCost - This value is used to specify the cost of copying a value
127 // between two registers in this register class. The default value is one
128 // meaning it takes a single instruction to perform the copying. A negative
129 // value means copying is extremely expensive or impossible.
132 // MemberList - Specify which registers are in this class. If the
133 // allocation_order_* method are not specified, this also defines the order of
134 // allocation used by the register allocator.
136 list<Register> MemberList = regList;
138 // SubRegClasses - Specify the register class of subregisters as a list of
139 // dags: (RegClass SubRegIndex, SubRegindex, ...)
140 list<dag> SubRegClasses = [];
142 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
143 // code into a generated register class. The normal usage of this is to
144 // overload virtual methods.
145 code MethodProtos = [{}];
146 code MethodBodies = [{}];
150 //===----------------------------------------------------------------------===//
151 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
152 // to the register numbering used by gcc and gdb. These values are used by a
153 // debug information writer to describe where values may be located during
155 class DwarfRegNum<list<int> Numbers> {
156 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
157 // These values can be determined by locating the <target>.h file in the
158 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
159 // order of these names correspond to the enumeration used by gcc. A value of
160 // -1 indicates that the gcc number is undefined and -2 that register number
161 // is invalid for this mode/flavour.
162 list<int> DwarfNumbers = Numbers;
165 //===----------------------------------------------------------------------===//
166 // Pull in the common support for scheduling
168 include "llvm/Target/TargetSchedule.td"
170 class Predicate; // Forward def
172 //===----------------------------------------------------------------------===//
173 // Instruction set description - These classes correspond to the C++ classes in
174 // the Target/TargetInstrInfo.h file.
177 string Namespace = "";
179 dag OutOperandList; // An dag containing the MI def operand list.
180 dag InOperandList; // An dag containing the MI use operand list.
181 string AsmString = ""; // The .s format to print the instruction with.
183 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
184 // otherwise, uninitialized.
187 // The follow state will eventually be inferred automatically from the
188 // instruction pattern.
190 list<Register> Uses = []; // Default to using no non-operand registers
191 list<Register> Defs = []; // Default to modifying no non-operand registers
193 // Predicates - List of predicates which will be turned into isel matching
195 list<Predicate> Predicates = [];
200 // Added complexity passed onto matching pattern.
201 int AddedComplexity = 0;
203 // These bits capture information about the high-level semantics of the
205 bit isReturn = 0; // Is this instruction a return instruction?
206 bit isBranch = 0; // Is this instruction a branch instruction?
207 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
208 bit isCompare = 0; // Is this instruction a comparison instruction?
209 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
210 bit isBitcast = 0; // Is this instruction a bitcast instruction?
211 bit isBarrier = 0; // Can control flow fall through this instruction?
212 bit isCall = 0; // Is this instruction a call instruction?
213 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
214 bit mayLoad = 0; // Is it possible for this inst to read memory?
215 bit mayStore = 0; // Is it possible for this inst to write memory?
216 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
217 bit isCommutable = 0; // Is this 3 operand instruction commutable?
218 bit isTerminator = 0; // Is this part of the terminator for a basic block?
219 bit isReMaterializable = 0; // Is this instruction re-materializable?
220 bit isPredicable = 0; // Is this instruction predicable?
221 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
222 bit usesCustomInserter = 0; // Pseudo instr needing special help.
223 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
224 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
225 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
226 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
227 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
229 // Side effect flags - When set, the flags have these meanings:
231 // hasSideEffects - The instruction has side effects that are not
232 // captured by any operands of the instruction or other flags.
234 // neverHasSideEffects - Set on an instruction with no pattern if it has no
236 bit hasSideEffects = 0;
237 bit neverHasSideEffects = 0;
239 // Is this instruction a "real" instruction (with a distinct machine
240 // encoding), or is it a pseudo instruction used for codegen modeling
242 bit isCodeGenOnly = 0;
244 // Is this instruction a pseudo instruction for use by the assembler parser.
245 bit isAsmParserOnly = 0;
247 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
249 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
251 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
252 /// be encoded into the output machineinstr.
253 string DisableEncoding = "";
255 string PostEncoderMethod = "";
256 string DecoderMethod = "";
258 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
259 bits<64> TSFlags = 0;
261 ///@name Assembler Parser Support
264 string AsmMatchConverter = "";
269 /// Predicates - These are extra conditionals which are turned into instruction
270 /// selector matching code. Currently each predicate is just a string.
271 class Predicate<string cond> {
272 string CondString = cond;
274 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
275 /// matcher, this is true. Targets should set this by inheriting their
276 /// feature from the AssemblerPredicate class in addition to Predicate.
277 bit AssemblerMatcherPredicate = 0;
280 /// NoHonorSignDependentRounding - This predicate is true if support for
281 /// sign-dependent-rounding is not enabled.
282 def NoHonorSignDependentRounding
283 : Predicate<"!HonorSignDependentRoundingFPMath()">;
285 class Requires<list<Predicate> preds> {
286 list<Predicate> Predicates = preds;
289 /// ops definition - This is just a simple marker used to identify the operand
290 /// list for an instruction. outs and ins are identical both syntactically and
291 /// semanticallyr; they are used to define def operands and use operands to
292 /// improve readibility. This should be used like this:
293 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
298 /// variable_ops definition - Mark this instruction as taking a variable number
303 /// PointerLikeRegClass - Values that are designed to have pointer width are
304 /// derived from this. TableGen treats the register class as having a symbolic
305 /// type that it doesn't know, and resolves the actual regclass to use by using
306 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
307 class PointerLikeRegClass<int Kind> {
308 int RegClassKind = Kind;
312 /// ptr_rc definition - Mark this operand as being a pointer value whose
313 /// register class is resolved dynamically via a callback to TargetInstrInfo.
314 /// FIXME: We should probably change this to a class which contain a list of
315 /// flags. But currently we have but one flag.
316 def ptr_rc : PointerLikeRegClass<0>;
318 /// unknown definition - Mark this operand as being of unknown type, causing
319 /// it to be resolved by inference in the context it is used.
322 /// AsmOperandClass - Representation for the kinds of operands which the target
323 /// specific parser can create and the assembly matcher may need to distinguish.
325 /// Operand classes are used to define the order in which instructions are
326 /// matched, to ensure that the instruction which gets matched for any
327 /// particular list of operands is deterministic.
329 /// The target specific parser must be able to classify a parsed operand into a
330 /// unique class which does not partially overlap with any other classes. It can
331 /// match a subset of some other class, in which case the super class field
332 /// should be defined.
333 class AsmOperandClass {
334 /// The name to use for this class, which should be usable as an enum value.
337 /// The super classes of this operand.
338 list<AsmOperandClass> SuperClasses = [];
340 /// The name of the method on the target specific operand to call to test
341 /// whether the operand is an instance of this class. If not set, this will
342 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
343 /// signature should be:
344 /// bool isFoo() const;
345 string PredicateMethod = ?;
347 /// The name of the method on the target specific operand to call to add the
348 /// target specific operand to an MCInst. If not set, this will default to
349 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
350 /// signature should be:
351 /// void addFooOperands(MCInst &Inst, unsigned N) const;
352 string RenderMethod = ?;
354 /// The name of the method on the target specific operand to call to custom
355 /// handle the operand parsing. This is useful when the operands do not relate
356 /// to immediates or registers and are very instruction specific (as flags to
357 /// set in a processor register, coprocessor number, ...).
358 string ParserMethod = ?;
361 def ImmAsmOperand : AsmOperandClass {
365 /// Operand Types - These provide the built-in operand types that may be used
366 /// by a target. Targets can optionally provide their own operand types as
367 /// needed, though this should not be needed for RISC targets.
368 class Operand<ValueType ty> {
370 string PrintMethod = "printOperand";
371 string EncoderMethod = "";
372 string DecoderMethod = "";
373 string AsmOperandLowerMethod = ?;
374 dag MIOperandInfo = (ops);
376 // ParserMatchClass - The "match class" that operands of this type fit
377 // in. Match classes are used to define the order in which instructions are
378 // match, to ensure that which instructions gets matched is deterministic.
380 // The target specific parser must be able to classify an parsed operand into
381 // a unique class, which does not partially overlap with any other classes. It
382 // can match a subset of some other class, in which case the AsmOperandClass
383 // should declare the other operand as one of its super classes.
384 AsmOperandClass ParserMatchClass = ImmAsmOperand;
387 def i1imm : Operand<i1>;
388 def i8imm : Operand<i8>;
389 def i16imm : Operand<i16>;
390 def i32imm : Operand<i32>;
391 def i64imm : Operand<i64>;
393 def f32imm : Operand<f32>;
394 def f64imm : Operand<f64>;
396 /// zero_reg definition - Special node to stand for the zero register.
400 /// PredicateOperand - This can be used to define a predicate operand for an
401 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
402 /// AlwaysVal specifies the value of this predicate when set to "always
404 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
406 let MIOperandInfo = OpTypes;
407 dag DefaultOps = AlwaysVal;
410 /// OptionalDefOperand - This is used to define a optional definition operand
411 /// for an instruction. DefaultOps is the register the operand represents if
412 /// none is supplied, e.g. zero_reg.
413 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
415 let MIOperandInfo = OpTypes;
416 dag DefaultOps = defaultops;
420 // InstrInfo - This class should only be instantiated once to provide parameters
421 // which are global to the target machine.
424 // Target can specify its instructions in either big or little-endian formats.
425 // For instance, while both Sparc and PowerPC are big-endian platforms, the
426 // Sparc manual specifies its instructions in the format [31..0] (big), while
427 // PowerPC specifies them using the format [0..31] (little).
428 bit isLittleEndianEncoding = 0;
431 // Standard Pseudo Instructions.
432 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
433 // Only these instructions are allowed in the TargetOpcode namespace.
434 let isCodeGenOnly = 1, Namespace = "TargetOpcode" in {
435 def PHI : Instruction {
436 let OutOperandList = (outs);
437 let InOperandList = (ins variable_ops);
438 let AsmString = "PHINODE";
440 def INLINEASM : Instruction {
441 let OutOperandList = (outs);
442 let InOperandList = (ins variable_ops);
444 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
446 def PROLOG_LABEL : Instruction {
447 let OutOperandList = (outs);
448 let InOperandList = (ins i32imm:$id);
451 let isNotDuplicable = 1;
453 def EH_LABEL : Instruction {
454 let OutOperandList = (outs);
455 let InOperandList = (ins i32imm:$id);
458 let isNotDuplicable = 1;
460 def GC_LABEL : Instruction {
461 let OutOperandList = (outs);
462 let InOperandList = (ins i32imm:$id);
465 let isNotDuplicable = 1;
467 def KILL : Instruction {
468 let OutOperandList = (outs);
469 let InOperandList = (ins variable_ops);
471 let neverHasSideEffects = 1;
473 def EXTRACT_SUBREG : Instruction {
474 let OutOperandList = (outs unknown:$dst);
475 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
477 let neverHasSideEffects = 1;
479 def INSERT_SUBREG : Instruction {
480 let OutOperandList = (outs unknown:$dst);
481 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
483 let neverHasSideEffects = 1;
484 let Constraints = "$supersrc = $dst";
486 def IMPLICIT_DEF : Instruction {
487 let OutOperandList = (outs unknown:$dst);
488 let InOperandList = (ins);
490 let neverHasSideEffects = 1;
491 let isReMaterializable = 1;
492 let isAsCheapAsAMove = 1;
494 def SUBREG_TO_REG : Instruction {
495 let OutOperandList = (outs unknown:$dst);
496 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
498 let neverHasSideEffects = 1;
500 def COPY_TO_REGCLASS : Instruction {
501 let OutOperandList = (outs unknown:$dst);
502 let InOperandList = (ins unknown:$src, i32imm:$regclass);
504 let neverHasSideEffects = 1;
505 let isAsCheapAsAMove = 1;
507 def DBG_VALUE : Instruction {
508 let OutOperandList = (outs);
509 let InOperandList = (ins variable_ops);
510 let AsmString = "DBG_VALUE";
511 let neverHasSideEffects = 1;
513 def REG_SEQUENCE : Instruction {
514 let OutOperandList = (outs unknown:$dst);
515 let InOperandList = (ins variable_ops);
517 let neverHasSideEffects = 1;
518 let isAsCheapAsAMove = 1;
520 def COPY : Instruction {
521 let OutOperandList = (outs unknown:$dst);
522 let InOperandList = (ins unknown:$src);
524 let neverHasSideEffects = 1;
525 let isAsCheapAsAMove = 1;
529 //===----------------------------------------------------------------------===//
530 // AsmParser - This class can be implemented by targets that wish to implement
533 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
534 // syntax on X86 for example).
537 // AsmParserClassName - This specifies the suffix to use for the asmparser
538 // class. Generated AsmParser classes are always prefixed with the target
540 string AsmParserClassName = "AsmParser";
542 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
543 // function of the AsmParser class to call on every matched instruction.
544 // This can be used to perform target specific instruction post-processing.
545 string AsmParserInstCleanup = "";
547 // Variant - AsmParsers can be of multiple different variants. Variants are
548 // used to support targets that need to parser multiple formats for the
549 // assembly language.
552 // CommentDelimiter - If given, the delimiter string used to recognize
553 // comments which are hard coded in the .td assembler strings for individual
555 string CommentDelimiter = "";
557 // RegisterPrefix - If given, the token prefix which indicates a register
558 // token. This is used by the matcher to automatically recognize hard coded
559 // register tokens as constrained registers, instead of tokens, for the
560 // purposes of matching.
561 string RegisterPrefix = "";
563 def DefaultAsmParser : AsmParser;
565 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
566 /// matches instructions and aliases.
567 class AssemblerPredicate {
568 bit AssemblerMatcherPredicate = 1;
573 /// MnemonicAlias - This class allows targets to define assembler mnemonic
574 /// aliases. This should be used when all forms of one mnemonic are accepted
575 /// with a different mnemonic. For example, X86 allows:
576 /// sal %al, 1 -> shl %al, 1
577 /// sal %ax, %cl -> shl %ax, %cl
578 /// sal %eax, %cl -> shl %eax, %cl
579 /// etc. Though "sal" is accepted with many forms, all of them are directly
580 /// translated to a shl, so it can be handled with (in the case of X86, it
581 /// actually has one for each suffix as well):
582 /// def : MnemonicAlias<"sal", "shl">;
584 /// Mnemonic aliases are mapped before any other translation in the match phase,
585 /// and do allow Requires predicates, e.g.:
587 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
588 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
590 class MnemonicAlias<string From, string To> {
591 string FromMnemonic = From;
592 string ToMnemonic = To;
594 // Predicates - Predicates that must be true for this remapping to happen.
595 list<Predicate> Predicates = [];
598 /// InstAlias - This defines an alternate assembly syntax that is allowed to
599 /// match an instruction that has a different (more canonical) assembly
601 class InstAlias<string Asm, dag Result, bit Emit = 0b1> {
602 string AsmString = Asm; // The .s format to match the instruction with.
603 dag ResultInst = Result; // The MCInst to generate.
604 bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
606 // Predicates - Predicates that must be true for this to match.
607 list<Predicate> Predicates = [];
610 //===----------------------------------------------------------------------===//
611 // AsmWriter - This class can be implemented by targets that need to customize
612 // the format of the .s file writer.
614 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
615 // on X86 for example).
618 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
619 // class. Generated AsmWriter classes are always prefixed with the target
621 string AsmWriterClassName = "AsmPrinter";
623 // Variant - AsmWriters can be of multiple different variants. Variants are
624 // used to support targets that need to emit assembly code in ways that are
625 // mostly the same for different targets, but have minor differences in
626 // syntax. If the asmstring contains {|} characters in them, this integer
627 // will specify which alternative to use. For example "{x|y|z}" with Variant
628 // == 1, will expand to "y".
632 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
633 // layout, the asmwriter can actually generate output in this columns (in
634 // verbose-asm mode). These two values indicate the width of the first column
635 // (the "opcode" area) and the width to reserve for subsequent operands. When
636 // verbose asm mode is enabled, operands will be indented to respect this.
637 int FirstOperandColumn = -1;
639 // OperandSpacing - Space between operand columns.
640 int OperandSpacing = -1;
642 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
643 // generation of the printInstruction() method. For MC printers, it takes
644 // an MCInstr* operand, otherwise it takes a MachineInstr*.
645 bit isMCAsmWriter = 0;
647 def DefaultAsmWriter : AsmWriter;
650 //===----------------------------------------------------------------------===//
651 // Target - This class contains the "global" target information
654 // InstructionSet - Instruction set description for this target.
655 InstrInfo InstructionSet;
657 // AssemblyParsers - The AsmParser instances available for this target.
658 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
660 // AssemblyWriters - The AsmWriter instances available for this target.
661 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
664 //===----------------------------------------------------------------------===//
665 // SubtargetFeature - A characteristic of the chip set.
667 class SubtargetFeature<string n, string a, string v, string d,
668 list<SubtargetFeature> i = []> {
669 // Name - Feature name. Used by command line (-mattr=) to determine the
670 // appropriate target chip.
674 // Attribute - Attribute to be set by feature.
676 string Attribute = a;
678 // Value - Value the attribute to be set to by feature.
682 // Desc - Feature description. Used by command line (-mattr=) to display help
687 // Implies - Features that this feature implies are present. If one of those
688 // features isn't set, then this one shouldn't be set either.
690 list<SubtargetFeature> Implies = i;
693 //===----------------------------------------------------------------------===//
694 // Processor chip sets - These values represent each of the chip sets supported
695 // by the scheduler. Each Processor definition requires corresponding
696 // instruction itineraries.
698 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
699 // Name - Chip set name. Used by command line (-mcpu=) to determine the
700 // appropriate target chip.
704 // ProcItin - The scheduling information for the target processor.
706 ProcessorItineraries ProcItin = pi;
708 // Features - list of
709 list<SubtargetFeature> Features = f;
712 //===----------------------------------------------------------------------===//
713 // Pull in the common support for calling conventions.
715 include "llvm/Target/TargetCallingConv.td"
717 //===----------------------------------------------------------------------===//
718 // Pull in the common support for DAG isel generation.
720 include "llvm/Target/TargetSelectionDAG.td"