1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/IR/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
25 class SubRegIndex<list<SubRegIndex> comps = []> {
26 string Namespace = "";
28 // ComposedOf - A list of two SubRegIndex instances, [A, B].
29 // This indicates that this SubRegIndex is the result of composing A and B.
30 list<SubRegIndex> ComposedOf = comps;
32 // CoveringSubRegIndices - A list of two or more sub-register indexes that
33 // cover this sub-register.
35 // This field should normally be left blank as TableGen can infer it.
37 // TableGen automatically detects sub-registers that straddle the registers
38 // in the SubRegs field of a Register definition. For example:
40 // Q0 = dsub_0 -> D0, dsub_1 -> D1
41 // Q1 = dsub_0 -> D2, dsub_1 -> D3
42 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2
43 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1
45 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given
46 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with
47 // CoveringSubRegIndices = [dsub_1, dsub_2].
48 list<SubRegIndex> CoveringSubRegIndices = [];
51 // RegAltNameIndex - The alternate name set to use for register operands of
52 // this register class when printing.
53 class RegAltNameIndex {
54 string Namespace = "";
56 def NoRegAltName : RegAltNameIndex;
58 // Register - You should define one instance of this class for each register
59 // in the target machine. String n will become the "name" of the register.
60 class Register<string n, list<string> altNames = []> {
61 string Namespace = "";
63 list<string> AltNames = altNames;
65 // Aliases - A list of registers that this register overlaps with. A read or
66 // modification of this register can potentially read or modify the aliased
68 list<Register> Aliases = [];
70 // SubRegs - A list of registers that are parts of this register. Note these
71 // are "immediate" sub-registers and the registers within the list do not
72 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
74 list<Register> SubRegs = [];
76 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
77 // to address it. Sub-sub-register indices are automatically inherited from
79 list<SubRegIndex> SubRegIndices = [];
81 // RegAltNameIndices - The alternate name indices which are valid for this
83 list<RegAltNameIndex> RegAltNameIndices = [];
85 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
86 // These values can be determined by locating the <target>.h file in the
87 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
88 // order of these names correspond to the enumeration used by gcc. A value of
89 // -1 indicates that the gcc number is undefined and -2 that register number
90 // is invalid for this mode/flavour.
91 list<int> DwarfNumbers = [];
93 // CostPerUse - Additional cost of instructions using this register compared
94 // to other registers in its class. The register allocator will try to
95 // minimize the number of instructions using a register with a CostPerUse.
96 // This is used by the x86-64 and ARM Thumb targets where some registers
97 // require larger instruction encodings.
100 // CoveredBySubRegs - When this bit is set, the value of this register is
101 // completely determined by the value of its sub-registers. For example, the
102 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
103 // covered by its sub-register AX.
104 bit CoveredBySubRegs = 0;
106 // HWEncoding - The target specific hardware encoding for this register.
107 bits<16> HWEncoding = 0;
110 // RegisterWithSubRegs - This can be used to define instances of Register which
111 // need to specify sub-registers.
112 // List "subregs" specifies which registers are sub-registers to this one. This
113 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
114 // This allows the code generator to be careful not to put two values with
115 // overlapping live ranges into registers which alias.
116 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
117 let SubRegs = subregs;
120 // DAGOperand - An empty base class that unifies RegisterClass's and other forms
121 // of Operand's that are legal as type qualifiers in DAG patterns. This should
122 // only ever be used for defining multiclasses that are polymorphic over both
123 // RegisterClass's and other Operand's.
126 // RegisterClass - Now that all of the registers are defined, and aliases
127 // between registers are defined, specify which registers belong to which
128 // register classes. This also defines the default allocation order of
129 // registers by register allocators.
131 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
132 dag regList, RegAltNameIndex idx = NoRegAltName>
134 string Namespace = namespace;
136 // RegType - Specify the list ValueType of the registers in this register
137 // class. Note that all registers in a register class must have the same
138 // ValueTypes. This is a list because some targets permit storing different
139 // types in same register, for example vector values with 128-bit total size,
140 // but different count/size of items, like SSE on x86.
142 list<ValueType> RegTypes = regTypes;
144 // Size - Specify the spill size in bits of the registers. A default value of
145 // zero lets tablgen pick an appropriate size.
148 // Alignment - Specify the alignment required of the registers when they are
149 // stored or loaded to memory.
151 int Alignment = alignment;
153 // CopyCost - This value is used to specify the cost of copying a value
154 // between two registers in this register class. The default value is one
155 // meaning it takes a single instruction to perform the copying. A negative
156 // value means copying is extremely expensive or impossible.
159 // MemberList - Specify which registers are in this class. If the
160 // allocation_order_* method are not specified, this also defines the order of
161 // allocation used by the register allocator.
163 dag MemberList = regList;
165 // AltNameIndex - The alternate register name to use when printing operands
166 // of this register class. Every register in the register class must have
167 // a valid alternate name for the given index.
168 RegAltNameIndex altNameIndex = idx;
170 // isAllocatable - Specify that the register class can be used for virtual
171 // registers and register allocation. Some register classes are only used to
172 // model instruction operand constraints, and should have isAllocatable = 0.
173 bit isAllocatable = 1;
175 // AltOrders - List of alternative allocation orders. The default order is
176 // MemberList itself, and that is good enough for most targets since the
177 // register allocators automatically remove reserved registers and move
178 // callee-saved registers to the end.
179 list<dag> AltOrders = [];
181 // AltOrderSelect - The body of a function that selects the allocation order
182 // to use in a given machine function. The code will be inserted in a
183 // function like this:
185 // static inline unsigned f(const MachineFunction &MF) { ... }
187 // The function should return 0 to select the default order defined by
188 // MemberList, 1 to select the first AltOrders entry and so on.
189 code AltOrderSelect = [{}];
192 // The memberList in a RegisterClass is a dag of set operations. TableGen
193 // evaluates these set operations and expand them into register lists. These
194 // are the most common operation, see test/TableGen/SetTheory.td for more
195 // examples of what is possible:
197 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
198 // register class, or a sub-expression. This is also the way to simply list
201 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
203 // (and GPR, CSR) - Set intersection. All registers from the first set that are
204 // also in the second set.
206 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
207 // numbered registers. Takes an optional 4th operand which is a stride to use
208 // when generating the sequence.
210 // (shl GPR, 4) - Remove the first N elements.
212 // (trunc GPR, 4) - Truncate after the first N elements.
214 // (rotl GPR, 1) - Rotate N places to the left.
216 // (rotr GPR, 1) - Rotate N places to the right.
218 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
220 // (interleave A, B, ...) - Interleave the elements from each argument list.
222 // All of these operators work on ordered sets, not lists. That means
223 // duplicates are removed from sub-expressions.
225 // Set operators. The rest is defined in TargetSelectionDAG.td.
230 // RegisterTuples - Automatically generate super-registers by forming tuples of
231 // sub-registers. This is useful for modeling register sequence constraints
232 // with pseudo-registers that are larger than the architectural registers.
234 // The sub-register lists are zipped together:
236 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
238 // Generates the same registers as:
240 // let SubRegIndices = [sube, subo] in {
241 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
242 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
245 // The generated pseudo-registers inherit super-classes and fields from their
246 // first sub-register. Most fields from the Register class are inferred, and
247 // the AsmName and Dwarf numbers are cleared.
249 // RegisterTuples instances can be used in other set operations to form
250 // register classes and so on. This is the only way of using the generated
252 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
253 // SubRegs - N lists of registers to be zipped up. Super-registers are
254 // synthesized from the first element of each SubRegs list, the second
255 // element and so on.
256 list<dag> SubRegs = Regs;
258 // SubRegIndices - N SubRegIndex instances. This provides the names of the
259 // sub-registers in the synthesized super-registers.
260 list<SubRegIndex> SubRegIndices = Indices;
264 //===----------------------------------------------------------------------===//
265 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
266 // to the register numbering used by gcc and gdb. These values are used by a
267 // debug information writer to describe where values may be located during
269 class DwarfRegNum<list<int> Numbers> {
270 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
271 // These values can be determined by locating the <target>.h file in the
272 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
273 // order of these names correspond to the enumeration used by gcc. A value of
274 // -1 indicates that the gcc number is undefined and -2 that register number
275 // is invalid for this mode/flavour.
276 list<int> DwarfNumbers = Numbers;
279 // DwarfRegAlias - This class declares that a given register uses the same dwarf
280 // numbers as another one. This is useful for making it clear that the two
281 // registers do have the same number. It also lets us build a mapping
282 // from dwarf register number to llvm register.
283 class DwarfRegAlias<Register reg> {
284 Register DwarfAlias = reg;
287 //===----------------------------------------------------------------------===//
288 // Pull in the common support for scheduling
290 include "llvm/Target/TargetSchedule.td"
292 class Predicate; // Forward def
294 //===----------------------------------------------------------------------===//
295 // Instruction set description - These classes correspond to the C++ classes in
296 // the Target/TargetInstrInfo.h file.
299 string Namespace = "";
301 dag OutOperandList; // An dag containing the MI def operand list.
302 dag InOperandList; // An dag containing the MI use operand list.
303 string AsmString = ""; // The .s format to print the instruction with.
305 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
306 // otherwise, uninitialized.
309 // The follow state will eventually be inferred automatically from the
310 // instruction pattern.
312 list<Register> Uses = []; // Default to using no non-operand registers
313 list<Register> Defs = []; // Default to modifying no non-operand registers
315 // Predicates - List of predicates which will be turned into isel matching
317 list<Predicate> Predicates = [];
319 // Size - Size of encoded instruction, or zero if the size cannot be determined
323 // DecoderNamespace - The "namespace" in which this instruction exists, on
324 // targets like ARM which multiple ISA namespaces exist.
325 string DecoderNamespace = "";
327 // Code size, for instruction selection.
328 // FIXME: What does this actually mean?
331 // Added complexity passed onto matching pattern.
332 int AddedComplexity = 0;
334 // These bits capture information about the high-level semantics of the
336 bit isReturn = 0; // Is this instruction a return instruction?
337 bit isBranch = 0; // Is this instruction a branch instruction?
338 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
339 bit isCompare = 0; // Is this instruction a comparison instruction?
340 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
341 bit isBitcast = 0; // Is this instruction a bitcast instruction?
342 bit isSelect = 0; // Is this instruction a select instruction?
343 bit isBarrier = 0; // Can control flow fall through this instruction?
344 bit isCall = 0; // Is this instruction a call instruction?
345 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
346 bit mayLoad = ?; // Is it possible for this inst to read memory?
347 bit mayStore = ?; // Is it possible for this inst to write memory?
348 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
349 bit isCommutable = 0; // Is this 3 operand instruction commutable?
350 bit isTerminator = 0; // Is this part of the terminator for a basic block?
351 bit isReMaterializable = 0; // Is this instruction re-materializable?
352 bit isPredicable = 0; // Is this instruction predicable?
353 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
354 bit usesCustomInserter = 0; // Pseudo instr needing special help.
355 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
356 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
357 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
358 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
359 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
360 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
361 bit isPseudo = 0; // Is this instruction a pseudo-instruction?
362 // If so, won't have encoding information for
363 // the [MC]CodeEmitter stuff.
365 // Side effect flags - When set, the flags have these meanings:
367 // hasSideEffects - The instruction has side effects that are not
368 // captured by any operands of the instruction or other flags.
370 // neverHasSideEffects (deprecated) - Set on an instruction with no pattern
371 // if it has no side effects. This is now equivalent to setting
372 // "hasSideEffects = 0".
373 bit hasSideEffects = ?;
374 bit neverHasSideEffects = 0;
376 // Is this instruction a "real" instruction (with a distinct machine
377 // encoding), or is it a pseudo instruction used for codegen modeling
379 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
380 // instructions can (and often do) still have encoding information
381 // associated with them. Once we've migrated all of them over to true
382 // pseudo-instructions that are lowered to real instructions prior to
383 // the printer/emitter, we can remove this attribute and just use isPseudo.
385 // The intended use is:
386 // isPseudo: Does not have encoding information and should be expanded,
387 // at the latest, during lowering to MCInst.
389 // isCodeGenOnly: Does have encoding information and can go through to the
390 // CodeEmitter unchanged, but duplicates a canonical instruction
391 // definition's encoding and should be ignored when constructing the
392 // assembler match tables.
393 bit isCodeGenOnly = 0;
395 // Is this instruction a pseudo instruction for use by the assembler parser.
396 bit isAsmParserOnly = 0;
398 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
400 // Scheduling information from TargetSchedule.td.
401 list<SchedReadWrite> SchedRW;
403 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
405 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
406 /// be encoded into the output machineinstr.
407 string DisableEncoding = "";
409 string PostEncoderMethod = "";
410 string DecoderMethod = "";
412 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
413 bits<64> TSFlags = 0;
415 ///@name Assembler Parser Support
418 string AsmMatchConverter = "";
420 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
421 /// two-operand matcher inst-alias for a three operand instruction.
422 /// For example, the arm instruction "add r3, r3, r5" can be written
423 /// as "add r3, r5". The constraint is of the same form as a tied-operand
424 /// constraint. For example, "$Rn = $Rd".
425 string TwoOperandAliasConstraint = "";
430 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
431 /// Which instruction it expands to and how the operands map from the
433 class PseudoInstExpansion<dag Result> {
434 dag ResultInst = Result; // The instruction to generate.
438 /// Predicates - These are extra conditionals which are turned into instruction
439 /// selector matching code. Currently each predicate is just a string.
440 class Predicate<string cond> {
441 string CondString = cond;
443 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
444 /// matcher, this is true. Targets should set this by inheriting their
445 /// feature from the AssemblerPredicate class in addition to Predicate.
446 bit AssemblerMatcherPredicate = 0;
448 /// AssemblerCondString - Name of the subtarget feature being tested used
449 /// as alternative condition string used for assembler matcher.
450 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
451 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
452 /// It can also list multiple features separated by ",".
453 /// e.g. "ModeThumb,FeatureThumb2" is translated to
454 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
455 string AssemblerCondString = "";
457 /// PredicateName - User-level name to use for the predicate. Mainly for use
458 /// in diagnostics such as missing feature errors in the asm matcher.
459 string PredicateName = "";
462 /// NoHonorSignDependentRounding - This predicate is true if support for
463 /// sign-dependent-rounding is not enabled.
464 def NoHonorSignDependentRounding
465 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
467 class Requires<list<Predicate> preds> {
468 list<Predicate> Predicates = preds;
471 /// ops definition - This is just a simple marker used to identify the operand
472 /// list for an instruction. outs and ins are identical both syntactically and
473 /// semanticallyr; they are used to define def operands and use operands to
474 /// improve readibility. This should be used like this:
475 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
480 /// variable_ops definition - Mark this instruction as taking a variable number
485 /// PointerLikeRegClass - Values that are designed to have pointer width are
486 /// derived from this. TableGen treats the register class as having a symbolic
487 /// type that it doesn't know, and resolves the actual regclass to use by using
488 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
489 class PointerLikeRegClass<int Kind> {
490 int RegClassKind = Kind;
494 /// ptr_rc definition - Mark this operand as being a pointer value whose
495 /// register class is resolved dynamically via a callback to TargetInstrInfo.
496 /// FIXME: We should probably change this to a class which contain a list of
497 /// flags. But currently we have but one flag.
498 def ptr_rc : PointerLikeRegClass<0>;
500 /// unknown definition - Mark this operand as being of unknown type, causing
501 /// it to be resolved by inference in the context it is used.
503 def unknown : unknown_class;
505 /// AsmOperandClass - Representation for the kinds of operands which the target
506 /// specific parser can create and the assembly matcher may need to distinguish.
508 /// Operand classes are used to define the order in which instructions are
509 /// matched, to ensure that the instruction which gets matched for any
510 /// particular list of operands is deterministic.
512 /// The target specific parser must be able to classify a parsed operand into a
513 /// unique class which does not partially overlap with any other classes. It can
514 /// match a subset of some other class, in which case the super class field
515 /// should be defined.
516 class AsmOperandClass {
517 /// The name to use for this class, which should be usable as an enum value.
520 /// The super classes of this operand.
521 list<AsmOperandClass> SuperClasses = [];
523 /// The name of the method on the target specific operand to call to test
524 /// whether the operand is an instance of this class. If not set, this will
525 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
526 /// signature should be:
527 /// bool isFoo() const;
528 string PredicateMethod = ?;
530 /// The name of the method on the target specific operand to call to add the
531 /// target specific operand to an MCInst. If not set, this will default to
532 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
533 /// signature should be:
534 /// void addFooOperands(MCInst &Inst, unsigned N) const;
535 string RenderMethod = ?;
537 /// The name of the method on the target specific operand to call to custom
538 /// handle the operand parsing. This is useful when the operands do not relate
539 /// to immediates or registers and are very instruction specific (as flags to
540 /// set in a processor register, coprocessor number, ...).
541 string ParserMethod = ?;
543 // The diagnostic type to present when referencing this operand in a
544 // match failure error message. By default, use a generic "invalid operand"
545 // diagnostic. The target AsmParser maps these codes to text.
546 string DiagnosticType = "";
549 def ImmAsmOperand : AsmOperandClass {
553 /// Operand Types - These provide the built-in operand types that may be used
554 /// by a target. Targets can optionally provide their own operand types as
555 /// needed, though this should not be needed for RISC targets.
556 class Operand<ValueType ty> : DAGOperand {
558 string PrintMethod = "printOperand";
559 string EncoderMethod = "";
560 string DecoderMethod = "";
561 string AsmOperandLowerMethod = ?;
562 string OperandType = "OPERAND_UNKNOWN";
563 dag MIOperandInfo = (ops);
565 // ParserMatchClass - The "match class" that operands of this type fit
566 // in. Match classes are used to define the order in which instructions are
567 // match, to ensure that which instructions gets matched is deterministic.
569 // The target specific parser must be able to classify an parsed operand into
570 // a unique class, which does not partially overlap with any other classes. It
571 // can match a subset of some other class, in which case the AsmOperandClass
572 // should declare the other operand as one of its super classes.
573 AsmOperandClass ParserMatchClass = ImmAsmOperand;
576 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
578 // RegClass - The register class of the operand.
579 RegisterClass RegClass = regclass;
580 // PrintMethod - The target method to call to print register operands of
581 // this type. The method normally will just use an alt-name index to look
582 // up the name to print. Default to the generic printOperand().
583 string PrintMethod = pm;
584 // ParserMatchClass - The "match class" that operands of this type fit
585 // in. Match classes are used to define the order in which instructions are
586 // match, to ensure that which instructions gets matched is deterministic.
588 // The target specific parser must be able to classify an parsed operand into
589 // a unique class, which does not partially overlap with any other classes. It
590 // can match a subset of some other class, in which case the AsmOperandClass
591 // should declare the other operand as one of its super classes.
592 AsmOperandClass ParserMatchClass;
595 let OperandType = "OPERAND_IMMEDIATE" in {
596 def i1imm : Operand<i1>;
597 def i8imm : Operand<i8>;
598 def i16imm : Operand<i16>;
599 def i32imm : Operand<i32>;
600 def i64imm : Operand<i64>;
602 def f32imm : Operand<f32>;
603 def f64imm : Operand<f64>;
606 /// zero_reg definition - Special node to stand for the zero register.
610 /// OperandWithDefaultOps - This Operand class can be used as the parent class
611 /// for an Operand that needs to be initialized with a default value if
612 /// no value is supplied in a pattern. This class can be used to simplify the
613 /// pattern definitions for instructions that have target specific flags
614 /// encoded as immediate operands.
615 class OperandWithDefaultOps<ValueType ty, dag defaultops>
617 dag DefaultOps = defaultops;
620 /// PredicateOperand - This can be used to define a predicate operand for an
621 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
622 /// AlwaysVal specifies the value of this predicate when set to "always
624 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
625 : OperandWithDefaultOps<ty, AlwaysVal> {
626 let MIOperandInfo = OpTypes;
629 /// OptionalDefOperand - This is used to define a optional definition operand
630 /// for an instruction. DefaultOps is the register the operand represents if
631 /// none is supplied, e.g. zero_reg.
632 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
633 : OperandWithDefaultOps<ty, defaultops> {
634 let MIOperandInfo = OpTypes;
638 // InstrInfo - This class should only be instantiated once to provide parameters
639 // which are global to the target machine.
642 // Target can specify its instructions in either big or little-endian formats.
643 // For instance, while both Sparc and PowerPC are big-endian platforms, the
644 // Sparc manual specifies its instructions in the format [31..0] (big), while
645 // PowerPC specifies them using the format [0..31] (little).
646 bit isLittleEndianEncoding = 0;
648 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset
649 // by default, and TableGen will infer their value from the instruction
650 // pattern when possible.
652 // Normally, TableGen will issue an error it it can't infer the value of a
653 // property that hasn't been set explicitly. When guessInstructionProperties
654 // is set, it will guess a safe value instead.
656 // This option is a temporary migration help. It will go away.
657 bit guessInstructionProperties = 1;
660 // Standard Pseudo Instructions.
661 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
662 // Only these instructions are allowed in the TargetOpcode namespace.
663 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
664 def PHI : Instruction {
665 let OutOperandList = (outs);
666 let InOperandList = (ins variable_ops);
667 let AsmString = "PHINODE";
669 def INLINEASM : Instruction {
670 let OutOperandList = (outs);
671 let InOperandList = (ins variable_ops);
673 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
675 def PROLOG_LABEL : Instruction {
676 let OutOperandList = (outs);
677 let InOperandList = (ins i32imm:$id);
680 let isNotDuplicable = 1;
682 def EH_LABEL : Instruction {
683 let OutOperandList = (outs);
684 let InOperandList = (ins i32imm:$id);
687 let isNotDuplicable = 1;
689 def GC_LABEL : Instruction {
690 let OutOperandList = (outs);
691 let InOperandList = (ins i32imm:$id);
694 let isNotDuplicable = 1;
696 def KILL : Instruction {
697 let OutOperandList = (outs);
698 let InOperandList = (ins variable_ops);
700 let neverHasSideEffects = 1;
702 def EXTRACT_SUBREG : Instruction {
703 let OutOperandList = (outs unknown:$dst);
704 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
706 let neverHasSideEffects = 1;
708 def INSERT_SUBREG : Instruction {
709 let OutOperandList = (outs unknown:$dst);
710 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
712 let neverHasSideEffects = 1;
713 let Constraints = "$supersrc = $dst";
715 def IMPLICIT_DEF : Instruction {
716 let OutOperandList = (outs unknown:$dst);
717 let InOperandList = (ins);
719 let neverHasSideEffects = 1;
720 let isReMaterializable = 1;
721 let isAsCheapAsAMove = 1;
723 def SUBREG_TO_REG : Instruction {
724 let OutOperandList = (outs unknown:$dst);
725 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
727 let neverHasSideEffects = 1;
729 def COPY_TO_REGCLASS : Instruction {
730 let OutOperandList = (outs unknown:$dst);
731 let InOperandList = (ins unknown:$src, i32imm:$regclass);
733 let neverHasSideEffects = 1;
734 let isAsCheapAsAMove = 1;
736 def DBG_VALUE : Instruction {
737 let OutOperandList = (outs);
738 let InOperandList = (ins variable_ops);
739 let AsmString = "DBG_VALUE";
740 let neverHasSideEffects = 1;
742 def REG_SEQUENCE : Instruction {
743 let OutOperandList = (outs unknown:$dst);
744 let InOperandList = (ins variable_ops);
746 let neverHasSideEffects = 1;
747 let isAsCheapAsAMove = 1;
749 def COPY : Instruction {
750 let OutOperandList = (outs unknown:$dst);
751 let InOperandList = (ins unknown:$src);
753 let neverHasSideEffects = 1;
754 let isAsCheapAsAMove = 1;
756 def BUNDLE : Instruction {
757 let OutOperandList = (outs);
758 let InOperandList = (ins variable_ops);
759 let AsmString = "BUNDLE";
761 def LIFETIME_START : Instruction {
762 let OutOperandList = (outs);
763 let InOperandList = (ins i32imm:$id);
764 let AsmString = "LIFETIME_START";
765 let neverHasSideEffects = 1;
767 def LIFETIME_END : Instruction {
768 let OutOperandList = (outs);
769 let InOperandList = (ins i32imm:$id);
770 let AsmString = "LIFETIME_END";
771 let neverHasSideEffects = 1;
775 //===----------------------------------------------------------------------===//
776 // AsmParser - This class can be implemented by targets that wish to implement
779 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
780 // syntax on X86 for example).
783 // AsmParserClassName - This specifies the suffix to use for the asmparser
784 // class. Generated AsmParser classes are always prefixed with the target
786 string AsmParserClassName = "AsmParser";
788 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
789 // function of the AsmParser class to call on every matched instruction.
790 // This can be used to perform target specific instruction post-processing.
791 string AsmParserInstCleanup = "";
793 //ShouldEmitMatchRegisterName - Set to false if the target needs a hand
794 //written register name matcher
795 bit ShouldEmitMatchRegisterName = 1;
797 def DefaultAsmParser : AsmParser;
799 //===----------------------------------------------------------------------===//
800 // AsmParserVariant - Subtargets can have multiple different assembly parsers
801 // (e.g. AT&T vs Intel syntax on X86 for example). This class can be
802 // implemented by targets to describe such variants.
804 class AsmParserVariant {
805 // Variant - AsmParsers can be of multiple different variants. Variants are
806 // used to support targets that need to parser multiple formats for the
807 // assembly language.
810 // CommentDelimiter - If given, the delimiter string used to recognize
811 // comments which are hard coded in the .td assembler strings for individual
813 string CommentDelimiter = "";
815 // RegisterPrefix - If given, the token prefix which indicates a register
816 // token. This is used by the matcher to automatically recognize hard coded
817 // register tokens as constrained registers, instead of tokens, for the
818 // purposes of matching.
819 string RegisterPrefix = "";
821 def DefaultAsmParserVariant : AsmParserVariant;
823 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
824 /// matches instructions and aliases.
825 class AssemblerPredicate<string cond, string name = ""> {
826 bit AssemblerMatcherPredicate = 1;
827 string AssemblerCondString = cond;
828 string PredicateName = name;
831 /// TokenAlias - This class allows targets to define assembler token
832 /// operand aliases. That is, a token literal operand which is equivalent
833 /// to another, canonical, token literal. For example, ARM allows:
834 /// vmov.u32 s4, #0 -> vmov.i32, #0
835 /// 'u32' is a more specific designator for the 32-bit integer type specifier
836 /// and is legal for any instruction which accepts 'i32' as a datatype suffix.
837 /// def : TokenAlias<".u32", ".i32">;
839 /// This works by marking the match class of 'From' as a subclass of the
840 /// match class of 'To'.
841 class TokenAlias<string From, string To> {
842 string FromToken = From;
846 /// MnemonicAlias - This class allows targets to define assembler mnemonic
847 /// aliases. This should be used when all forms of one mnemonic are accepted
848 /// with a different mnemonic. For example, X86 allows:
849 /// sal %al, 1 -> shl %al, 1
850 /// sal %ax, %cl -> shl %ax, %cl
851 /// sal %eax, %cl -> shl %eax, %cl
852 /// etc. Though "sal" is accepted with many forms, all of them are directly
853 /// translated to a shl, so it can be handled with (in the case of X86, it
854 /// actually has one for each suffix as well):
855 /// def : MnemonicAlias<"sal", "shl">;
857 /// Mnemonic aliases are mapped before any other translation in the match phase,
858 /// and do allow Requires predicates, e.g.:
860 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
861 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
863 class MnemonicAlias<string From, string To> {
864 string FromMnemonic = From;
865 string ToMnemonic = To;
867 // Predicates - Predicates that must be true for this remapping to happen.
868 list<Predicate> Predicates = [];
871 /// InstAlias - This defines an alternate assembly syntax that is allowed to
872 /// match an instruction that has a different (more canonical) assembly
874 class InstAlias<string Asm, dag Result, bit Emit = 0b1> {
875 string AsmString = Asm; // The .s format to match the instruction with.
876 dag ResultInst = Result; // The MCInst to generate.
877 bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
879 // Predicates - Predicates that must be true for this to match.
880 list<Predicate> Predicates = [];
883 //===----------------------------------------------------------------------===//
884 // AsmWriter - This class can be implemented by targets that need to customize
885 // the format of the .s file writer.
887 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
888 // on X86 for example).
891 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
892 // class. Generated AsmWriter classes are always prefixed with the target
894 string AsmWriterClassName = "AsmPrinter";
896 // Variant - AsmWriters can be of multiple different variants. Variants are
897 // used to support targets that need to emit assembly code in ways that are
898 // mostly the same for different targets, but have minor differences in
899 // syntax. If the asmstring contains {|} characters in them, this integer
900 // will specify which alternative to use. For example "{x|y|z}" with Variant
901 // == 1, will expand to "y".
905 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
906 // layout, the asmwriter can actually generate output in this columns (in
907 // verbose-asm mode). These two values indicate the width of the first column
908 // (the "opcode" area) and the width to reserve for subsequent operands. When
909 // verbose asm mode is enabled, operands will be indented to respect this.
910 int FirstOperandColumn = -1;
912 // OperandSpacing - Space between operand columns.
913 int OperandSpacing = -1;
915 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
916 // generation of the printInstruction() method. For MC printers, it takes
917 // an MCInstr* operand, otherwise it takes a MachineInstr*.
918 bit isMCAsmWriter = 0;
920 def DefaultAsmWriter : AsmWriter;
923 //===----------------------------------------------------------------------===//
924 // Target - This class contains the "global" target information
927 // InstructionSet - Instruction set description for this target.
928 InstrInfo InstructionSet;
930 // AssemblyParsers - The AsmParser instances available for this target.
931 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
933 /// AssemblyParserVariants - The AsmParserVariant instances available for
935 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
937 // AssemblyWriters - The AsmWriter instances available for this target.
938 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
941 //===----------------------------------------------------------------------===//
942 // SubtargetFeature - A characteristic of the chip set.
944 class SubtargetFeature<string n, string a, string v, string d,
945 list<SubtargetFeature> i = []> {
946 // Name - Feature name. Used by command line (-mattr=) to determine the
947 // appropriate target chip.
951 // Attribute - Attribute to be set by feature.
953 string Attribute = a;
955 // Value - Value the attribute to be set to by feature.
959 // Desc - Feature description. Used by command line (-mattr=) to display help
964 // Implies - Features that this feature implies are present. If one of those
965 // features isn't set, then this one shouldn't be set either.
967 list<SubtargetFeature> Implies = i;
970 //===----------------------------------------------------------------------===//
971 // Processor chip sets - These values represent each of the chip sets supported
972 // by the scheduler. Each Processor definition requires corresponding
973 // instruction itineraries.
975 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
976 // Name - Chip set name. Used by command line (-mcpu=) to determine the
977 // appropriate target chip.
981 // SchedModel - The machine model for scheduling and instruction cost.
983 SchedMachineModel SchedModel = NoSchedModel;
985 // ProcItin - The scheduling information for the target processor.
987 ProcessorItineraries ProcItin = pi;
989 // Features - list of
990 list<SubtargetFeature> Features = f;
993 // ProcessorModel allows subtargets to specify the more general
994 // SchedMachineModel instead if a ProcessorItinerary. Subtargets will
995 // gradually move to this newer form.
997 // Although this class always passes NoItineraries to the Processor
998 // class, the SchedMachineModel may still define valid Itineraries.
999 class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f>
1000 : Processor<n, NoItineraries, f> {
1004 //===----------------------------------------------------------------------===//
1005 // InstrMapping - This class is used to create mapping tables to relate
1006 // instructions with each other based on the values specified in RowFields,
1007 // ColFields, KeyCol and ValueCols.
1009 class InstrMapping {
1010 // FilterClass - Used to limit search space only to the instructions that
1011 // define the relationship modeled by this InstrMapping record.
1014 // RowFields - List of fields/attributes that should be same for all the
1015 // instructions in a row of the relation table. Think of this as a set of
1016 // properties shared by all the instructions related by this relationship
1017 // model and is used to categorize instructions into subgroups. For instance,
1018 // if we want to define a relation that maps 'Add' instruction to its
1019 // predicated forms, we can define RowFields like this:
1021 // let RowFields = BaseOp
1022 // All add instruction predicated/non-predicated will have to set their BaseOp
1023 // to the same value.
1025 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1026 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1027 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
1028 list<string> RowFields = [];
1030 // List of fields/attributes that are same for all the instructions
1031 // in a column of the relation table.
1032 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged
1033 // based on the 'predSense' values. All the instruction in a specific
1034 // column have the same value and it is fixed for the column according
1035 // to the values set in 'ValueCols'.
1036 list<string> ColFields = [];
1038 // Values for the fields/attributes listed in 'ColFields'.
1039 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction
1040 // that models this relation) should be non-predicated.
1041 // In the example above, 'Add' is the key instruction.
1042 list<string> KeyCol = [];
1044 // List of values for the fields/attributes listed in 'ColFields', one for
1045 // each column in the relation table.
1047 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the
1048 // table. First column requires all the instructions to have predSense
1049 // set to 'true' and second column requires it to be 'false'.
1050 list<list<string> > ValueCols = [];
1053 //===----------------------------------------------------------------------===//
1054 // Pull in the common support for calling conventions.
1056 include "llvm/Target/TargetCallingConv.td"
1058 //===----------------------------------------------------------------------===//
1059 // Pull in the common support for DAG isel generation.
1061 include "llvm/Target/TargetSelectionDAG.td"