1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
26 string Namespace = "";
29 // Register - You should define one instance of this class for each register
30 // in the target machine. String n will become the "name" of the register.
31 class Register<string n> {
32 string Namespace = "";
35 // Aliases - A list of registers that this register overlaps with. A read or
36 // modification of this register can potentially read or modify the aliased
38 list<Register> Aliases = [];
40 // SubRegs - A list of registers that are parts of this register. Note these
41 // are "immediate" sub-registers and the registers within the list do not
42 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
44 list<Register> SubRegs = [];
46 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
47 // to address it. Sub-sub-register indices are automatically inherited from
49 list<SubRegIndex> SubRegIndices = [];
51 // CompositeIndices - Specify subreg indices that don't correspond directly to
52 // a register in SubRegs and are not inherited. The following formats are
55 // (a) Identity - Reg:a == Reg
56 // (a b) Alias - Reg:a == Reg:b
57 // (a b,c) Composite - Reg:a == (Reg:b):c
59 // This can be used to disambiguate a sub-sub-register that exists in more
60 // than one subregister and other weird stuff.
61 list<dag> CompositeIndices = [];
63 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
64 // These values can be determined by locating the <target>.h file in the
65 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
66 // order of these names correspond to the enumeration used by gcc. A value of
67 // -1 indicates that the gcc number is undefined and -2 that register number
68 // is invalid for this mode/flavour.
69 list<int> DwarfNumbers = [];
71 // CostPerUse - Additional cost of instructions using this register compared
72 // to other registers in its class. The register allocator will try to
73 // minimize the number of instructions using a register with a CostPerUse.
74 // This is used by the x86-64 and ARM Thumb targets where some registers
75 // require larger instruction encodings.
79 // RegisterWithSubRegs - This can be used to define instances of Register which
80 // need to specify sub-registers.
81 // List "subregs" specifies which registers are sub-registers to this one. This
82 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
83 // This allows the code generator to be careful not to put two values with
84 // overlapping live ranges into registers which alias.
85 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
86 let SubRegs = subregs;
89 // RegisterClass - Now that all of the registers are defined, and aliases
90 // between registers are defined, specify which registers belong to which
91 // register classes. This also defines the default allocation order of
92 // registers by register allocators.
94 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
95 list<Register> regList> {
96 string Namespace = namespace;
98 // RegType - Specify the list ValueType of the registers in this register
99 // class. Note that all registers in a register class must have the same
100 // ValueTypes. This is a list because some targets permit storing different
101 // types in same register, for example vector values with 128-bit total size,
102 // but different count/size of items, like SSE on x86.
104 list<ValueType> RegTypes = regTypes;
106 // Size - Specify the spill size in bits of the registers. A default value of
107 // zero lets tablgen pick an appropriate size.
110 // Alignment - Specify the alignment required of the registers when they are
111 // stored or loaded to memory.
113 int Alignment = alignment;
115 // CopyCost - This value is used to specify the cost of copying a value
116 // between two registers in this register class. The default value is one
117 // meaning it takes a single instruction to perform the copying. A negative
118 // value means copying is extremely expensive or impossible.
121 // MemberList - Specify which registers are in this class. If the
122 // allocation_order_* method are not specified, this also defines the order of
123 // allocation used by the register allocator.
125 list<Register> MemberList = regList;
127 // SubRegClasses - Specify the register class of subregisters as a list of
128 // dags: (RegClass SubRegIndex, SubRegindex, ...)
129 list<dag> SubRegClasses = [];
131 // isAllocatable - Specify that the register class can be used for virtual
132 // registers and register allocation. Some register classes are only used to
133 // model instruction operand constraints, and should have isAllocatable = 0.
134 bit isAllocatable = 1;
136 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
137 // code into a generated register class. The normal usage of this is to
138 // overload virtual methods.
139 code MethodProtos = [{}];
140 code MethodBodies = [{}];
144 //===----------------------------------------------------------------------===//
145 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
146 // to the register numbering used by gcc and gdb. These values are used by a
147 // debug information writer to describe where values may be located during
149 class DwarfRegNum<list<int> Numbers> {
150 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
151 // These values can be determined by locating the <target>.h file in the
152 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
153 // order of these names correspond to the enumeration used by gcc. A value of
154 // -1 indicates that the gcc number is undefined and -2 that register number
155 // is invalid for this mode/flavour.
156 list<int> DwarfNumbers = Numbers;
159 // DwarfRegAlias - This class declares that a given register uses the same dwarf
160 // numbers as another one. This is useful for making it clear that the two
161 // registers do have the same number. It also lets us build a mapping
162 // from dwarf register number to llvm register.
163 class DwarfRegAlias<Register reg> {
164 Register DwarfAlias = reg;
167 //===----------------------------------------------------------------------===//
168 // Pull in the common support for scheduling
170 include "llvm/Target/TargetSchedule.td"
172 class Predicate; // Forward def
174 //===----------------------------------------------------------------------===//
175 // Instruction set description - These classes correspond to the C++ classes in
176 // the Target/TargetInstrInfo.h file.
179 string Namespace = "";
181 dag OutOperandList; // An dag containing the MI def operand list.
182 dag InOperandList; // An dag containing the MI use operand list.
183 string AsmString = ""; // The .s format to print the instruction with.
185 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
186 // otherwise, uninitialized.
189 // The follow state will eventually be inferred automatically from the
190 // instruction pattern.
192 list<Register> Uses = []; // Default to using no non-operand registers
193 list<Register> Defs = []; // Default to modifying no non-operand registers
195 // Predicates - List of predicates which will be turned into isel matching
197 list<Predicate> Predicates = [];
202 // Added complexity passed onto matching pattern.
203 int AddedComplexity = 0;
205 // These bits capture information about the high-level semantics of the
207 bit isReturn = 0; // Is this instruction a return instruction?
208 bit isBranch = 0; // Is this instruction a branch instruction?
209 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
210 bit isCompare = 0; // Is this instruction a comparison instruction?
211 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
212 bit isBitcast = 0; // Is this instruction a bitcast instruction?
213 bit isBarrier = 0; // Can control flow fall through this instruction?
214 bit isCall = 0; // Is this instruction a call instruction?
215 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
216 bit mayLoad = 0; // Is it possible for this inst to read memory?
217 bit mayStore = 0; // Is it possible for this inst to write memory?
218 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
219 bit isCommutable = 0; // Is this 3 operand instruction commutable?
220 bit isTerminator = 0; // Is this part of the terminator for a basic block?
221 bit isReMaterializable = 0; // Is this instruction re-materializable?
222 bit isPredicable = 0; // Is this instruction predicable?
223 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
224 bit usesCustomInserter = 0; // Pseudo instr needing special help.
225 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
226 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
227 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
228 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
229 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
231 // Side effect flags - When set, the flags have these meanings:
233 // hasSideEffects - The instruction has side effects that are not
234 // captured by any operands of the instruction or other flags.
236 // neverHasSideEffects - Set on an instruction with no pattern if it has no
238 bit hasSideEffects = 0;
239 bit neverHasSideEffects = 0;
241 // Is this instruction a "real" instruction (with a distinct machine
242 // encoding), or is it a pseudo instruction used for codegen modeling
244 bit isCodeGenOnly = 0;
246 // Is this instruction a pseudo instruction for use by the assembler parser.
247 bit isAsmParserOnly = 0;
249 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
251 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
253 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
254 /// be encoded into the output machineinstr.
255 string DisableEncoding = "";
257 string PostEncoderMethod = "";
258 string DecoderMethod = "";
260 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
261 bits<64> TSFlags = 0;
263 ///@name Assembler Parser Support
266 string AsmMatchConverter = "";
271 /// Predicates - These are extra conditionals which are turned into instruction
272 /// selector matching code. Currently each predicate is just a string.
273 class Predicate<string cond> {
274 string CondString = cond;
276 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
277 /// matcher, this is true. Targets should set this by inheriting their
278 /// feature from the AssemblerPredicate class in addition to Predicate.
279 bit AssemblerMatcherPredicate = 0;
282 /// NoHonorSignDependentRounding - This predicate is true if support for
283 /// sign-dependent-rounding is not enabled.
284 def NoHonorSignDependentRounding
285 : Predicate<"!HonorSignDependentRoundingFPMath()">;
287 class Requires<list<Predicate> preds> {
288 list<Predicate> Predicates = preds;
291 /// ops definition - This is just a simple marker used to identify the operand
292 /// list for an instruction. outs and ins are identical both syntactically and
293 /// semanticallyr; they are used to define def operands and use operands to
294 /// improve readibility. This should be used like this:
295 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
300 /// variable_ops definition - Mark this instruction as taking a variable number
305 /// PointerLikeRegClass - Values that are designed to have pointer width are
306 /// derived from this. TableGen treats the register class as having a symbolic
307 /// type that it doesn't know, and resolves the actual regclass to use by using
308 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
309 class PointerLikeRegClass<int Kind> {
310 int RegClassKind = Kind;
314 /// ptr_rc definition - Mark this operand as being a pointer value whose
315 /// register class is resolved dynamically via a callback to TargetInstrInfo.
316 /// FIXME: We should probably change this to a class which contain a list of
317 /// flags. But currently we have but one flag.
318 def ptr_rc : PointerLikeRegClass<0>;
320 /// unknown definition - Mark this operand as being of unknown type, causing
321 /// it to be resolved by inference in the context it is used.
324 /// AsmOperandClass - Representation for the kinds of operands which the target
325 /// specific parser can create and the assembly matcher may need to distinguish.
327 /// Operand classes are used to define the order in which instructions are
328 /// matched, to ensure that the instruction which gets matched for any
329 /// particular list of operands is deterministic.
331 /// The target specific parser must be able to classify a parsed operand into a
332 /// unique class which does not partially overlap with any other classes. It can
333 /// match a subset of some other class, in which case the super class field
334 /// should be defined.
335 class AsmOperandClass {
336 /// The name to use for this class, which should be usable as an enum value.
339 /// The super classes of this operand.
340 list<AsmOperandClass> SuperClasses = [];
342 /// The name of the method on the target specific operand to call to test
343 /// whether the operand is an instance of this class. If not set, this will
344 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
345 /// signature should be:
346 /// bool isFoo() const;
347 string PredicateMethod = ?;
349 /// The name of the method on the target specific operand to call to add the
350 /// target specific operand to an MCInst. If not set, this will default to
351 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
352 /// signature should be:
353 /// void addFooOperands(MCInst &Inst, unsigned N) const;
354 string RenderMethod = ?;
356 /// The name of the method on the target specific operand to call to custom
357 /// handle the operand parsing. This is useful when the operands do not relate
358 /// to immediates or registers and are very instruction specific (as flags to
359 /// set in a processor register, coprocessor number, ...).
360 string ParserMethod = ?;
363 def ImmAsmOperand : AsmOperandClass {
367 /// Operand Types - These provide the built-in operand types that may be used
368 /// by a target. Targets can optionally provide their own operand types as
369 /// needed, though this should not be needed for RISC targets.
370 class Operand<ValueType ty> {
372 string PrintMethod = "printOperand";
373 string EncoderMethod = "";
374 string DecoderMethod = "";
375 string AsmOperandLowerMethod = ?;
376 dag MIOperandInfo = (ops);
378 // ParserMatchClass - The "match class" that operands of this type fit
379 // in. Match classes are used to define the order in which instructions are
380 // match, to ensure that which instructions gets matched is deterministic.
382 // The target specific parser must be able to classify an parsed operand into
383 // a unique class, which does not partially overlap with any other classes. It
384 // can match a subset of some other class, in which case the AsmOperandClass
385 // should declare the other operand as one of its super classes.
386 AsmOperandClass ParserMatchClass = ImmAsmOperand;
389 def i1imm : Operand<i1>;
390 def i8imm : Operand<i8>;
391 def i16imm : Operand<i16>;
392 def i32imm : Operand<i32>;
393 def i64imm : Operand<i64>;
395 def f32imm : Operand<f32>;
396 def f64imm : Operand<f64>;
398 /// zero_reg definition - Special node to stand for the zero register.
402 /// PredicateOperand - This can be used to define a predicate operand for an
403 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
404 /// AlwaysVal specifies the value of this predicate when set to "always
406 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
408 let MIOperandInfo = OpTypes;
409 dag DefaultOps = AlwaysVal;
412 /// OptionalDefOperand - This is used to define a optional definition operand
413 /// for an instruction. DefaultOps is the register the operand represents if
414 /// none is supplied, e.g. zero_reg.
415 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
417 let MIOperandInfo = OpTypes;
418 dag DefaultOps = defaultops;
422 // InstrInfo - This class should only be instantiated once to provide parameters
423 // which are global to the target machine.
426 // Target can specify its instructions in either big or little-endian formats.
427 // For instance, while both Sparc and PowerPC are big-endian platforms, the
428 // Sparc manual specifies its instructions in the format [31..0] (big), while
429 // PowerPC specifies them using the format [0..31] (little).
430 bit isLittleEndianEncoding = 0;
433 // Standard Pseudo Instructions.
434 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
435 // Only these instructions are allowed in the TargetOpcode namespace.
436 let isCodeGenOnly = 1, Namespace = "TargetOpcode" in {
437 def PHI : Instruction {
438 let OutOperandList = (outs);
439 let InOperandList = (ins variable_ops);
440 let AsmString = "PHINODE";
442 def INLINEASM : Instruction {
443 let OutOperandList = (outs);
444 let InOperandList = (ins variable_ops);
446 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
448 def PROLOG_LABEL : Instruction {
449 let OutOperandList = (outs);
450 let InOperandList = (ins i32imm:$id);
453 let isNotDuplicable = 1;
455 def EH_LABEL : Instruction {
456 let OutOperandList = (outs);
457 let InOperandList = (ins i32imm:$id);
460 let isNotDuplicable = 1;
462 def GC_LABEL : Instruction {
463 let OutOperandList = (outs);
464 let InOperandList = (ins i32imm:$id);
467 let isNotDuplicable = 1;
469 def KILL : Instruction {
470 let OutOperandList = (outs);
471 let InOperandList = (ins variable_ops);
473 let neverHasSideEffects = 1;
475 def EXTRACT_SUBREG : Instruction {
476 let OutOperandList = (outs unknown:$dst);
477 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
479 let neverHasSideEffects = 1;
481 def INSERT_SUBREG : Instruction {
482 let OutOperandList = (outs unknown:$dst);
483 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
485 let neverHasSideEffects = 1;
486 let Constraints = "$supersrc = $dst";
488 def IMPLICIT_DEF : Instruction {
489 let OutOperandList = (outs unknown:$dst);
490 let InOperandList = (ins);
492 let neverHasSideEffects = 1;
493 let isReMaterializable = 1;
494 let isAsCheapAsAMove = 1;
496 def SUBREG_TO_REG : Instruction {
497 let OutOperandList = (outs unknown:$dst);
498 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
500 let neverHasSideEffects = 1;
502 def COPY_TO_REGCLASS : Instruction {
503 let OutOperandList = (outs unknown:$dst);
504 let InOperandList = (ins unknown:$src, i32imm:$regclass);
506 let neverHasSideEffects = 1;
507 let isAsCheapAsAMove = 1;
509 def DBG_VALUE : Instruction {
510 let OutOperandList = (outs);
511 let InOperandList = (ins variable_ops);
512 let AsmString = "DBG_VALUE";
513 let neverHasSideEffects = 1;
515 def REG_SEQUENCE : Instruction {
516 let OutOperandList = (outs unknown:$dst);
517 let InOperandList = (ins variable_ops);
519 let neverHasSideEffects = 1;
520 let isAsCheapAsAMove = 1;
522 def COPY : Instruction {
523 let OutOperandList = (outs unknown:$dst);
524 let InOperandList = (ins unknown:$src);
526 let neverHasSideEffects = 1;
527 let isAsCheapAsAMove = 1;
531 //===----------------------------------------------------------------------===//
532 // AsmParser - This class can be implemented by targets that wish to implement
535 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
536 // syntax on X86 for example).
539 // AsmParserClassName - This specifies the suffix to use for the asmparser
540 // class. Generated AsmParser classes are always prefixed with the target
542 string AsmParserClassName = "AsmParser";
544 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
545 // function of the AsmParser class to call on every matched instruction.
546 // This can be used to perform target specific instruction post-processing.
547 string AsmParserInstCleanup = "";
549 // Variant - AsmParsers can be of multiple different variants. Variants are
550 // used to support targets that need to parser multiple formats for the
551 // assembly language.
554 // CommentDelimiter - If given, the delimiter string used to recognize
555 // comments which are hard coded in the .td assembler strings for individual
557 string CommentDelimiter = "";
559 // RegisterPrefix - If given, the token prefix which indicates a register
560 // token. This is used by the matcher to automatically recognize hard coded
561 // register tokens as constrained registers, instead of tokens, for the
562 // purposes of matching.
563 string RegisterPrefix = "";
565 def DefaultAsmParser : AsmParser;
567 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
568 /// matches instructions and aliases.
569 class AssemblerPredicate {
570 bit AssemblerMatcherPredicate = 1;
575 /// MnemonicAlias - This class allows targets to define assembler mnemonic
576 /// aliases. This should be used when all forms of one mnemonic are accepted
577 /// with a different mnemonic. For example, X86 allows:
578 /// sal %al, 1 -> shl %al, 1
579 /// sal %ax, %cl -> shl %ax, %cl
580 /// sal %eax, %cl -> shl %eax, %cl
581 /// etc. Though "sal" is accepted with many forms, all of them are directly
582 /// translated to a shl, so it can be handled with (in the case of X86, it
583 /// actually has one for each suffix as well):
584 /// def : MnemonicAlias<"sal", "shl">;
586 /// Mnemonic aliases are mapped before any other translation in the match phase,
587 /// and do allow Requires predicates, e.g.:
589 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
590 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
592 class MnemonicAlias<string From, string To> {
593 string FromMnemonic = From;
594 string ToMnemonic = To;
596 // Predicates - Predicates that must be true for this remapping to happen.
597 list<Predicate> Predicates = [];
600 /// InstAlias - This defines an alternate assembly syntax that is allowed to
601 /// match an instruction that has a different (more canonical) assembly
603 class InstAlias<string Asm, dag Result, bit Emit = 0b1> {
604 string AsmString = Asm; // The .s format to match the instruction with.
605 dag ResultInst = Result; // The MCInst to generate.
606 bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
608 // Predicates - Predicates that must be true for this to match.
609 list<Predicate> Predicates = [];
612 //===----------------------------------------------------------------------===//
613 // AsmWriter - This class can be implemented by targets that need to customize
614 // the format of the .s file writer.
616 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
617 // on X86 for example).
620 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
621 // class. Generated AsmWriter classes are always prefixed with the target
623 string AsmWriterClassName = "AsmPrinter";
625 // Variant - AsmWriters can be of multiple different variants. Variants are
626 // used to support targets that need to emit assembly code in ways that are
627 // mostly the same for different targets, but have minor differences in
628 // syntax. If the asmstring contains {|} characters in them, this integer
629 // will specify which alternative to use. For example "{x|y|z}" with Variant
630 // == 1, will expand to "y".
634 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
635 // layout, the asmwriter can actually generate output in this columns (in
636 // verbose-asm mode). These two values indicate the width of the first column
637 // (the "opcode" area) and the width to reserve for subsequent operands. When
638 // verbose asm mode is enabled, operands will be indented to respect this.
639 int FirstOperandColumn = -1;
641 // OperandSpacing - Space between operand columns.
642 int OperandSpacing = -1;
644 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
645 // generation of the printInstruction() method. For MC printers, it takes
646 // an MCInstr* operand, otherwise it takes a MachineInstr*.
647 bit isMCAsmWriter = 0;
649 def DefaultAsmWriter : AsmWriter;
652 //===----------------------------------------------------------------------===//
653 // Target - This class contains the "global" target information
656 // InstructionSet - Instruction set description for this target.
657 InstrInfo InstructionSet;
659 // AssemblyParsers - The AsmParser instances available for this target.
660 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
662 // AssemblyWriters - The AsmWriter instances available for this target.
663 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
666 //===----------------------------------------------------------------------===//
667 // SubtargetFeature - A characteristic of the chip set.
669 class SubtargetFeature<string n, string a, string v, string d,
670 list<SubtargetFeature> i = []> {
671 // Name - Feature name. Used by command line (-mattr=) to determine the
672 // appropriate target chip.
676 // Attribute - Attribute to be set by feature.
678 string Attribute = a;
680 // Value - Value the attribute to be set to by feature.
684 // Desc - Feature description. Used by command line (-mattr=) to display help
689 // Implies - Features that this feature implies are present. If one of those
690 // features isn't set, then this one shouldn't be set either.
692 list<SubtargetFeature> Implies = i;
695 //===----------------------------------------------------------------------===//
696 // Processor chip sets - These values represent each of the chip sets supported
697 // by the scheduler. Each Processor definition requires corresponding
698 // instruction itineraries.
700 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
701 // Name - Chip set name. Used by command line (-mcpu=) to determine the
702 // appropriate target chip.
706 // ProcItin - The scheduling information for the target processor.
708 ProcessorItineraries ProcItin = pi;
710 // Features - list of
711 list<SubtargetFeature> Features = f;
714 //===----------------------------------------------------------------------===//
715 // Pull in the common support for calling conventions.
717 include "llvm/Target/TargetCallingConv.td"
719 //===----------------------------------------------------------------------===//
720 // Pull in the common support for DAG isel generation.
722 include "llvm/Target/TargetSelectionDAG.td"