1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
26 string Namespace = "";
29 // RegAltNameIndex - The alternate name set to use for register operands of
30 // this register class when printing.
31 class RegAltNameIndex {
32 string Namespace = "";
34 def NoRegAltName : RegAltNameIndex;
36 // Register - You should define one instance of this class for each register
37 // in the target machine. String n will become the "name" of the register.
38 class Register<string n, list<string> altNames = []> {
39 string Namespace = "";
41 list<string> AltNames = altNames;
43 // Aliases - A list of registers that this register overlaps with. A read or
44 // modification of this register can potentially read or modify the aliased
46 list<Register> Aliases = [];
48 // SubRegs - A list of registers that are parts of this register. Note these
49 // are "immediate" sub-registers and the registers within the list do not
50 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
52 list<Register> SubRegs = [];
54 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
55 // to address it. Sub-sub-register indices are automatically inherited from
57 list<SubRegIndex> SubRegIndices = [];
59 // RegAltNameIndices - The alternate name indices which are valid for this
61 list<RegAltNameIndex> RegAltNameIndices = [];
63 // CompositeIndices - Specify subreg indices that don't correspond directly to
64 // a register in SubRegs and are not inherited. The following formats are
67 // (a) Identity - Reg:a == Reg
68 // (a b) Alias - Reg:a == Reg:b
69 // (a b,c) Composite - Reg:a == (Reg:b):c
71 // This can be used to disambiguate a sub-sub-register that exists in more
72 // than one subregister and other weird stuff.
73 list<dag> CompositeIndices = [];
75 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
76 // These values can be determined by locating the <target>.h file in the
77 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
78 // order of these names correspond to the enumeration used by gcc. A value of
79 // -1 indicates that the gcc number is undefined and -2 that register number
80 // is invalid for this mode/flavour.
81 list<int> DwarfNumbers = [];
83 // CostPerUse - Additional cost of instructions using this register compared
84 // to other registers in its class. The register allocator will try to
85 // minimize the number of instructions using a register with a CostPerUse.
86 // This is used by the x86-64 and ARM Thumb targets where some registers
87 // require larger instruction encodings.
90 // CoveredBySubRegs - When this bit is set, the value of this register is
91 // completely determined by the value of its sub-registers. For example, the
92 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
93 // covered by its sub-register AX.
94 bit CoveredBySubRegs = 0;
97 // RegisterWithSubRegs - This can be used to define instances of Register which
98 // need to specify sub-registers.
99 // List "subregs" specifies which registers are sub-registers to this one. This
100 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
101 // This allows the code generator to be careful not to put two values with
102 // overlapping live ranges into registers which alias.
103 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
104 let SubRegs = subregs;
107 // RegisterClass - Now that all of the registers are defined, and aliases
108 // between registers are defined, specify which registers belong to which
109 // register classes. This also defines the default allocation order of
110 // registers by register allocators.
112 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
113 dag regList, RegAltNameIndex idx = NoRegAltName> {
114 string Namespace = namespace;
116 // RegType - Specify the list ValueType of the registers in this register
117 // class. Note that all registers in a register class must have the same
118 // ValueTypes. This is a list because some targets permit storing different
119 // types in same register, for example vector values with 128-bit total size,
120 // but different count/size of items, like SSE on x86.
122 list<ValueType> RegTypes = regTypes;
124 // Size - Specify the spill size in bits of the registers. A default value of
125 // zero lets tablgen pick an appropriate size.
128 // Alignment - Specify the alignment required of the registers when they are
129 // stored or loaded to memory.
131 int Alignment = alignment;
133 // CopyCost - This value is used to specify the cost of copying a value
134 // between two registers in this register class. The default value is one
135 // meaning it takes a single instruction to perform the copying. A negative
136 // value means copying is extremely expensive or impossible.
139 // MemberList - Specify which registers are in this class. If the
140 // allocation_order_* method are not specified, this also defines the order of
141 // allocation used by the register allocator.
143 dag MemberList = regList;
145 // AltNameIndex - The alternate register name to use when printing operands
146 // of this register class. Every register in the register class must have
147 // a valid alternate name for the given index.
148 RegAltNameIndex altNameIndex = idx;
150 // SubRegClasses - Specify the register class of subregisters as a list of
151 // dags: (RegClass SubRegIndex, SubRegindex, ...)
152 list<dag> SubRegClasses = [];
154 // isAllocatable - Specify that the register class can be used for virtual
155 // registers and register allocation. Some register classes are only used to
156 // model instruction operand constraints, and should have isAllocatable = 0.
157 bit isAllocatable = 1;
159 // AltOrders - List of alternative allocation orders. The default order is
160 // MemberList itself, and that is good enough for most targets since the
161 // register allocators automatically remove reserved registers and move
162 // callee-saved registers to the end.
163 list<dag> AltOrders = [];
165 // AltOrderSelect - The body of a function that selects the allocation order
166 // to use in a given machine function. The code will be inserted in a
167 // function like this:
169 // static inline unsigned f(const MachineFunction &MF) { ... }
171 // The function should return 0 to select the default order defined by
172 // MemberList, 1 to select the first AltOrders entry and so on.
173 code AltOrderSelect = [{}];
176 // The memberList in a RegisterClass is a dag of set operations. TableGen
177 // evaluates these set operations and expand them into register lists. These
178 // are the most common operation, see test/TableGen/SetTheory.td for more
179 // examples of what is possible:
181 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
182 // register class, or a sub-expression. This is also the way to simply list
185 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
187 // (and GPR, CSR) - Set intersection. All registers from the first set that are
188 // also in the second set.
190 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
191 // numbered registers.
193 // (shl GPR, 4) - Remove the first N elements.
195 // (trunc GPR, 4) - Truncate after the first N elements.
197 // (rotl GPR, 1) - Rotate N places to the left.
199 // (rotr GPR, 1) - Rotate N places to the right.
201 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
203 // (interleave A, B, ...) - Interleave the elements from each argument list.
205 // All of these operators work on ordered sets, not lists. That means
206 // duplicates are removed from sub-expressions.
208 // Set operators. The rest is defined in TargetSelectionDAG.td.
213 // RegisterTuples - Automatically generate super-registers by forming tuples of
214 // sub-registers. This is useful for modeling register sequence constraints
215 // with pseudo-registers that are larger than the architectural registers.
217 // The sub-register lists are zipped together:
219 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
221 // Generates the same registers as:
223 // let SubRegIndices = [sube, subo] in {
224 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
225 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
228 // The generated pseudo-registers inherit super-classes and fields from their
229 // first sub-register. Most fields from the Register class are inferred, and
230 // the AsmName and Dwarf numbers are cleared.
232 // RegisterTuples instances can be used in other set operations to form
233 // register classes and so on. This is the only way of using the generated
235 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
236 // SubRegs - N lists of registers to be zipped up. Super-registers are
237 // synthesized from the first element of each SubRegs list, the second
238 // element and so on.
239 list<dag> SubRegs = Regs;
241 // SubRegIndices - N SubRegIndex instances. This provides the names of the
242 // sub-registers in the synthesized super-registers.
243 list<SubRegIndex> SubRegIndices = Indices;
245 // Compose sub-register indices like in a normal Register.
246 list<dag> CompositeIndices = [];
250 //===----------------------------------------------------------------------===//
251 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
252 // to the register numbering used by gcc and gdb. These values are used by a
253 // debug information writer to describe where values may be located during
255 class DwarfRegNum<list<int> Numbers> {
256 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
257 // These values can be determined by locating the <target>.h file in the
258 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
259 // order of these names correspond to the enumeration used by gcc. A value of
260 // -1 indicates that the gcc number is undefined and -2 that register number
261 // is invalid for this mode/flavour.
262 list<int> DwarfNumbers = Numbers;
265 // DwarfRegAlias - This class declares that a given register uses the same dwarf
266 // numbers as another one. This is useful for making it clear that the two
267 // registers do have the same number. It also lets us build a mapping
268 // from dwarf register number to llvm register.
269 class DwarfRegAlias<Register reg> {
270 Register DwarfAlias = reg;
273 //===----------------------------------------------------------------------===//
274 // Pull in the common support for scheduling
276 include "llvm/Target/TargetSchedule.td"
278 class Predicate; // Forward def
280 //===----------------------------------------------------------------------===//
281 // Instruction set description - These classes correspond to the C++ classes in
282 // the Target/TargetInstrInfo.h file.
285 string Namespace = "";
287 dag OutOperandList; // An dag containing the MI def operand list.
288 dag InOperandList; // An dag containing the MI use operand list.
289 string AsmString = ""; // The .s format to print the instruction with.
291 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
292 // otherwise, uninitialized.
295 // The follow state will eventually be inferred automatically from the
296 // instruction pattern.
298 list<Register> Uses = []; // Default to using no non-operand registers
299 list<Register> Defs = []; // Default to modifying no non-operand registers
301 // Predicates - List of predicates which will be turned into isel matching
303 list<Predicate> Predicates = [];
305 // Size - Size of encoded instruction, or zero if the size cannot be determined
309 // DecoderNamespace - The "namespace" in which this instruction exists, on
310 // targets like ARM which multiple ISA namespaces exist.
311 string DecoderNamespace = "";
313 // Code size, for instruction selection.
314 // FIXME: What does this actually mean?
317 // Added complexity passed onto matching pattern.
318 int AddedComplexity = 0;
320 // These bits capture information about the high-level semantics of the
322 bit isReturn = 0; // Is this instruction a return instruction?
323 bit isBranch = 0; // Is this instruction a branch instruction?
324 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
325 bit isCompare = 0; // Is this instruction a comparison instruction?
326 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
327 bit isBitcast = 0; // Is this instruction a bitcast instruction?
328 bit isBarrier = 0; // Can control flow fall through this instruction?
329 bit isCall = 0; // Is this instruction a call instruction?
330 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
331 bit mayLoad = 0; // Is it possible for this inst to read memory?
332 bit mayStore = 0; // Is it possible for this inst to write memory?
333 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
334 bit isCommutable = 0; // Is this 3 operand instruction commutable?
335 bit isTerminator = 0; // Is this part of the terminator for a basic block?
336 bit isReMaterializable = 0; // Is this instruction re-materializable?
337 bit isPredicable = 0; // Is this instruction predicable?
338 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
339 bit usesCustomInserter = 0; // Pseudo instr needing special help.
340 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
341 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
342 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
343 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
344 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
345 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
346 bit isPseudo = 0; // Is this instruction a pseudo-instruction?
347 // If so, won't have encoding information for
348 // the [MC]CodeEmitter stuff.
350 // Side effect flags - When set, the flags have these meanings:
352 // hasSideEffects - The instruction has side effects that are not
353 // captured by any operands of the instruction or other flags.
355 // neverHasSideEffects - Set on an instruction with no pattern if it has no
357 bit hasSideEffects = 0;
358 bit neverHasSideEffects = 0;
360 // Is this instruction a "real" instruction (with a distinct machine
361 // encoding), or is it a pseudo instruction used for codegen modeling
363 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
364 // instructions can (and often do) still have encoding information
365 // associated with them. Once we've migrated all of them over to true
366 // pseudo-instructions that are lowered to real instructions prior to
367 // the printer/emitter, we can remove this attribute and just use isPseudo.
369 // The intended use is:
370 // isPseudo: Does not have encoding information and should be expanded,
371 // at the latest, during lowering to MCInst.
373 // isCodeGenOnly: Does have encoding information and can go through to the
374 // CodeEmitter unchanged, but duplicates a canonical instruction
375 // definition's encoding and should be ignored when constructing the
376 // assembler match tables.
377 bit isCodeGenOnly = 0;
379 // Is this instruction a pseudo instruction for use by the assembler parser.
380 bit isAsmParserOnly = 0;
382 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
384 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
386 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
387 /// be encoded into the output machineinstr.
388 string DisableEncoding = "";
390 string PostEncoderMethod = "";
391 string DecoderMethod = "";
393 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
394 bits<64> TSFlags = 0;
396 ///@name Assembler Parser Support
399 string AsmMatchConverter = "";
404 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
405 /// Which instruction it expands to and how the operands map from the
407 class PseudoInstExpansion<dag Result> {
408 dag ResultInst = Result; // The instruction to generate.
412 /// Predicates - These are extra conditionals which are turned into instruction
413 /// selector matching code. Currently each predicate is just a string.
414 class Predicate<string cond> {
415 string CondString = cond;
417 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
418 /// matcher, this is true. Targets should set this by inheriting their
419 /// feature from the AssemblerPredicate class in addition to Predicate.
420 bit AssemblerMatcherPredicate = 0;
422 /// AssemblerCondString - Name of the subtarget feature being tested used
423 /// as alternative condition string used for assembler matcher.
424 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
425 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
426 /// It can also list multiple features separated by ",".
427 /// e.g. "ModeThumb,FeatureThumb2" is translated to
428 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
429 string AssemblerCondString = "";
432 /// NoHonorSignDependentRounding - This predicate is true if support for
433 /// sign-dependent-rounding is not enabled.
434 def NoHonorSignDependentRounding
435 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
437 class Requires<list<Predicate> preds> {
438 list<Predicate> Predicates = preds;
441 /// ops definition - This is just a simple marker used to identify the operand
442 /// list for an instruction. outs and ins are identical both syntactically and
443 /// semanticallyr; they are used to define def operands and use operands to
444 /// improve readibility. This should be used like this:
445 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
450 /// variable_ops definition - Mark this instruction as taking a variable number
455 /// PointerLikeRegClass - Values that are designed to have pointer width are
456 /// derived from this. TableGen treats the register class as having a symbolic
457 /// type that it doesn't know, and resolves the actual regclass to use by using
458 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
459 class PointerLikeRegClass<int Kind> {
460 int RegClassKind = Kind;
464 /// ptr_rc definition - Mark this operand as being a pointer value whose
465 /// register class is resolved dynamically via a callback to TargetInstrInfo.
466 /// FIXME: We should probably change this to a class which contain a list of
467 /// flags. But currently we have but one flag.
468 def ptr_rc : PointerLikeRegClass<0>;
470 /// unknown definition - Mark this operand as being of unknown type, causing
471 /// it to be resolved by inference in the context it is used.
474 /// AsmOperandClass - Representation for the kinds of operands which the target
475 /// specific parser can create and the assembly matcher may need to distinguish.
477 /// Operand classes are used to define the order in which instructions are
478 /// matched, to ensure that the instruction which gets matched for any
479 /// particular list of operands is deterministic.
481 /// The target specific parser must be able to classify a parsed operand into a
482 /// unique class which does not partially overlap with any other classes. It can
483 /// match a subset of some other class, in which case the super class field
484 /// should be defined.
485 class AsmOperandClass {
486 /// The name to use for this class, which should be usable as an enum value.
489 /// The super classes of this operand.
490 list<AsmOperandClass> SuperClasses = [];
492 /// The name of the method on the target specific operand to call to test
493 /// whether the operand is an instance of this class. If not set, this will
494 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
495 /// signature should be:
496 /// bool isFoo() const;
497 string PredicateMethod = ?;
499 /// The name of the method on the target specific operand to call to add the
500 /// target specific operand to an MCInst. If not set, this will default to
501 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
502 /// signature should be:
503 /// void addFooOperands(MCInst &Inst, unsigned N) const;
504 string RenderMethod = ?;
506 /// The name of the method on the target specific operand to call to custom
507 /// handle the operand parsing. This is useful when the operands do not relate
508 /// to immediates or registers and are very instruction specific (as flags to
509 /// set in a processor register, coprocessor number, ...).
510 string ParserMethod = ?;
513 def ImmAsmOperand : AsmOperandClass {
517 /// Operand Types - These provide the built-in operand types that may be used
518 /// by a target. Targets can optionally provide their own operand types as
519 /// needed, though this should not be needed for RISC targets.
520 class Operand<ValueType ty> {
522 string PrintMethod = "printOperand";
523 string EncoderMethod = "";
524 string DecoderMethod = "";
525 string AsmOperandLowerMethod = ?;
526 string OperandType = "OPERAND_UNKNOWN";
527 dag MIOperandInfo = (ops);
529 // ParserMatchClass - The "match class" that operands of this type fit
530 // in. Match classes are used to define the order in which instructions are
531 // match, to ensure that which instructions gets matched is deterministic.
533 // The target specific parser must be able to classify an parsed operand into
534 // a unique class, which does not partially overlap with any other classes. It
535 // can match a subset of some other class, in which case the AsmOperandClass
536 // should declare the other operand as one of its super classes.
537 AsmOperandClass ParserMatchClass = ImmAsmOperand;
540 class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> {
541 // RegClass - The register class of the operand.
542 RegisterClass RegClass = regclass;
543 // PrintMethod - The target method to call to print register operands of
544 // this type. The method normally will just use an alt-name index to look
545 // up the name to print. Default to the generic printOperand().
546 string PrintMethod = pm;
547 // ParserMatchClass - The "match class" that operands of this type fit
548 // in. Match classes are used to define the order in which instructions are
549 // match, to ensure that which instructions gets matched is deterministic.
551 // The target specific parser must be able to classify an parsed operand into
552 // a unique class, which does not partially overlap with any other classes. It
553 // can match a subset of some other class, in which case the AsmOperandClass
554 // should declare the other operand as one of its super classes.
555 AsmOperandClass ParserMatchClass;
558 let OperandType = "OPERAND_IMMEDIATE" in {
559 def i1imm : Operand<i1>;
560 def i8imm : Operand<i8>;
561 def i16imm : Operand<i16>;
562 def i32imm : Operand<i32>;
563 def i64imm : Operand<i64>;
565 def f32imm : Operand<f32>;
566 def f64imm : Operand<f64>;
569 /// zero_reg definition - Special node to stand for the zero register.
573 /// PredicateOperand - This can be used to define a predicate operand for an
574 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
575 /// AlwaysVal specifies the value of this predicate when set to "always
577 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
579 let MIOperandInfo = OpTypes;
580 dag DefaultOps = AlwaysVal;
583 /// OptionalDefOperand - This is used to define a optional definition operand
584 /// for an instruction. DefaultOps is the register the operand represents if
585 /// none is supplied, e.g. zero_reg.
586 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
588 let MIOperandInfo = OpTypes;
589 dag DefaultOps = defaultops;
593 // InstrInfo - This class should only be instantiated once to provide parameters
594 // which are global to the target machine.
597 // Target can specify its instructions in either big or little-endian formats.
598 // For instance, while both Sparc and PowerPC are big-endian platforms, the
599 // Sparc manual specifies its instructions in the format [31..0] (big), while
600 // PowerPC specifies them using the format [0..31] (little).
601 bit isLittleEndianEncoding = 0;
604 // Standard Pseudo Instructions.
605 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
606 // Only these instructions are allowed in the TargetOpcode namespace.
607 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
608 def PHI : Instruction {
609 let OutOperandList = (outs);
610 let InOperandList = (ins variable_ops);
611 let AsmString = "PHINODE";
613 def INLINEASM : Instruction {
614 let OutOperandList = (outs);
615 let InOperandList = (ins variable_ops);
617 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
619 def PROLOG_LABEL : Instruction {
620 let OutOperandList = (outs);
621 let InOperandList = (ins i32imm:$id);
624 let isNotDuplicable = 1;
626 def EH_LABEL : Instruction {
627 let OutOperandList = (outs);
628 let InOperandList = (ins i32imm:$id);
631 let isNotDuplicable = 1;
633 def GC_LABEL : Instruction {
634 let OutOperandList = (outs);
635 let InOperandList = (ins i32imm:$id);
638 let isNotDuplicable = 1;
640 def KILL : Instruction {
641 let OutOperandList = (outs);
642 let InOperandList = (ins variable_ops);
644 let neverHasSideEffects = 1;
646 def EXTRACT_SUBREG : Instruction {
647 let OutOperandList = (outs unknown:$dst);
648 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
650 let neverHasSideEffects = 1;
652 def INSERT_SUBREG : Instruction {
653 let OutOperandList = (outs unknown:$dst);
654 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
656 let neverHasSideEffects = 1;
657 let Constraints = "$supersrc = $dst";
659 def IMPLICIT_DEF : Instruction {
660 let OutOperandList = (outs unknown:$dst);
661 let InOperandList = (ins);
663 let neverHasSideEffects = 1;
664 let isReMaterializable = 1;
665 let isAsCheapAsAMove = 1;
667 def SUBREG_TO_REG : Instruction {
668 let OutOperandList = (outs unknown:$dst);
669 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
671 let neverHasSideEffects = 1;
673 def COPY_TO_REGCLASS : Instruction {
674 let OutOperandList = (outs unknown:$dst);
675 let InOperandList = (ins unknown:$src, i32imm:$regclass);
677 let neverHasSideEffects = 1;
678 let isAsCheapAsAMove = 1;
680 def DBG_VALUE : Instruction {
681 let OutOperandList = (outs);
682 let InOperandList = (ins variable_ops);
683 let AsmString = "DBG_VALUE";
684 let neverHasSideEffects = 1;
686 def REG_SEQUENCE : Instruction {
687 let OutOperandList = (outs unknown:$dst);
688 let InOperandList = (ins variable_ops);
690 let neverHasSideEffects = 1;
691 let isAsCheapAsAMove = 1;
693 def COPY : Instruction {
694 let OutOperandList = (outs unknown:$dst);
695 let InOperandList = (ins unknown:$src);
697 let neverHasSideEffects = 1;
698 let isAsCheapAsAMove = 1;
700 def BUNDLE : Instruction {
701 let OutOperandList = (outs);
702 let InOperandList = (ins variable_ops);
703 let AsmString = "BUNDLE";
707 //===----------------------------------------------------------------------===//
708 // AsmParser - This class can be implemented by targets that wish to implement
711 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
712 // syntax on X86 for example).
715 // AsmParserClassName - This specifies the suffix to use for the asmparser
716 // class. Generated AsmParser classes are always prefixed with the target
718 string AsmParserClassName = "AsmParser";
720 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
721 // function of the AsmParser class to call on every matched instruction.
722 // This can be used to perform target specific instruction post-processing.
723 string AsmParserInstCleanup = "";
725 def DefaultAsmParser : AsmParser;
727 //===----------------------------------------------------------------------===//
728 // AsmParserVariant - Subtargets can have multiple different assembly parsers
729 // (e.g. AT&T vs Intel syntax on X86 for example). This class can be
730 // implemented by targets to describe such variants.
732 class AsmParserVariant {
733 // Variant - AsmParsers can be of multiple different variants. Variants are
734 // used to support targets that need to parser multiple formats for the
735 // assembly language.
738 // CommentDelimiter - If given, the delimiter string used to recognize
739 // comments which are hard coded in the .td assembler strings for individual
741 string CommentDelimiter = "";
743 // RegisterPrefix - If given, the token prefix which indicates a register
744 // token. This is used by the matcher to automatically recognize hard coded
745 // register tokens as constrained registers, instead of tokens, for the
746 // purposes of matching.
747 string RegisterPrefix = "";
749 def DefaultAsmParserVariant : AsmParserVariant;
751 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
752 /// matches instructions and aliases.
753 class AssemblerPredicate<string cond> {
754 bit AssemblerMatcherPredicate = 1;
755 string AssemblerCondString = cond;
758 /// TokenAlias - This class allows targets to define assembler token
759 /// operand aliases. That is, a token literal operand which is equivalent
760 /// to another, canonical, token literal. For example, ARM allows:
761 /// vmov.u32 s4, #0 -> vmov.i32, #0
762 /// 'u32' is a more specific designator for the 32-bit integer type specifier
763 /// and is legal for any instruction which accepts 'i32' as a datatype suffix.
764 /// def : TokenAlias<".u32", ".i32">;
766 /// This works by marking the match class of 'From' as a subclass of the
767 /// match class of 'To'.
768 class TokenAlias<string From, string To> {
769 string FromToken = From;
773 /// MnemonicAlias - This class allows targets to define assembler mnemonic
774 /// aliases. This should be used when all forms of one mnemonic are accepted
775 /// with a different mnemonic. For example, X86 allows:
776 /// sal %al, 1 -> shl %al, 1
777 /// sal %ax, %cl -> shl %ax, %cl
778 /// sal %eax, %cl -> shl %eax, %cl
779 /// etc. Though "sal" is accepted with many forms, all of them are directly
780 /// translated to a shl, so it can be handled with (in the case of X86, it
781 /// actually has one for each suffix as well):
782 /// def : MnemonicAlias<"sal", "shl">;
784 /// Mnemonic aliases are mapped before any other translation in the match phase,
785 /// and do allow Requires predicates, e.g.:
787 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
788 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
790 class MnemonicAlias<string From, string To> {
791 string FromMnemonic = From;
792 string ToMnemonic = To;
794 // Predicates - Predicates that must be true for this remapping to happen.
795 list<Predicate> Predicates = [];
798 /// InstAlias - This defines an alternate assembly syntax that is allowed to
799 /// match an instruction that has a different (more canonical) assembly
801 class InstAlias<string Asm, dag Result, bit Emit = 0b1> {
802 string AsmString = Asm; // The .s format to match the instruction with.
803 dag ResultInst = Result; // The MCInst to generate.
804 bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
806 // Predicates - Predicates that must be true for this to match.
807 list<Predicate> Predicates = [];
810 //===----------------------------------------------------------------------===//
811 // AsmWriter - This class can be implemented by targets that need to customize
812 // the format of the .s file writer.
814 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
815 // on X86 for example).
818 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
819 // class. Generated AsmWriter classes are always prefixed with the target
821 string AsmWriterClassName = "AsmPrinter";
823 // Variant - AsmWriters can be of multiple different variants. Variants are
824 // used to support targets that need to emit assembly code in ways that are
825 // mostly the same for different targets, but have minor differences in
826 // syntax. If the asmstring contains {|} characters in them, this integer
827 // will specify which alternative to use. For example "{x|y|z}" with Variant
828 // == 1, will expand to "y".
832 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
833 // layout, the asmwriter can actually generate output in this columns (in
834 // verbose-asm mode). These two values indicate the width of the first column
835 // (the "opcode" area) and the width to reserve for subsequent operands. When
836 // verbose asm mode is enabled, operands will be indented to respect this.
837 int FirstOperandColumn = -1;
839 // OperandSpacing - Space between operand columns.
840 int OperandSpacing = -1;
842 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
843 // generation of the printInstruction() method. For MC printers, it takes
844 // an MCInstr* operand, otherwise it takes a MachineInstr*.
845 bit isMCAsmWriter = 0;
847 def DefaultAsmWriter : AsmWriter;
850 //===----------------------------------------------------------------------===//
851 // Target - This class contains the "global" target information
854 // InstructionSet - Instruction set description for this target.
855 InstrInfo InstructionSet;
857 // AssemblyParsers - The AsmParser instances available for this target.
858 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
860 /// AssemblyParserVariants - The AsmParserVariant instances available for
862 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
864 // AssemblyWriters - The AsmWriter instances available for this target.
865 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
868 //===----------------------------------------------------------------------===//
869 // SubtargetFeature - A characteristic of the chip set.
871 class SubtargetFeature<string n, string a, string v, string d,
872 list<SubtargetFeature> i = []> {
873 // Name - Feature name. Used by command line (-mattr=) to determine the
874 // appropriate target chip.
878 // Attribute - Attribute to be set by feature.
880 string Attribute = a;
882 // Value - Value the attribute to be set to by feature.
886 // Desc - Feature description. Used by command line (-mattr=) to display help
891 // Implies - Features that this feature implies are present. If one of those
892 // features isn't set, then this one shouldn't be set either.
894 list<SubtargetFeature> Implies = i;
897 //===----------------------------------------------------------------------===//
898 // Processor chip sets - These values represent each of the chip sets supported
899 // by the scheduler. Each Processor definition requires corresponding
900 // instruction itineraries.
902 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
903 // Name - Chip set name. Used by command line (-mcpu=) to determine the
904 // appropriate target chip.
908 // ProcItin - The scheduling information for the target processor.
910 ProcessorItineraries ProcItin = pi;
912 // Features - list of
913 list<SubtargetFeature> Features = f;
916 //===----------------------------------------------------------------------===//
917 // Pull in the common support for calling conventions.
919 include "llvm/Target/TargetCallingConv.td"
921 //===----------------------------------------------------------------------===//
922 // Pull in the common support for DAG isel generation.
924 include "llvm/Target/TargetSelectionDAG.td"