1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
26 string Namespace = "";
29 // Register - You should define one instance of this class for each register
30 // in the target machine. String n will become the "name" of the register.
31 class Register<string n> {
32 string Namespace = "";
35 // SpillSize - If this value is set to a non-zero value, it is the size in
36 // bits of the spill slot required to hold this register. If this value is
37 // set to zero, the information is inferred from any register classes the
38 // register belongs to.
41 // SpillAlignment - This value is used to specify the alignment required for
42 // spilling the register. Like SpillSize, this should only be explicitly
43 // specified if the register is not in a register class.
44 int SpillAlignment = 0;
46 // Aliases - A list of registers that this register overlaps with. A read or
47 // modification of this register can potentially read or modify the aliased
49 list<Register> Aliases = [];
51 // SubRegs - A list of registers that are parts of this register. Note these
52 // are "immediate" sub-registers and the registers within the list do not
53 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
55 list<Register> SubRegs = [];
57 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
58 // to address it. Sub-sub-register indices are automatically inherited from
60 list<SubRegIndex> SubRegIndices = [];
62 // CompositeIndices - Specify subreg indices that don't correspond directly to
63 // a register in SubRegs and are not inherited. The following formats are
66 // (a) Identity - Reg:a == Reg
67 // (a b) Alias - Reg:a == Reg:b
68 // (a b,c) Composite - Reg:a == (Reg:b):c
70 // This can be used to disambiguate a sub-sub-register that exists in more
71 // than one subregister and other weird stuff.
72 list<dag> CompositeIndices = [];
74 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
75 // These values can be determined by locating the <target>.h file in the
76 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
77 // order of these names correspond to the enumeration used by gcc. A value of
78 // -1 indicates that the gcc number is undefined and -2 that register number
79 // is invalid for this mode/flavour.
80 list<int> DwarfNumbers = [];
83 // RegisterWithSubRegs - This can be used to define instances of Register which
84 // need to specify sub-registers.
85 // List "subregs" specifies which registers are sub-registers to this one. This
86 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
87 // This allows the code generator to be careful not to put two values with
88 // overlapping live ranges into registers which alias.
89 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
90 let SubRegs = subregs;
93 // RegisterClass - Now that all of the registers are defined, and aliases
94 // between registers are defined, specify which registers belong to which
95 // register classes. This also defines the default allocation order of
96 // registers by register allocators.
98 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
99 list<Register> regList> {
100 string Namespace = namespace;
102 // RegType - Specify the list ValueType of the registers in this register
103 // class. Note that all registers in a register class must have the same
104 // ValueTypes. This is a list because some targets permit storing different
105 // types in same register, for example vector values with 128-bit total size,
106 // but different count/size of items, like SSE on x86.
108 list<ValueType> RegTypes = regTypes;
110 // Size - Specify the spill size in bits of the registers. A default value of
111 // zero lets tablgen pick an appropriate size.
114 // Alignment - Specify the alignment required of the registers when they are
115 // stored or loaded to memory.
117 int Alignment = alignment;
119 // CopyCost - This value is used to specify the cost of copying a value
120 // between two registers in this register class. The default value is one
121 // meaning it takes a single instruction to perform the copying. A negative
122 // value means copying is extremely expensive or impossible.
125 // MemberList - Specify which registers are in this class. If the
126 // allocation_order_* method are not specified, this also defines the order of
127 // allocation used by the register allocator.
129 list<Register> MemberList = regList;
131 // SubRegClasses - Specify the register class of subregisters as a list of
132 // dags: (RegClass SubRegIndex, SubRegindex, ...)
133 list<dag> SubRegClasses = [];
135 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
136 // code into a generated register class. The normal usage of this is to
137 // overload virtual methods.
138 code MethodProtos = [{}];
139 code MethodBodies = [{}];
143 //===----------------------------------------------------------------------===//
144 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
145 // to the register numbering used by gcc and gdb. These values are used by a
146 // debug information writer to describe where values may be located during
148 class DwarfRegNum<list<int> Numbers> {
149 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
150 // These values can be determined by locating the <target>.h file in the
151 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
152 // order of these names correspond to the enumeration used by gcc. A value of
153 // -1 indicates that the gcc number is undefined and -2 that register number
154 // is invalid for this mode/flavour.
155 list<int> DwarfNumbers = Numbers;
158 //===----------------------------------------------------------------------===//
159 // Pull in the common support for scheduling
161 include "llvm/Target/TargetSchedule.td"
163 class Predicate; // Forward def
165 //===----------------------------------------------------------------------===//
166 // Instruction set description - These classes correspond to the C++ classes in
167 // the Target/TargetInstrInfo.h file.
170 string Namespace = "";
172 dag OutOperandList; // An dag containing the MI def operand list.
173 dag InOperandList; // An dag containing the MI use operand list.
174 string AsmString = ""; // The .s format to print the instruction with.
176 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
177 // otherwise, uninitialized.
180 // The follow state will eventually be inferred automatically from the
181 // instruction pattern.
183 list<Register> Uses = []; // Default to using no non-operand registers
184 list<Register> Defs = []; // Default to modifying no non-operand registers
186 // Predicates - List of predicates which will be turned into isel matching
188 list<Predicate> Predicates = [];
193 // Added complexity passed onto matching pattern.
194 int AddedComplexity = 0;
196 // These bits capture information about the high-level semantics of the
198 bit isReturn = 0; // Is this instruction a return instruction?
199 bit isBranch = 0; // Is this instruction a branch instruction?
200 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
201 bit isCompare = 0; // Is this instruction a comparison instruction?
202 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
203 bit isBarrier = 0; // Can control flow fall through this instruction?
204 bit isCall = 0; // Is this instruction a call instruction?
205 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
206 bit mayLoad = 0; // Is it possible for this inst to read memory?
207 bit mayStore = 0; // Is it possible for this inst to write memory?
208 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
209 bit isCommutable = 0; // Is this 3 operand instruction commutable?
210 bit isTerminator = 0; // Is this part of the terminator for a basic block?
211 bit isReMaterializable = 0; // Is this instruction re-materializable?
212 bit isPredicable = 0; // Is this instruction predicable?
213 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
214 bit usesCustomInserter = 0; // Pseudo instr needing special help.
215 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
216 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
217 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
218 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
219 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
221 // Side effect flags - When set, the flags have these meanings:
223 // hasSideEffects - The instruction has side effects that are not
224 // captured by any operands of the instruction or other flags.
226 // neverHasSideEffects - Set on an instruction with no pattern if it has no
228 bit hasSideEffects = 0;
229 bit neverHasSideEffects = 0;
231 // Is this instruction a "real" instruction (with a distinct machine
232 // encoding), or is it a pseudo instruction used for codegen modeling
234 bit isCodeGenOnly = 0;
236 // Is this instruction a pseudo instruction for use by the assembler parser.
237 bit isAsmParserOnly = 0;
239 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
241 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
243 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
244 /// be encoded into the output machineinstr.
245 string DisableEncoding = "";
247 string PostEncoderMethod = "";
249 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
250 bits<64> TSFlags = 0;
252 ///@name Assembler Parser Support
255 string AsmMatchConverter = "";
260 /// Predicates - These are extra conditionals which are turned into instruction
261 /// selector matching code. Currently each predicate is just a string.
262 class Predicate<string cond> {
263 string CondString = cond;
265 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
266 /// matcher, this is true. Targets should set this by inheriting their
267 /// feature from the AssemblerPredicate class in addition to Predicate.
268 bit AssemblerMatcherPredicate = 0;
271 /// NoHonorSignDependentRounding - This predicate is true if support for
272 /// sign-dependent-rounding is not enabled.
273 def NoHonorSignDependentRounding
274 : Predicate<"!HonorSignDependentRoundingFPMath()">;
276 class Requires<list<Predicate> preds> {
277 list<Predicate> Predicates = preds;
280 /// ops definition - This is just a simple marker used to identify the operand
281 /// list for an instruction. outs and ins are identical both syntactically and
282 /// semanticallyr; they are used to define def operands and use operands to
283 /// improve readibility. This should be used like this:
284 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
289 /// variable_ops definition - Mark this instruction as taking a variable number
294 /// PointerLikeRegClass - Values that are designed to have pointer width are
295 /// derived from this. TableGen treats the register class as having a symbolic
296 /// type that it doesn't know, and resolves the actual regclass to use by using
297 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
298 class PointerLikeRegClass<int Kind> {
299 int RegClassKind = Kind;
303 /// ptr_rc definition - Mark this operand as being a pointer value whose
304 /// register class is resolved dynamically via a callback to TargetInstrInfo.
305 /// FIXME: We should probably change this to a class which contain a list of
306 /// flags. But currently we have but one flag.
307 def ptr_rc : PointerLikeRegClass<0>;
309 /// unknown definition - Mark this operand as being of unknown type, causing
310 /// it to be resolved by inference in the context it is used.
313 /// AsmOperandClass - Representation for the kinds of operands which the target
314 /// specific parser can create and the assembly matcher may need to distinguish.
316 /// Operand classes are used to define the order in which instructions are
317 /// matched, to ensure that the instruction which gets matched for any
318 /// particular list of operands is deterministic.
320 /// The target specific parser must be able to classify a parsed operand into a
321 /// unique class which does not partially overlap with any other classes. It can
322 /// match a subset of some other class, in which case the super class field
323 /// should be defined.
324 class AsmOperandClass {
325 /// The name to use for this class, which should be usable as an enum value.
328 /// The super classes of this operand.
329 list<AsmOperandClass> SuperClasses = [];
331 /// The name of the method on the target specific operand to call to test
332 /// whether the operand is an instance of this class. If not set, this will
333 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
334 /// signature should be:
335 /// bool isFoo() const;
336 string PredicateMethod = ?;
338 /// The name of the method on the target specific operand to call to add the
339 /// target specific operand to an MCInst. If not set, this will default to
340 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
341 /// signature should be:
342 /// void addFooOperands(MCInst &Inst, unsigned N) const;
343 string RenderMethod = ?;
345 /// The name of the method on the target specific operand to call to custom
346 /// handle the operand parsing. This is useful when the operands do not relate
347 /// to immediates or registers and are very instruction specific (as flags to
348 /// set in a processor register, coprocessor number, ...).
349 string ParserMethod = ?;
352 def ImmAsmOperand : AsmOperandClass {
356 /// Operand Types - These provide the built-in operand types that may be used
357 /// by a target. Targets can optionally provide their own operand types as
358 /// needed, though this should not be needed for RISC targets.
359 class Operand<ValueType ty> {
361 string PrintMethod = "printOperand";
362 string EncoderMethod = "";
363 string AsmOperandLowerMethod = ?;
364 dag MIOperandInfo = (ops);
366 // ParserMatchClass - The "match class" that operands of this type fit
367 // in. Match classes are used to define the order in which instructions are
368 // match, to ensure that which instructions gets matched is deterministic.
370 // The target specific parser must be able to classify an parsed operand into
371 // a unique class, which does not partially overlap with any other classes. It
372 // can match a subset of some other class, in which case the AsmOperandClass
373 // should declare the other operand as one of its super classes.
374 AsmOperandClass ParserMatchClass = ImmAsmOperand;
377 def i1imm : Operand<i1>;
378 def i8imm : Operand<i8>;
379 def i16imm : Operand<i16>;
380 def i32imm : Operand<i32>;
381 def i64imm : Operand<i64>;
383 def f32imm : Operand<f32>;
384 def f64imm : Operand<f64>;
386 /// zero_reg definition - Special node to stand for the zero register.
390 /// PredicateOperand - This can be used to define a predicate operand for an
391 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
392 /// AlwaysVal specifies the value of this predicate when set to "always
394 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
396 let MIOperandInfo = OpTypes;
397 dag DefaultOps = AlwaysVal;
400 /// OptionalDefOperand - This is used to define a optional definition operand
401 /// for an instruction. DefaultOps is the register the operand represents if
402 /// none is supplied, e.g. zero_reg.
403 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
405 let MIOperandInfo = OpTypes;
406 dag DefaultOps = defaultops;
410 // InstrInfo - This class should only be instantiated once to provide parameters
411 // which are global to the target machine.
414 // Target can specify its instructions in either big or little-endian formats.
415 // For instance, while both Sparc and PowerPC are big-endian platforms, the
416 // Sparc manual specifies its instructions in the format [31..0] (big), while
417 // PowerPC specifies them using the format [0..31] (little).
418 bit isLittleEndianEncoding = 0;
421 // Standard Pseudo Instructions.
422 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
423 // Only these instructions are allowed in the TargetOpcode namespace.
424 let isCodeGenOnly = 1, Namespace = "TargetOpcode" in {
425 def PHI : Instruction {
426 let OutOperandList = (outs);
427 let InOperandList = (ins variable_ops);
428 let AsmString = "PHINODE";
430 def INLINEASM : Instruction {
431 let OutOperandList = (outs);
432 let InOperandList = (ins variable_ops);
434 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
436 def PROLOG_LABEL : Instruction {
437 let OutOperandList = (outs);
438 let InOperandList = (ins i32imm:$id);
441 let isNotDuplicable = 1;
443 def EH_LABEL : Instruction {
444 let OutOperandList = (outs);
445 let InOperandList = (ins i32imm:$id);
448 let isNotDuplicable = 1;
450 def GC_LABEL : Instruction {
451 let OutOperandList = (outs);
452 let InOperandList = (ins i32imm:$id);
455 let isNotDuplicable = 1;
457 def KILL : Instruction {
458 let OutOperandList = (outs);
459 let InOperandList = (ins variable_ops);
461 let neverHasSideEffects = 1;
463 def EXTRACT_SUBREG : Instruction {
464 let OutOperandList = (outs unknown:$dst);
465 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
467 let neverHasSideEffects = 1;
469 def INSERT_SUBREG : Instruction {
470 let OutOperandList = (outs unknown:$dst);
471 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
473 let neverHasSideEffects = 1;
474 let Constraints = "$supersrc = $dst";
476 def IMPLICIT_DEF : Instruction {
477 let OutOperandList = (outs unknown:$dst);
478 let InOperandList = (ins);
480 let neverHasSideEffects = 1;
481 let isReMaterializable = 1;
482 let isAsCheapAsAMove = 1;
484 def SUBREG_TO_REG : Instruction {
485 let OutOperandList = (outs unknown:$dst);
486 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
488 let neverHasSideEffects = 1;
490 def COPY_TO_REGCLASS : Instruction {
491 let OutOperandList = (outs unknown:$dst);
492 let InOperandList = (ins unknown:$src, i32imm:$regclass);
494 let neverHasSideEffects = 1;
495 let isAsCheapAsAMove = 1;
497 def DBG_VALUE : Instruction {
498 let OutOperandList = (outs);
499 let InOperandList = (ins variable_ops);
500 let AsmString = "DBG_VALUE";
501 let neverHasSideEffects = 1;
503 def REG_SEQUENCE : Instruction {
504 let OutOperandList = (outs unknown:$dst);
505 let InOperandList = (ins variable_ops);
507 let neverHasSideEffects = 1;
508 let isAsCheapAsAMove = 1;
510 def COPY : Instruction {
511 let OutOperandList = (outs unknown:$dst);
512 let InOperandList = (ins unknown:$src);
514 let neverHasSideEffects = 1;
515 let isAsCheapAsAMove = 1;
519 //===----------------------------------------------------------------------===//
520 // AsmParser - This class can be implemented by targets that wish to implement
523 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
524 // syntax on X86 for example).
527 // AsmParserClassName - This specifies the suffix to use for the asmparser
528 // class. Generated AsmParser classes are always prefixed with the target
530 string AsmParserClassName = "AsmParser";
532 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
533 // function of the AsmParser class to call on every matched instruction.
534 // This can be used to perform target specific instruction post-processing.
535 string AsmParserInstCleanup = "";
537 // Variant - AsmParsers can be of multiple different variants. Variants are
538 // used to support targets that need to parser multiple formats for the
539 // assembly language.
542 // CommentDelimiter - If given, the delimiter string used to recognize
543 // comments which are hard coded in the .td assembler strings for individual
545 string CommentDelimiter = "";
547 // RegisterPrefix - If given, the token prefix which indicates a register
548 // token. This is used by the matcher to automatically recognize hard coded
549 // register tokens as constrained registers, instead of tokens, for the
550 // purposes of matching.
551 string RegisterPrefix = "";
553 def DefaultAsmParser : AsmParser;
555 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
556 /// matches instructions and aliases.
557 class AssemblerPredicate {
558 bit AssemblerMatcherPredicate = 1;
563 /// MnemonicAlias - This class allows targets to define assembler mnemonic
564 /// aliases. This should be used when all forms of one mnemonic are accepted
565 /// with a different mnemonic. For example, X86 allows:
566 /// sal %al, 1 -> shl %al, 1
567 /// sal %ax, %cl -> shl %ax, %cl
568 /// sal %eax, %cl -> shl %eax, %cl
569 /// etc. Though "sal" is accepted with many forms, all of them are directly
570 /// translated to a shl, so it can be handled with (in the case of X86, it
571 /// actually has one for each suffix as well):
572 /// def : MnemonicAlias<"sal", "shl">;
574 /// Mnemonic aliases are mapped before any other translation in the match phase,
575 /// and do allow Requires predicates, e.g.:
577 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
578 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
580 class MnemonicAlias<string From, string To> {
581 string FromMnemonic = From;
582 string ToMnemonic = To;
584 // Predicates - Predicates that must be true for this remapping to happen.
585 list<Predicate> Predicates = [];
588 /// InstAlias - This defines an alternate assembly syntax that is allowed to
589 /// match an instruction that has a different (more canonical) assembly
591 class InstAlias<string Asm, dag Result> {
592 string AsmString = Asm; // The .s format to match the instruction with.
593 dag ResultInst = Result; // The MCInst to generate.
595 // Predicates - Predicates that must be true for this to match.
596 list<Predicate> Predicates = [];
599 //===----------------------------------------------------------------------===//
600 // AsmWriter - This class can be implemented by targets that need to customize
601 // the format of the .s file writer.
603 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
604 // on X86 for example).
607 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
608 // class. Generated AsmWriter classes are always prefixed with the target
610 string AsmWriterClassName = "AsmPrinter";
612 // Variant - AsmWriters can be of multiple different variants. Variants are
613 // used to support targets that need to emit assembly code in ways that are
614 // mostly the same for different targets, but have minor differences in
615 // syntax. If the asmstring contains {|} characters in them, this integer
616 // will specify which alternative to use. For example "{x|y|z}" with Variant
617 // == 1, will expand to "y".
621 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
622 // layout, the asmwriter can actually generate output in this columns (in
623 // verbose-asm mode). These two values indicate the width of the first column
624 // (the "opcode" area) and the width to reserve for subsequent operands. When
625 // verbose asm mode is enabled, operands will be indented to respect this.
626 int FirstOperandColumn = -1;
628 // OperandSpacing - Space between operand columns.
629 int OperandSpacing = -1;
631 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
632 // generation of the printInstruction() method. For MC printers, it takes
633 // an MCInstr* operand, otherwise it takes a MachineInstr*.
634 bit isMCAsmWriter = 0;
636 def DefaultAsmWriter : AsmWriter;
639 //===----------------------------------------------------------------------===//
640 // Target - This class contains the "global" target information
643 // InstructionSet - Instruction set description for this target.
644 InstrInfo InstructionSet;
646 // AssemblyParsers - The AsmParser instances available for this target.
647 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
649 // AssemblyWriters - The AsmWriter instances available for this target.
650 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
653 //===----------------------------------------------------------------------===//
654 // SubtargetFeature - A characteristic of the chip set.
656 class SubtargetFeature<string n, string a, string v, string d,
657 list<SubtargetFeature> i = []> {
658 // Name - Feature name. Used by command line (-mattr=) to determine the
659 // appropriate target chip.
663 // Attribute - Attribute to be set by feature.
665 string Attribute = a;
667 // Value - Value the attribute to be set to by feature.
671 // Desc - Feature description. Used by command line (-mattr=) to display help
676 // Implies - Features that this feature implies are present. If one of those
677 // features isn't set, then this one shouldn't be set either.
679 list<SubtargetFeature> Implies = i;
682 //===----------------------------------------------------------------------===//
683 // Processor chip sets - These values represent each of the chip sets supported
684 // by the scheduler. Each Processor definition requires corresponding
685 // instruction itineraries.
687 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
688 // Name - Chip set name. Used by command line (-mcpu=) to determine the
689 // appropriate target chip.
693 // ProcItin - The scheduling information for the target processor.
695 ProcessorItineraries ProcItin = pi;
697 // Features - list of
698 list<SubtargetFeature> Features = f;
701 //===----------------------------------------------------------------------===//
702 // Pull in the common support for calling conventions.
704 include "llvm/Target/TargetCallingConv.td"
706 //===----------------------------------------------------------------------===//
707 // Pull in the common support for DAG isel generation.
709 include "llvm/Target/TargetSelectionDAG.td"