1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances on SubRegIndex to identify subregisters.
26 string Namespace = "";
28 // This explicit numbering is going away after RegisterClass::SubRegClassList
33 // Register - You should define one instance of this class for each register
34 // in the target machine. String n will become the "name" of the register.
35 class Register<string n> {
36 string Namespace = "";
39 // SpillSize - If this value is set to a non-zero value, it is the size in
40 // bits of the spill slot required to hold this register. If this value is
41 // set to zero, the information is inferred from any register classes the
42 // register belongs to.
45 // SpillAlignment - This value is used to specify the alignment required for
46 // spilling the register. Like SpillSize, this should only be explicitly
47 // specified if the register is not in a register class.
48 int SpillAlignment = 0;
50 // Aliases - A list of registers that this register overlaps with. A read or
51 // modification of this register can potentially read or modify the aliased
53 list<Register> Aliases = [];
55 // SubRegs - A list of registers that are parts of this register. Note these
56 // are "immediate" sub-registers and the registers within the list do not
57 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
59 list<Register> SubRegs = [];
61 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
62 // These values can be determined by locating the <target>.h file in the
63 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
64 // order of these names correspond to the enumeration used by gcc. A value of
65 // -1 indicates that the gcc number is undefined and -2 that register number
66 // is invalid for this mode/flavour.
67 list<int> DwarfNumbers = [];
70 // RegisterWithSubRegs - This can be used to define instances of Register which
71 // need to specify sub-registers.
72 // List "subregs" specifies which registers are sub-registers to this one. This
73 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
74 // This allows the code generator to be careful not to put two values with
75 // overlapping live ranges into registers which alias.
76 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
77 let SubRegs = subregs;
80 // SubRegSet - This can be used to define a specific mapping of registers to
81 // indices, for use as named subregs of a particular physical register. Each
82 // register in 'subregs' becomes an addressable subregister at index 'n' of the
83 // corresponding register in 'regs'.
84 class SubRegSet<SubRegIndex n, list<Register> regs, list<Register> subregs> {
85 SubRegIndex Index = n;
87 list<Register> From = regs;
88 list<Register> To = subregs;
91 // RegisterClass - Now that all of the registers are defined, and aliases
92 // between registers are defined, specify which registers belong to which
93 // register classes. This also defines the default allocation order of
94 // registers by register allocators.
96 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
97 list<Register> regList> {
98 string Namespace = namespace;
100 // RegType - Specify the list ValueType of the registers in this register
101 // class. Note that all registers in a register class must have the same
102 // ValueTypes. This is a list because some targets permit storing different
103 // types in same register, for example vector values with 128-bit total size,
104 // but different count/size of items, like SSE on x86.
106 list<ValueType> RegTypes = regTypes;
108 // Size - Specify the spill size in bits of the registers. A default value of
109 // zero lets tablgen pick an appropriate size.
112 // Alignment - Specify the alignment required of the registers when they are
113 // stored or loaded to memory.
115 int Alignment = alignment;
117 // CopyCost - This value is used to specify the cost of copying a value
118 // between two registers in this register class. The default value is one
119 // meaning it takes a single instruction to perform the copying. A negative
120 // value means copying is extremely expensive or impossible.
123 // MemberList - Specify which registers are in this class. If the
124 // allocation_order_* method are not specified, this also defines the order of
125 // allocation used by the register allocator.
127 list<Register> MemberList = regList;
129 // SubRegClasses - Specify the register class of subregisters as a list of
130 // dags: (RegClass SubRegIndex, SubRegindex, ...)
131 list<dag> SubRegClasses = [];
133 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
134 // code into a generated register class. The normal usage of this is to
135 // overload virtual methods.
136 code MethodProtos = [{}];
137 code MethodBodies = [{}];
141 //===----------------------------------------------------------------------===//
142 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
143 // to the register numbering used by gcc and gdb. These values are used by a
144 // debug information writer to describe where values may be located during
146 class DwarfRegNum<list<int> Numbers> {
147 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
148 // These values can be determined by locating the <target>.h file in the
149 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
150 // order of these names correspond to the enumeration used by gcc. A value of
151 // -1 indicates that the gcc number is undefined and -2 that register number is
152 // invalid for this mode/flavour.
153 list<int> DwarfNumbers = Numbers;
156 //===----------------------------------------------------------------------===//
157 // Pull in the common support for scheduling
159 include "llvm/Target/TargetSchedule.td"
161 class Predicate; // Forward def
163 //===----------------------------------------------------------------------===//
164 // Instruction set description - These classes correspond to the C++ classes in
165 // the Target/TargetInstrInfo.h file.
168 string Namespace = "";
170 dag OutOperandList; // An dag containing the MI def operand list.
171 dag InOperandList; // An dag containing the MI use operand list.
172 string AsmString = ""; // The .s format to print the instruction with.
174 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
175 // otherwise, uninitialized.
178 // The follow state will eventually be inferred automatically from the
179 // instruction pattern.
181 list<Register> Uses = []; // Default to using no non-operand registers
182 list<Register> Defs = []; // Default to modifying no non-operand registers
184 // Predicates - List of predicates which will be turned into isel matching
186 list<Predicate> Predicates = [];
191 // Added complexity passed onto matching pattern.
192 int AddedComplexity = 0;
194 // These bits capture information about the high-level semantics of the
196 bit isReturn = 0; // Is this instruction a return instruction?
197 bit isBranch = 0; // Is this instruction a branch instruction?
198 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
199 bit isBarrier = 0; // Can control flow fall through this instruction?
200 bit isCall = 0; // Is this instruction a call instruction?
201 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
202 bit mayLoad = 0; // Is it possible for this inst to read memory?
203 bit mayStore = 0; // Is it possible for this inst to write memory?
204 bit isTwoAddress = 0; // Is this a two address instruction?
205 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
206 bit isCommutable = 0; // Is this 3 operand instruction commutable?
207 bit isTerminator = 0; // Is this part of the terminator for a basic block?
208 bit isReMaterializable = 0; // Is this instruction re-materializable?
209 bit isPredicable = 0; // Is this instruction predicable?
210 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
211 bit usesCustomInserter = 0; // Pseudo instr needing special help.
212 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
213 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
214 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
215 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
216 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
218 // Side effect flags - When set, the flags have these meanings:
220 // hasSideEffects - The instruction has side effects that are not
221 // captured by any operands of the instruction or other flags.
223 // neverHasSideEffects - Set on an instruction with no pattern if it has no
225 bit hasSideEffects = 0;
226 bit neverHasSideEffects = 0;
228 // Is this instruction a "real" instruction (with a distinct machine
229 // encoding), or is it a pseudo instruction used for codegen modeling
231 bit isCodeGenOnly = 0;
233 // Is this instruction a pseudo instruction for use by the assembler parser.
234 bit isAsmParserOnly = 0;
236 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
238 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
240 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
241 /// be encoded into the output machineinstr.
242 string DisableEncoding = "";
244 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
245 bits<32> TSFlags = 0;
248 /// Predicates - These are extra conditionals which are turned into instruction
249 /// selector matching code. Currently each predicate is just a string.
250 class Predicate<string cond> {
251 string CondString = cond;
254 /// NoHonorSignDependentRounding - This predicate is true if support for
255 /// sign-dependent-rounding is not enabled.
256 def NoHonorSignDependentRounding
257 : Predicate<"!HonorSignDependentRoundingFPMath()">;
259 class Requires<list<Predicate> preds> {
260 list<Predicate> Predicates = preds;
263 /// ops definition - This is just a simple marker used to identify the operands
264 /// list for an instruction. outs and ins are identical both syntatically and
265 /// semantically, they are used to define def operands and use operands to
266 /// improve readibility. This should be used like this:
267 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
272 /// variable_ops definition - Mark this instruction as taking a variable number
277 /// PointerLikeRegClass - Values that are designed to have pointer width are
278 /// derived from this. TableGen treats the register class as having a symbolic
279 /// type that it doesn't know, and resolves the actual regclass to use by using
280 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
281 class PointerLikeRegClass<int Kind> {
282 int RegClassKind = Kind;
286 /// ptr_rc definition - Mark this operand as being a pointer value whose
287 /// register class is resolved dynamically via a callback to TargetInstrInfo.
288 /// FIXME: We should probably change this to a class which contain a list of
289 /// flags. But currently we have but one flag.
290 def ptr_rc : PointerLikeRegClass<0>;
292 /// unknown definition - Mark this operand as being of unknown type, causing
293 /// it to be resolved by inference in the context it is used.
296 /// AsmOperandClass - Representation for the kinds of operands which the target
297 /// specific parser can create and the assembly matcher may need to distinguish.
299 /// Operand classes are used to define the order in which instructions are
300 /// matched, to ensure that the instruction which gets matched for any
301 /// particular list of operands is deterministic.
303 /// The target specific parser must be able to classify a parsed operand into a
304 /// unique class which does not partially overlap with any other classes. It can
305 /// match a subset of some other class, in which case the super class field
306 /// should be defined.
307 class AsmOperandClass {
308 /// The name to use for this class, which should be usable as an enum value.
311 /// The super classes of this operand.
312 list<AsmOperandClass> SuperClasses = [];
314 /// The name of the method on the target specific operand to call to test
315 /// whether the operand is an instance of this class. If not set, this will
316 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
317 /// signature should be:
318 /// bool isFoo() const;
319 string PredicateMethod = ?;
321 /// The name of the method on the target specific operand to call to add the
322 /// target specific operand to an MCInst. If not set, this will default to
323 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
324 /// signature should be:
325 /// void addFooOperands(MCInst &Inst, unsigned N) const;
326 string RenderMethod = ?;
329 def ImmAsmOperand : AsmOperandClass {
333 /// Operand Types - These provide the built-in operand types that may be used
334 /// by a target. Targets can optionally provide their own operand types as
335 /// needed, though this should not be needed for RISC targets.
336 class Operand<ValueType ty> {
338 string PrintMethod = "printOperand";
339 string AsmOperandLowerMethod = ?;
340 dag MIOperandInfo = (ops);
342 // ParserMatchClass - The "match class" that operands of this type fit
343 // in. Match classes are used to define the order in which instructions are
344 // match, to ensure that which instructions gets matched is deterministic.
346 // The target specific parser must be able to classify an parsed operand into
347 // a unique class, which does not partially overlap with any other classes. It
348 // can match a subset of some other class, in which case the AsmOperandClass
349 // should declare the other operand as one of its super classes.
350 AsmOperandClass ParserMatchClass = ImmAsmOperand;
353 def i1imm : Operand<i1>;
354 def i8imm : Operand<i8>;
355 def i16imm : Operand<i16>;
356 def i32imm : Operand<i32>;
357 def i64imm : Operand<i64>;
359 def f32imm : Operand<f32>;
360 def f64imm : Operand<f64>;
362 /// zero_reg definition - Special node to stand for the zero register.
366 /// PredicateOperand - This can be used to define a predicate operand for an
367 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
368 /// AlwaysVal specifies the value of this predicate when set to "always
370 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
372 let MIOperandInfo = OpTypes;
373 dag DefaultOps = AlwaysVal;
376 /// OptionalDefOperand - This is used to define a optional definition operand
377 /// for an instruction. DefaultOps is the register the operand represents if
378 /// none is supplied, e.g. zero_reg.
379 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
381 let MIOperandInfo = OpTypes;
382 dag DefaultOps = defaultops;
386 // InstrInfo - This class should only be instantiated once to provide parameters
387 // which are global to the target machine.
390 // Target can specify its instructions in either big or little-endian formats.
391 // For instance, while both Sparc and PowerPC are big-endian platforms, the
392 // Sparc manual specifies its instructions in the format [31..0] (big), while
393 // PowerPC specifies them using the format [0..31] (little).
394 bit isLittleEndianEncoding = 0;
397 // Standard Pseudo Instructions.
398 let isCodeGenOnly = 1 in {
399 def PHI : Instruction {
400 let OutOperandList = (outs);
401 let InOperandList = (ins variable_ops);
402 let AsmString = "PHINODE";
403 let Namespace = "TargetOpcode";
405 def INLINEASM : Instruction {
406 let OutOperandList = (outs);
407 let InOperandList = (ins variable_ops);
409 let Namespace = "TargetOpcode";
411 def DBG_LABEL : Instruction {
412 let OutOperandList = (outs);
413 let InOperandList = (ins i32imm:$id);
415 let Namespace = "TargetOpcode";
417 let isNotDuplicable = 1;
419 def EH_LABEL : Instruction {
420 let OutOperandList = (outs);
421 let InOperandList = (ins i32imm:$id);
423 let Namespace = "TargetOpcode";
425 let isNotDuplicable = 1;
427 def GC_LABEL : Instruction {
428 let OutOperandList = (outs);
429 let InOperandList = (ins i32imm:$id);
431 let Namespace = "TargetOpcode";
433 let isNotDuplicable = 1;
435 def KILL : Instruction {
436 let OutOperandList = (outs);
437 let InOperandList = (ins variable_ops);
439 let Namespace = "TargetOpcode";
440 let neverHasSideEffects = 1;
442 def EXTRACT_SUBREG : Instruction {
443 let OutOperandList = (outs unknown:$dst);
444 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
446 let Namespace = "TargetOpcode";
447 let neverHasSideEffects = 1;
449 def INSERT_SUBREG : Instruction {
450 let OutOperandList = (outs unknown:$dst);
451 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
453 let Namespace = "TargetOpcode";
454 let neverHasSideEffects = 1;
455 let Constraints = "$supersrc = $dst";
457 def IMPLICIT_DEF : Instruction {
458 let OutOperandList = (outs unknown:$dst);
459 let InOperandList = (ins);
461 let Namespace = "TargetOpcode";
462 let neverHasSideEffects = 1;
463 let isReMaterializable = 1;
464 let isAsCheapAsAMove = 1;
466 def SUBREG_TO_REG : Instruction {
467 let OutOperandList = (outs unknown:$dst);
468 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
470 let Namespace = "TargetOpcode";
471 let neverHasSideEffects = 1;
473 def COPY_TO_REGCLASS : Instruction {
474 let OutOperandList = (outs unknown:$dst);
475 let InOperandList = (ins unknown:$src, i32imm:$regclass);
477 let Namespace = "TargetOpcode";
478 let neverHasSideEffects = 1;
479 let isAsCheapAsAMove = 1;
481 def DBG_VALUE : Instruction {
482 let OutOperandList = (outs);
483 let InOperandList = (ins variable_ops);
484 let AsmString = "DBG_VALUE";
485 let Namespace = "TargetOpcode";
486 let isAsCheapAsAMove = 1;
489 def REG_SEQUENCE : Instruction {
490 let OutOperandList = (outs unknown:$dst);
491 let InOperandList = (ins variable_ops);
493 let Namespace = "TargetOpcode";
494 let neverHasSideEffects = 1;
495 let isAsCheapAsAMove = 1;
499 //===----------------------------------------------------------------------===//
500 // AsmParser - This class can be implemented by targets that wish to implement
503 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
504 // syntax on X86 for example).
507 // AsmParserClassName - This specifies the suffix to use for the asmparser
508 // class. Generated AsmParser classes are always prefixed with the target
510 string AsmParserClassName = "AsmParser";
512 // AsmParserInstCleanup - If non-empty, this is the name of a custom function on the
513 // AsmParser class to call on every matched instruction. This can be used to
514 // perform target specific instruction post-processing.
515 string AsmParserInstCleanup = "";
517 // MatchInstructionName - The name of the instruction matching function to
519 string MatchInstructionName = "MatchInstruction";
521 // Variant - AsmParsers can be of multiple different variants. Variants are
522 // used to support targets that need to parser multiple formats for the
523 // assembly language.
526 // CommentDelimiter - If given, the delimiter string used to recognize
527 // comments which are hard coded in the .td assembler strings for individual
529 string CommentDelimiter = "";
531 // RegisterPrefix - If given, the token prefix which indicates a register
532 // token. This is used by the matcher to automatically recognize hard coded
533 // register tokens as constrained registers, instead of tokens, for the
534 // purposes of matching.
535 string RegisterPrefix = "";
537 def DefaultAsmParser : AsmParser;
540 //===----------------------------------------------------------------------===//
541 // AsmWriter - This class can be implemented by targets that need to customize
542 // the format of the .s file writer.
544 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
545 // on X86 for example).
548 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
549 // class. Generated AsmWriter classes are always prefixed with the target
551 string AsmWriterClassName = "AsmPrinter";
553 // InstFormatName - AsmWriters can specify the name of the format string to
554 // print instructions with.
555 string InstFormatName = "AsmString";
557 // Variant - AsmWriters can be of multiple different variants. Variants are
558 // used to support targets that need to emit assembly code in ways that are
559 // mostly the same for different targets, but have minor differences in
560 // syntax. If the asmstring contains {|} characters in them, this integer
561 // will specify which alternative to use. For example "{x|y|z}" with Variant
562 // == 1, will expand to "y".
566 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
567 // layout, the asmwriter can actually generate output in this columns (in
568 // verbose-asm mode). These two values indicate the width of the first column
569 // (the "opcode" area) and the width to reserve for subsequent operands. When
570 // verbose asm mode is enabled, operands will be indented to respect this.
571 int FirstOperandColumn = -1;
573 // OperandSpacing - Space between operand columns.
574 int OperandSpacing = -1;
576 def DefaultAsmWriter : AsmWriter;
579 //===----------------------------------------------------------------------===//
580 // Target - This class contains the "global" target information
583 // InstructionSet - Instruction set description for this target.
584 InstrInfo InstructionSet;
586 // AssemblyParsers - The AsmParser instances available for this target.
587 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
589 // AssemblyWriters - The AsmWriter instances available for this target.
590 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
593 //===----------------------------------------------------------------------===//
594 // SubtargetFeature - A characteristic of the chip set.
596 class SubtargetFeature<string n, string a, string v, string d,
597 list<SubtargetFeature> i = []> {
598 // Name - Feature name. Used by command line (-mattr=) to determine the
599 // appropriate target chip.
603 // Attribute - Attribute to be set by feature.
605 string Attribute = a;
607 // Value - Value the attribute to be set to by feature.
611 // Desc - Feature description. Used by command line (-mattr=) to display help
616 // Implies - Features that this feature implies are present. If one of those
617 // features isn't set, then this one shouldn't be set either.
619 list<SubtargetFeature> Implies = i;
622 //===----------------------------------------------------------------------===//
623 // Processor chip sets - These values represent each of the chip sets supported
624 // by the scheduler. Each Processor definition requires corresponding
625 // instruction itineraries.
627 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
628 // Name - Chip set name. Used by command line (-mcpu=) to determine the
629 // appropriate target chip.
633 // ProcItin - The scheduling information for the target processor.
635 ProcessorItineraries ProcItin = pi;
637 // Features - list of
638 list<SubtargetFeature> Features = f;
641 //===----------------------------------------------------------------------===//
642 // Pull in the common support for calling conventions.
644 include "llvm/Target/TargetCallingConv.td"
646 //===----------------------------------------------------------------------===//
647 // Pull in the common support for DAG isel generation.
649 include "llvm/Target/TargetSelectionDAG.td"