1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
25 class SubRegIndex<list<SubRegIndex> comps = []> {
26 string Namespace = "";
28 // ComposedOf - A list of two SubRegIndex instances, [A, B].
29 // This indicates that this SubRegIndex is the result of composing A and B.
30 list<SubRegIndex> ComposedOf = comps;
33 // RegAltNameIndex - The alternate name set to use for register operands of
34 // this register class when printing.
35 class RegAltNameIndex {
36 string Namespace = "";
38 def NoRegAltName : RegAltNameIndex;
40 // Register - You should define one instance of this class for each register
41 // in the target machine. String n will become the "name" of the register.
42 class Register<string n, list<string> altNames = []> {
43 string Namespace = "";
45 list<string> AltNames = altNames;
47 // Aliases - A list of registers that this register overlaps with. A read or
48 // modification of this register can potentially read or modify the aliased
50 list<Register> Aliases = [];
52 // SubRegs - A list of registers that are parts of this register. Note these
53 // are "immediate" sub-registers and the registers within the list do not
54 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
56 list<Register> SubRegs = [];
58 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
59 // to address it. Sub-sub-register indices are automatically inherited from
61 list<SubRegIndex> SubRegIndices = [];
63 // RegAltNameIndices - The alternate name indices which are valid for this
65 list<RegAltNameIndex> RegAltNameIndices = [];
67 // CompositeIndices - Specify subreg indices that don't correspond directly to
68 // a register in SubRegs and are not inherited. The following formats are
71 // (a) Identity - Reg:a == Reg
72 // (a b) Alias - Reg:a == Reg:b
73 // (a b,c) Composite - Reg:a == (Reg:b):c
75 // This can be used to disambiguate a sub-sub-register that exists in more
76 // than one subregister and other weird stuff.
77 list<dag> CompositeIndices = [];
79 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
80 // These values can be determined by locating the <target>.h file in the
81 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
82 // order of these names correspond to the enumeration used by gcc. A value of
83 // -1 indicates that the gcc number is undefined and -2 that register number
84 // is invalid for this mode/flavour.
85 list<int> DwarfNumbers = [];
87 // CostPerUse - Additional cost of instructions using this register compared
88 // to other registers in its class. The register allocator will try to
89 // minimize the number of instructions using a register with a CostPerUse.
90 // This is used by the x86-64 and ARM Thumb targets where some registers
91 // require larger instruction encodings.
94 // CoveredBySubRegs - When this bit is set, the value of this register is
95 // completely determined by the value of its sub-registers. For example, the
96 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
97 // covered by its sub-register AX.
98 bit CoveredBySubRegs = 0;
100 // HWEncoding - The target specific hardware encoding for this register.
101 bits<16> HWEncoding = 0;
104 // RegisterWithSubRegs - This can be used to define instances of Register which
105 // need to specify sub-registers.
106 // List "subregs" specifies which registers are sub-registers to this one. This
107 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
108 // This allows the code generator to be careful not to put two values with
109 // overlapping live ranges into registers which alias.
110 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
111 let SubRegs = subregs;
114 // DAGOperand - An empty base class that unifies RegisterClass's and other forms
115 // of Operand's that are legal as type qualifiers in DAG patterns. This should
116 // only ever be used for defining multiclasses that are polymorphic over both
117 // RegisterClass's and other Operand's.
120 // RegisterClass - Now that all of the registers are defined, and aliases
121 // between registers are defined, specify which registers belong to which
122 // register classes. This also defines the default allocation order of
123 // registers by register allocators.
125 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
126 dag regList, RegAltNameIndex idx = NoRegAltName>
128 string Namespace = namespace;
130 // RegType - Specify the list ValueType of the registers in this register
131 // class. Note that all registers in a register class must have the same
132 // ValueTypes. This is a list because some targets permit storing different
133 // types in same register, for example vector values with 128-bit total size,
134 // but different count/size of items, like SSE on x86.
136 list<ValueType> RegTypes = regTypes;
138 // Size - Specify the spill size in bits of the registers. A default value of
139 // zero lets tablgen pick an appropriate size.
142 // Alignment - Specify the alignment required of the registers when they are
143 // stored or loaded to memory.
145 int Alignment = alignment;
147 // CopyCost - This value is used to specify the cost of copying a value
148 // between two registers in this register class. The default value is one
149 // meaning it takes a single instruction to perform the copying. A negative
150 // value means copying is extremely expensive or impossible.
153 // MemberList - Specify which registers are in this class. If the
154 // allocation_order_* method are not specified, this also defines the order of
155 // allocation used by the register allocator.
157 dag MemberList = regList;
159 // AltNameIndex - The alternate register name to use when printing operands
160 // of this register class. Every register in the register class must have
161 // a valid alternate name for the given index.
162 RegAltNameIndex altNameIndex = idx;
164 // isAllocatable - Specify that the register class can be used for virtual
165 // registers and register allocation. Some register classes are only used to
166 // model instruction operand constraints, and should have isAllocatable = 0.
167 bit isAllocatable = 1;
169 // AltOrders - List of alternative allocation orders. The default order is
170 // MemberList itself, and that is good enough for most targets since the
171 // register allocators automatically remove reserved registers and move
172 // callee-saved registers to the end.
173 list<dag> AltOrders = [];
175 // AltOrderSelect - The body of a function that selects the allocation order
176 // to use in a given machine function. The code will be inserted in a
177 // function like this:
179 // static inline unsigned f(const MachineFunction &MF) { ... }
181 // The function should return 0 to select the default order defined by
182 // MemberList, 1 to select the first AltOrders entry and so on.
183 code AltOrderSelect = [{}];
186 // The memberList in a RegisterClass is a dag of set operations. TableGen
187 // evaluates these set operations and expand them into register lists. These
188 // are the most common operation, see test/TableGen/SetTheory.td for more
189 // examples of what is possible:
191 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
192 // register class, or a sub-expression. This is also the way to simply list
195 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
197 // (and GPR, CSR) - Set intersection. All registers from the first set that are
198 // also in the second set.
200 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
201 // numbered registers. Takes an optional 4th operand which is a stride to use
202 // when generating the sequence.
204 // (shl GPR, 4) - Remove the first N elements.
206 // (trunc GPR, 4) - Truncate after the first N elements.
208 // (rotl GPR, 1) - Rotate N places to the left.
210 // (rotr GPR, 1) - Rotate N places to the right.
212 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
214 // (interleave A, B, ...) - Interleave the elements from each argument list.
216 // All of these operators work on ordered sets, not lists. That means
217 // duplicates are removed from sub-expressions.
219 // Set operators. The rest is defined in TargetSelectionDAG.td.
224 // RegisterTuples - Automatically generate super-registers by forming tuples of
225 // sub-registers. This is useful for modeling register sequence constraints
226 // with pseudo-registers that are larger than the architectural registers.
228 // The sub-register lists are zipped together:
230 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
232 // Generates the same registers as:
234 // let SubRegIndices = [sube, subo] in {
235 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
236 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
239 // The generated pseudo-registers inherit super-classes and fields from their
240 // first sub-register. Most fields from the Register class are inferred, and
241 // the AsmName and Dwarf numbers are cleared.
243 // RegisterTuples instances can be used in other set operations to form
244 // register classes and so on. This is the only way of using the generated
246 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
247 // SubRegs - N lists of registers to be zipped up. Super-registers are
248 // synthesized from the first element of each SubRegs list, the second
249 // element and so on.
250 list<dag> SubRegs = Regs;
252 // SubRegIndices - N SubRegIndex instances. This provides the names of the
253 // sub-registers in the synthesized super-registers.
254 list<SubRegIndex> SubRegIndices = Indices;
256 // Compose sub-register indices like in a normal Register.
257 list<dag> CompositeIndices = [];
261 //===----------------------------------------------------------------------===//
262 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
263 // to the register numbering used by gcc and gdb. These values are used by a
264 // debug information writer to describe where values may be located during
266 class DwarfRegNum<list<int> Numbers> {
267 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
268 // These values can be determined by locating the <target>.h file in the
269 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
270 // order of these names correspond to the enumeration used by gcc. A value of
271 // -1 indicates that the gcc number is undefined and -2 that register number
272 // is invalid for this mode/flavour.
273 list<int> DwarfNumbers = Numbers;
276 // DwarfRegAlias - This class declares that a given register uses the same dwarf
277 // numbers as another one. This is useful for making it clear that the two
278 // registers do have the same number. It also lets us build a mapping
279 // from dwarf register number to llvm register.
280 class DwarfRegAlias<Register reg> {
281 Register DwarfAlias = reg;
284 //===----------------------------------------------------------------------===//
285 // Pull in the common support for scheduling
287 include "llvm/Target/TargetSchedule.td"
289 class Predicate; // Forward def
291 //===----------------------------------------------------------------------===//
292 // Instruction set description - These classes correspond to the C++ classes in
293 // the Target/TargetInstrInfo.h file.
296 string Namespace = "";
298 dag OutOperandList; // An dag containing the MI def operand list.
299 dag InOperandList; // An dag containing the MI use operand list.
300 string AsmString = ""; // The .s format to print the instruction with.
302 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
303 // otherwise, uninitialized.
306 // The follow state will eventually be inferred automatically from the
307 // instruction pattern.
309 list<Register> Uses = []; // Default to using no non-operand registers
310 list<Register> Defs = []; // Default to modifying no non-operand registers
312 // Predicates - List of predicates which will be turned into isel matching
314 list<Predicate> Predicates = [];
316 // Size - Size of encoded instruction, or zero if the size cannot be determined
320 // DecoderNamespace - The "namespace" in which this instruction exists, on
321 // targets like ARM which multiple ISA namespaces exist.
322 string DecoderNamespace = "";
324 // Code size, for instruction selection.
325 // FIXME: What does this actually mean?
328 // Added complexity passed onto matching pattern.
329 int AddedComplexity = 0;
331 // These bits capture information about the high-level semantics of the
333 bit isReturn = 0; // Is this instruction a return instruction?
334 bit isBranch = 0; // Is this instruction a branch instruction?
335 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
336 bit isCompare = 0; // Is this instruction a comparison instruction?
337 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
338 bit isBitcast = 0; // Is this instruction a bitcast instruction?
339 bit isBarrier = 0; // Can control flow fall through this instruction?
340 bit isCall = 0; // Is this instruction a call instruction?
341 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
342 bit mayLoad = 0; // Is it possible for this inst to read memory?
343 bit mayStore = 0; // Is it possible for this inst to write memory?
344 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
345 bit isCommutable = 0; // Is this 3 operand instruction commutable?
346 bit isTerminator = 0; // Is this part of the terminator for a basic block?
347 bit isReMaterializable = 0; // Is this instruction re-materializable?
348 bit isPredicable = 0; // Is this instruction predicable?
349 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
350 bit usesCustomInserter = 0; // Pseudo instr needing special help.
351 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
352 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
353 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
354 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
355 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
356 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
357 bit isPseudo = 0; // Is this instruction a pseudo-instruction?
358 // If so, won't have encoding information for
359 // the [MC]CodeEmitter stuff.
361 // Side effect flags - When set, the flags have these meanings:
363 // hasSideEffects - The instruction has side effects that are not
364 // captured by any operands of the instruction or other flags.
366 // neverHasSideEffects - Set on an instruction with no pattern if it has no
368 bit hasSideEffects = 0;
369 bit neverHasSideEffects = 0;
371 // Is this instruction a "real" instruction (with a distinct machine
372 // encoding), or is it a pseudo instruction used for codegen modeling
374 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
375 // instructions can (and often do) still have encoding information
376 // associated with them. Once we've migrated all of them over to true
377 // pseudo-instructions that are lowered to real instructions prior to
378 // the printer/emitter, we can remove this attribute and just use isPseudo.
380 // The intended use is:
381 // isPseudo: Does not have encoding information and should be expanded,
382 // at the latest, during lowering to MCInst.
384 // isCodeGenOnly: Does have encoding information and can go through to the
385 // CodeEmitter unchanged, but duplicates a canonical instruction
386 // definition's encoding and should be ignored when constructing the
387 // assembler match tables.
388 bit isCodeGenOnly = 0;
390 // Is this instruction a pseudo instruction for use by the assembler parser.
391 bit isAsmParserOnly = 0;
393 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
395 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
397 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
398 /// be encoded into the output machineinstr.
399 string DisableEncoding = "";
401 string PostEncoderMethod = "";
402 string DecoderMethod = "";
404 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
405 bits<64> TSFlags = 0;
407 ///@name Assembler Parser Support
410 string AsmMatchConverter = "";
412 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
413 /// two-operand matcher inst-alias for a three operand instruction.
414 /// For example, the arm instruction "add r3, r3, r5" can be written
415 /// as "add r3, r5". The constraint is of the same form as a tied-operand
416 /// constraint. For example, "$Rn = $Rd".
417 string TwoOperandAliasConstraint = "";
422 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
423 /// Which instruction it expands to and how the operands map from the
425 class PseudoInstExpansion<dag Result> {
426 dag ResultInst = Result; // The instruction to generate.
430 /// Predicates - These are extra conditionals which are turned into instruction
431 /// selector matching code. Currently each predicate is just a string.
432 class Predicate<string cond> {
433 string CondString = cond;
435 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
436 /// matcher, this is true. Targets should set this by inheriting their
437 /// feature from the AssemblerPredicate class in addition to Predicate.
438 bit AssemblerMatcherPredicate = 0;
440 /// AssemblerCondString - Name of the subtarget feature being tested used
441 /// as alternative condition string used for assembler matcher.
442 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
443 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
444 /// It can also list multiple features separated by ",".
445 /// e.g. "ModeThumb,FeatureThumb2" is translated to
446 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
447 string AssemblerCondString = "";
449 /// PredicateName - User-level name to use for the predicate. Mainly for use
450 /// in diagnostics such as missing feature errors in the asm matcher.
451 string PredicateName = "";
454 /// NoHonorSignDependentRounding - This predicate is true if support for
455 /// sign-dependent-rounding is not enabled.
456 def NoHonorSignDependentRounding
457 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
459 class Requires<list<Predicate> preds> {
460 list<Predicate> Predicates = preds;
463 /// ops definition - This is just a simple marker used to identify the operand
464 /// list for an instruction. outs and ins are identical both syntactically and
465 /// semanticallyr; they are used to define def operands and use operands to
466 /// improve readibility. This should be used like this:
467 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
472 /// variable_ops definition - Mark this instruction as taking a variable number
477 /// PointerLikeRegClass - Values that are designed to have pointer width are
478 /// derived from this. TableGen treats the register class as having a symbolic
479 /// type that it doesn't know, and resolves the actual regclass to use by using
480 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
481 class PointerLikeRegClass<int Kind> {
482 int RegClassKind = Kind;
486 /// ptr_rc definition - Mark this operand as being a pointer value whose
487 /// register class is resolved dynamically via a callback to TargetInstrInfo.
488 /// FIXME: We should probably change this to a class which contain a list of
489 /// flags. But currently we have but one flag.
490 def ptr_rc : PointerLikeRegClass<0>;
492 /// unknown definition - Mark this operand as being of unknown type, causing
493 /// it to be resolved by inference in the context it is used.
496 /// AsmOperandClass - Representation for the kinds of operands which the target
497 /// specific parser can create and the assembly matcher may need to distinguish.
499 /// Operand classes are used to define the order in which instructions are
500 /// matched, to ensure that the instruction which gets matched for any
501 /// particular list of operands is deterministic.
503 /// The target specific parser must be able to classify a parsed operand into a
504 /// unique class which does not partially overlap with any other classes. It can
505 /// match a subset of some other class, in which case the super class field
506 /// should be defined.
507 class AsmOperandClass {
508 /// The name to use for this class, which should be usable as an enum value.
511 /// The super classes of this operand.
512 list<AsmOperandClass> SuperClasses = [];
514 /// The name of the method on the target specific operand to call to test
515 /// whether the operand is an instance of this class. If not set, this will
516 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
517 /// signature should be:
518 /// bool isFoo() const;
519 string PredicateMethod = ?;
521 /// The name of the method on the target specific operand to call to add the
522 /// target specific operand to an MCInst. If not set, this will default to
523 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
524 /// signature should be:
525 /// void addFooOperands(MCInst &Inst, unsigned N) const;
526 string RenderMethod = ?;
528 /// The name of the method on the target specific operand to call to custom
529 /// handle the operand parsing. This is useful when the operands do not relate
530 /// to immediates or registers and are very instruction specific (as flags to
531 /// set in a processor register, coprocessor number, ...).
532 string ParserMethod = ?;
534 // The diagnostic type to present when referencing this operand in a
535 // match failure error message. By default, use a generic "invalid operand"
536 // diagnostic. The target AsmParser maps these codes to text.
537 string DiagnosticType = "";
540 def ImmAsmOperand : AsmOperandClass {
544 /// Operand Types - These provide the built-in operand types that may be used
545 /// by a target. Targets can optionally provide their own operand types as
546 /// needed, though this should not be needed for RISC targets.
547 class Operand<ValueType ty> : DAGOperand {
549 string PrintMethod = "printOperand";
550 string EncoderMethod = "";
551 string DecoderMethod = "";
552 string AsmOperandLowerMethod = ?;
553 string OperandType = "OPERAND_UNKNOWN";
554 dag MIOperandInfo = (ops);
556 // ParserMatchClass - The "match class" that operands of this type fit
557 // in. Match classes are used to define the order in which instructions are
558 // match, to ensure that which instructions gets matched is deterministic.
560 // The target specific parser must be able to classify an parsed operand into
561 // a unique class, which does not partially overlap with any other classes. It
562 // can match a subset of some other class, in which case the AsmOperandClass
563 // should declare the other operand as one of its super classes.
564 AsmOperandClass ParserMatchClass = ImmAsmOperand;
567 class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> {
568 // RegClass - The register class of the operand.
569 RegisterClass RegClass = regclass;
570 // PrintMethod - The target method to call to print register operands of
571 // this type. The method normally will just use an alt-name index to look
572 // up the name to print. Default to the generic printOperand().
573 string PrintMethod = pm;
574 // ParserMatchClass - The "match class" that operands of this type fit
575 // in. Match classes are used to define the order in which instructions are
576 // match, to ensure that which instructions gets matched is deterministic.
578 // The target specific parser must be able to classify an parsed operand into
579 // a unique class, which does not partially overlap with any other classes. It
580 // can match a subset of some other class, in which case the AsmOperandClass
581 // should declare the other operand as one of its super classes.
582 AsmOperandClass ParserMatchClass;
585 let OperandType = "OPERAND_IMMEDIATE" in {
586 def i1imm : Operand<i1>;
587 def i8imm : Operand<i8>;
588 def i16imm : Operand<i16>;
589 def i32imm : Operand<i32>;
590 def i64imm : Operand<i64>;
592 def f32imm : Operand<f32>;
593 def f64imm : Operand<f64>;
596 /// zero_reg definition - Special node to stand for the zero register.
600 /// PredicateOperand - This can be used to define a predicate operand for an
601 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
602 /// AlwaysVal specifies the value of this predicate when set to "always
604 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
606 let MIOperandInfo = OpTypes;
607 dag DefaultOps = AlwaysVal;
610 /// OptionalDefOperand - This is used to define a optional definition operand
611 /// for an instruction. DefaultOps is the register the operand represents if
612 /// none is supplied, e.g. zero_reg.
613 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
615 let MIOperandInfo = OpTypes;
616 dag DefaultOps = defaultops;
620 // InstrInfo - This class should only be instantiated once to provide parameters
621 // which are global to the target machine.
624 // Target can specify its instructions in either big or little-endian formats.
625 // For instance, while both Sparc and PowerPC are big-endian platforms, the
626 // Sparc manual specifies its instructions in the format [31..0] (big), while
627 // PowerPC specifies them using the format [0..31] (little).
628 bit isLittleEndianEncoding = 0;
631 // Standard Pseudo Instructions.
632 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
633 // Only these instructions are allowed in the TargetOpcode namespace.
634 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
635 def PHI : Instruction {
636 let OutOperandList = (outs);
637 let InOperandList = (ins variable_ops);
638 let AsmString = "PHINODE";
640 def INLINEASM : Instruction {
641 let OutOperandList = (outs);
642 let InOperandList = (ins variable_ops);
644 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
646 def PROLOG_LABEL : Instruction {
647 let OutOperandList = (outs);
648 let InOperandList = (ins i32imm:$id);
651 let isNotDuplicable = 1;
653 def EH_LABEL : Instruction {
654 let OutOperandList = (outs);
655 let InOperandList = (ins i32imm:$id);
658 let isNotDuplicable = 1;
660 def GC_LABEL : Instruction {
661 let OutOperandList = (outs);
662 let InOperandList = (ins i32imm:$id);
665 let isNotDuplicable = 1;
667 def KILL : Instruction {
668 let OutOperandList = (outs);
669 let InOperandList = (ins variable_ops);
671 let neverHasSideEffects = 1;
673 def EXTRACT_SUBREG : Instruction {
674 let OutOperandList = (outs unknown:$dst);
675 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
677 let neverHasSideEffects = 1;
679 def INSERT_SUBREG : Instruction {
680 let OutOperandList = (outs unknown:$dst);
681 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
683 let neverHasSideEffects = 1;
684 let Constraints = "$supersrc = $dst";
686 def IMPLICIT_DEF : Instruction {
687 let OutOperandList = (outs unknown:$dst);
688 let InOperandList = (ins);
690 let neverHasSideEffects = 1;
691 let isReMaterializable = 1;
692 let isAsCheapAsAMove = 1;
694 def SUBREG_TO_REG : Instruction {
695 let OutOperandList = (outs unknown:$dst);
696 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
698 let neverHasSideEffects = 1;
700 def COPY_TO_REGCLASS : Instruction {
701 let OutOperandList = (outs unknown:$dst);
702 let InOperandList = (ins unknown:$src, i32imm:$regclass);
704 let neverHasSideEffects = 1;
705 let isAsCheapAsAMove = 1;
707 def DBG_VALUE : Instruction {
708 let OutOperandList = (outs);
709 let InOperandList = (ins variable_ops);
710 let AsmString = "DBG_VALUE";
711 let neverHasSideEffects = 1;
713 def REG_SEQUENCE : Instruction {
714 let OutOperandList = (outs unknown:$dst);
715 let InOperandList = (ins variable_ops);
717 let neverHasSideEffects = 1;
718 let isAsCheapAsAMove = 1;
720 def COPY : Instruction {
721 let OutOperandList = (outs unknown:$dst);
722 let InOperandList = (ins unknown:$src);
724 let neverHasSideEffects = 1;
725 let isAsCheapAsAMove = 1;
727 def BUNDLE : Instruction {
728 let OutOperandList = (outs);
729 let InOperandList = (ins variable_ops);
730 let AsmString = "BUNDLE";
734 //===----------------------------------------------------------------------===//
735 // AsmParser - This class can be implemented by targets that wish to implement
738 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
739 // syntax on X86 for example).
742 // AsmParserClassName - This specifies the suffix to use for the asmparser
743 // class. Generated AsmParser classes are always prefixed with the target
745 string AsmParserClassName = "AsmParser";
747 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
748 // function of the AsmParser class to call on every matched instruction.
749 // This can be used to perform target specific instruction post-processing.
750 string AsmParserInstCleanup = "";
752 def DefaultAsmParser : AsmParser;
754 //===----------------------------------------------------------------------===//
755 // AsmParserVariant - Subtargets can have multiple different assembly parsers
756 // (e.g. AT&T vs Intel syntax on X86 for example). This class can be
757 // implemented by targets to describe such variants.
759 class AsmParserVariant {
760 // Variant - AsmParsers can be of multiple different variants. Variants are
761 // used to support targets that need to parser multiple formats for the
762 // assembly language.
765 // CommentDelimiter - If given, the delimiter string used to recognize
766 // comments which are hard coded in the .td assembler strings for individual
768 string CommentDelimiter = "";
770 // RegisterPrefix - If given, the token prefix which indicates a register
771 // token. This is used by the matcher to automatically recognize hard coded
772 // register tokens as constrained registers, instead of tokens, for the
773 // purposes of matching.
774 string RegisterPrefix = "";
776 def DefaultAsmParserVariant : AsmParserVariant;
778 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
779 /// matches instructions and aliases.
780 class AssemblerPredicate<string cond, string name = ""> {
781 bit AssemblerMatcherPredicate = 1;
782 string AssemblerCondString = cond;
783 string PredicateName = name;
786 /// TokenAlias - This class allows targets to define assembler token
787 /// operand aliases. That is, a token literal operand which is equivalent
788 /// to another, canonical, token literal. For example, ARM allows:
789 /// vmov.u32 s4, #0 -> vmov.i32, #0
790 /// 'u32' is a more specific designator for the 32-bit integer type specifier
791 /// and is legal for any instruction which accepts 'i32' as a datatype suffix.
792 /// def : TokenAlias<".u32", ".i32">;
794 /// This works by marking the match class of 'From' as a subclass of the
795 /// match class of 'To'.
796 class TokenAlias<string From, string To> {
797 string FromToken = From;
801 /// MnemonicAlias - This class allows targets to define assembler mnemonic
802 /// aliases. This should be used when all forms of one mnemonic are accepted
803 /// with a different mnemonic. For example, X86 allows:
804 /// sal %al, 1 -> shl %al, 1
805 /// sal %ax, %cl -> shl %ax, %cl
806 /// sal %eax, %cl -> shl %eax, %cl
807 /// etc. Though "sal" is accepted with many forms, all of them are directly
808 /// translated to a shl, so it can be handled with (in the case of X86, it
809 /// actually has one for each suffix as well):
810 /// def : MnemonicAlias<"sal", "shl">;
812 /// Mnemonic aliases are mapped before any other translation in the match phase,
813 /// and do allow Requires predicates, e.g.:
815 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
816 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
818 class MnemonicAlias<string From, string To> {
819 string FromMnemonic = From;
820 string ToMnemonic = To;
822 // Predicates - Predicates that must be true for this remapping to happen.
823 list<Predicate> Predicates = [];
826 /// InstAlias - This defines an alternate assembly syntax that is allowed to
827 /// match an instruction that has a different (more canonical) assembly
829 class InstAlias<string Asm, dag Result, bit Emit = 0b1> {
830 string AsmString = Asm; // The .s format to match the instruction with.
831 dag ResultInst = Result; // The MCInst to generate.
832 bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
834 // Predicates - Predicates that must be true for this to match.
835 list<Predicate> Predicates = [];
838 //===----------------------------------------------------------------------===//
839 // AsmWriter - This class can be implemented by targets that need to customize
840 // the format of the .s file writer.
842 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
843 // on X86 for example).
846 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
847 // class. Generated AsmWriter classes are always prefixed with the target
849 string AsmWriterClassName = "AsmPrinter";
851 // Variant - AsmWriters can be of multiple different variants. Variants are
852 // used to support targets that need to emit assembly code in ways that are
853 // mostly the same for different targets, but have minor differences in
854 // syntax. If the asmstring contains {|} characters in them, this integer
855 // will specify which alternative to use. For example "{x|y|z}" with Variant
856 // == 1, will expand to "y".
860 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
861 // layout, the asmwriter can actually generate output in this columns (in
862 // verbose-asm mode). These two values indicate the width of the first column
863 // (the "opcode" area) and the width to reserve for subsequent operands. When
864 // verbose asm mode is enabled, operands will be indented to respect this.
865 int FirstOperandColumn = -1;
867 // OperandSpacing - Space between operand columns.
868 int OperandSpacing = -1;
870 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
871 // generation of the printInstruction() method. For MC printers, it takes
872 // an MCInstr* operand, otherwise it takes a MachineInstr*.
873 bit isMCAsmWriter = 0;
875 def DefaultAsmWriter : AsmWriter;
878 //===----------------------------------------------------------------------===//
879 // Target - This class contains the "global" target information
882 // InstructionSet - Instruction set description for this target.
883 InstrInfo InstructionSet;
885 // AssemblyParsers - The AsmParser instances available for this target.
886 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
888 /// AssemblyParserVariants - The AsmParserVariant instances available for
890 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
892 // AssemblyWriters - The AsmWriter instances available for this target.
893 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
896 //===----------------------------------------------------------------------===//
897 // SubtargetFeature - A characteristic of the chip set.
899 class SubtargetFeature<string n, string a, string v, string d,
900 list<SubtargetFeature> i = []> {
901 // Name - Feature name. Used by command line (-mattr=) to determine the
902 // appropriate target chip.
906 // Attribute - Attribute to be set by feature.
908 string Attribute = a;
910 // Value - Value the attribute to be set to by feature.
914 // Desc - Feature description. Used by command line (-mattr=) to display help
919 // Implies - Features that this feature implies are present. If one of those
920 // features isn't set, then this one shouldn't be set either.
922 list<SubtargetFeature> Implies = i;
925 //===----------------------------------------------------------------------===//
926 // Processor chip sets - These values represent each of the chip sets supported
927 // by the scheduler. Each Processor definition requires corresponding
928 // instruction itineraries.
930 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
931 // Name - Chip set name. Used by command line (-mcpu=) to determine the
932 // appropriate target chip.
936 // ProcItin - The scheduling information for the target processor.
938 ProcessorItineraries ProcItin = pi;
940 // Features - list of
941 list<SubtargetFeature> Features = f;
944 //===----------------------------------------------------------------------===//
945 // Pull in the common support for calling conventions.
947 include "llvm/Target/TargetCallingConv.td"
949 //===----------------------------------------------------------------------===//
950 // Pull in the common support for DAG isel generation.
952 include "llvm/Target/TargetSelectionDAG.td"