1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // This file describes the target machine instructions to the code generator.
5 //===----------------------------------------------------------------------===//
7 #ifndef LLVM_TARGET_MACHINEINSTRINFO_H
8 #define LLVM_TARGET_MACHINEINSTRINFO_H
10 #include "Support/DataTypes.h"
19 class MachineCodeForInstruction;
21 //---------------------------------------------------------------------------
22 // Data types used to define information about a single machine instruction
23 //---------------------------------------------------------------------------
25 typedef int MachineOpCode;
26 typedef unsigned InstrSchedClass;
28 const MachineOpCode INVALID_MACHINE_OPCODE = -1;
31 //---------------------------------------------------------------------------
32 // struct MachineInstrDescriptor:
33 // Predefined information about each machine instruction.
34 // Designed to initialized statically.
36 // class MachineInstructionInfo
37 // Interface to description of machine instructions
39 //---------------------------------------------------------------------------
41 const unsigned M_NOP_FLAG = 1 << 0;
42 const unsigned M_BRANCH_FLAG = 1 << 1;
43 const unsigned M_CALL_FLAG = 1 << 2;
44 const unsigned M_RET_FLAG = 1 << 3;
45 const unsigned M_ARITH_FLAG = 1 << 4;
46 const unsigned M_CC_FLAG = 1 << 6;
47 const unsigned M_LOGICAL_FLAG = 1 << 6;
48 const unsigned M_INT_FLAG = 1 << 7;
49 const unsigned M_FLOAT_FLAG = 1 << 8;
50 const unsigned M_CONDL_FLAG = 1 << 9;
51 const unsigned M_LOAD_FLAG = 1 << 10;
52 const unsigned M_PREFETCH_FLAG = 1 << 11;
53 const unsigned M_STORE_FLAG = 1 << 12;
54 const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
55 const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction
56 // 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub
57 const unsigned M_2_ADDR_FLAG = 1 << 15;
59 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
60 // block? Typically this is things like return and branch instructions.
61 // Various passes use this to insert code into the bottom of a basic block, but
62 // before control flow occurs.
63 const unsigned M_TERMINATOR_FLAG = 1 << 16;
65 struct TargetInstrDescriptor {
66 const char * Name; // Assembly language mnemonic for the opcode.
67 int numOperands; // Number of args; -1 if variable #args
68 int resultPos; // Position of the result; -1 if no result
69 unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0.
70 bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
71 // smallest -ve value is -(maxImmedConst+1).
72 unsigned numDelaySlots; // Number of delay slots after instruction
73 unsigned latency; // Latency in machine cycles
74 InstrSchedClass schedClass; // enum identifying instr sched class
75 unsigned Flags; // flags identifying machine instr class
76 unsigned TSFlags; // Target Specific Flag values
77 const unsigned *ImplicitUses; // Registers implicitly read by this instr
78 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
81 typedef TargetInstrDescriptor MachineInstrDescriptor;
83 class TargetInstrInfo {
84 const TargetInstrDescriptor* desc; // raw array to allow static init'n
85 unsigned descSize; // number of entries in the desc array
86 unsigned numRealOpCodes; // number of non-dummy op codes
88 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
89 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
91 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned descSize,
92 unsigned numRealOpCodes);
93 virtual ~TargetInstrInfo();
95 // Invariant: All instruction sets use opcode #0 as the PHI instruction and
96 // opcode #1 as the noop instruction.
101 unsigned getNumRealOpCodes() const { return numRealOpCodes; }
102 unsigned getNumTotalOpCodes() const { return descSize; }
104 /// get - Return the machine instruction descriptor that corresponds to the
105 /// specified instruction opcode.
107 const TargetInstrDescriptor& get(MachineOpCode opCode) const {
108 assert(opCode >= 0 && opCode < (int)descSize);
112 /// print - Print out the specified machine instruction in the appropriate
113 /// target specific assembly language. If this method is not overridden, the
114 /// default implementation uses the crummy machine independant printer.
116 virtual void print(const MachineInstr *MI, std::ostream &O,
117 const TargetMachine &TM) const;
119 const char *getName(MachineOpCode opCode) const {
120 return get(opCode).Name;
123 int getNumOperands(MachineOpCode opCode) const {
124 return get(opCode).numOperands;
127 int getResultPos(MachineOpCode opCode) const {
128 return get(opCode).resultPos;
131 unsigned getNumDelaySlots(MachineOpCode opCode) const {
132 return get(opCode).numDelaySlots;
135 InstrSchedClass getSchedClass(MachineOpCode opCode) const {
136 return get(opCode).schedClass;
140 // Query instruction class flags according to the machine-independent
141 // flags listed above.
143 bool isNop(MachineOpCode opCode) const {
144 return get(opCode).Flags & M_NOP_FLAG;
146 bool isBranch(MachineOpCode opCode) const {
147 return get(opCode).Flags & M_BRANCH_FLAG;
149 bool isCall(MachineOpCode opCode) const {
150 return get(opCode).Flags & M_CALL_FLAG;
152 bool isReturn(MachineOpCode opCode) const {
153 return get(opCode).Flags & M_RET_FLAG;
155 bool isControlFlow(MachineOpCode opCode) const {
156 return get(opCode).Flags & M_BRANCH_FLAG
157 || get(opCode).Flags & M_CALL_FLAG
158 || get(opCode).Flags & M_RET_FLAG;
160 bool isArith(MachineOpCode opCode) const {
161 return get(opCode).Flags & M_ARITH_FLAG;
163 bool isCCInstr(MachineOpCode opCode) const {
164 return get(opCode).Flags & M_CC_FLAG;
166 bool isLogical(MachineOpCode opCode) const {
167 return get(opCode).Flags & M_LOGICAL_FLAG;
169 bool isIntInstr(MachineOpCode opCode) const {
170 return get(opCode).Flags & M_INT_FLAG;
172 bool isFloatInstr(MachineOpCode opCode) const {
173 return get(opCode).Flags & M_FLOAT_FLAG;
175 bool isConditional(MachineOpCode opCode) const {
176 return get(opCode).Flags & M_CONDL_FLAG;
178 bool isLoad(MachineOpCode opCode) const {
179 return get(opCode).Flags & M_LOAD_FLAG;
181 bool isPrefetch(MachineOpCode opCode) const {
182 return get(opCode).Flags & M_PREFETCH_FLAG;
184 bool isLoadOrPrefetch(MachineOpCode opCode) const {
185 return get(opCode).Flags & M_LOAD_FLAG
186 || get(opCode).Flags & M_PREFETCH_FLAG;
188 bool isStore(MachineOpCode opCode) const {
189 return get(opCode).Flags & M_STORE_FLAG;
191 bool isMemoryAccess(MachineOpCode opCode) const {
192 return get(opCode).Flags & M_LOAD_FLAG
193 || get(opCode).Flags & M_PREFETCH_FLAG
194 || get(opCode).Flags & M_STORE_FLAG;
196 bool isDummyPhiInstr(MachineOpCode opCode) const {
197 return get(opCode).Flags & M_DUMMY_PHI_FLAG;
199 bool isPseudoInstr(MachineOpCode opCode) const {
200 return get(opCode).Flags & M_PSEUDO_FLAG;
202 bool isTwoAddrInstr(MachineOpCode opCode) const {
203 return get(opCode).Flags & M_2_ADDR_FLAG;
205 bool isTerminatorInstr(unsigned Opcode) const {
206 return get(Opcode).Flags & M_TERMINATOR_FLAG;
209 // Check if an instruction can be issued before its operands are ready,
210 // or if a subsequent instruction that uses its result can be issued
211 // before the results are ready.
212 // Default to true since most instructions on many architectures allow this.
214 virtual bool hasOperandInterlock(MachineOpCode opCode) const {
218 virtual bool hasResultInterlock(MachineOpCode opCode) const {
223 // Latencies for individual instructions and instruction pairs
225 virtual int minLatency(MachineOpCode opCode) const {
226 return get(opCode).latency;
229 virtual int maxLatency(MachineOpCode opCode) const {
230 return get(opCode).latency;
234 // Which operand holds an immediate constant? Returns -1 if none
236 virtual int getImmedConstantPos(MachineOpCode opCode) const {
237 return -1; // immediate position is machine specific, so say -1 == "none"
240 // Check if the specified constant fits in the immediate field
241 // of this machine instruction
243 virtual bool constantFitsInImmedField(MachineOpCode opCode,
244 int64_t intValue) const;
246 // Return the largest +ve constant that can be held in the IMMMED field
247 // of this machine instruction.
248 // isSignExtended is set to true if the value is sign-extended before use
249 // (this is true for all immediate fields in SPARC instructions).
250 // Return 0 if the instruction has no IMMED field.
252 virtual uint64_t maxImmedConstant(MachineOpCode opCode,
253 bool &isSignExtended) const {
254 isSignExtended = get(opCode).immedIsSignExtended;
255 return get(opCode).maxImmedConst;
258 //-------------------------------------------------------------------------
259 // Queries about representation of LLVM quantities (e.g., constants)
260 //-------------------------------------------------------------------------
262 /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded
263 /// from memory into a register, i.e., cannot be set bitwise in register and
264 /// cannot use immediate fields of instructions. Note that this only makes
265 /// sense for primitive types.
267 virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const;
269 // Test if this constant may not fit in the immediate field of the
270 // machine instructions (probably) generated for this instruction.
272 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
273 const Instruction* I) const {
274 return true; // safe but very conservative
277 //-------------------------------------------------------------------------
278 // Code generation support for creating individual machine instructions
280 // WARNING: These methods are Sparc specific
282 //-------------------------------------------------------------------------
284 // Get certain common op codes for the current target. this and all the
285 // Create* methods below should be moved to a machine code generation class
287 virtual MachineOpCode getNOPOpCode() const { abort(); }
289 // Create an instruction sequence to put the constant `val' into
290 // the virtual register `dest'. `val' may be a Constant or a
291 // GlobalValue, viz., the constant address of a global variable or function.
292 // The generated instructions are returned in `mvec'.
293 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
294 // Symbolic constants or constants that must be accessed from memory
295 // are added to the constant pool via MachineFunction::get(F).
297 virtual void CreateCodeToLoadConst(const TargetMachine& target,
301 std::vector<MachineInstr*>& mvec,
302 MachineCodeForInstruction& mcfi) const {
306 // Create an instruction sequence to copy an integer value `val'
307 // to a floating point value `dest' by copying to memory and back.
308 // val must be an integral type. dest must be a Float or Double.
309 // The generated instructions are returned in `mvec'.
310 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
311 // Any stack space required is allocated via mcff.
313 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
317 std::vector<MachineInstr*>& mvec,
318 MachineCodeForInstruction& MI) const {
322 // Similarly, create an instruction sequence to copy an FP value
323 // `val' to an integer value `dest' by copying to memory and back.
324 // The generated instructions are returned in `mvec'.
325 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
326 // Any stack space required is allocated via mcff.
328 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
332 std::vector<MachineInstr*>& mvec,
333 MachineCodeForInstruction& MI) const {
337 // Create instruction(s) to copy src to dest, for arbitrary types
338 // The generated instructions are returned in `mvec'.
339 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
340 // Any stack space required is allocated via mcff.
342 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
346 std::vector<MachineInstr*>& mvec,
347 MachineCodeForInstruction& MI) const {
351 // Create instruction sequence to produce a sign-extended register value
352 // from an arbitrary sized value (sized in bits, not bytes).
353 // The generated instructions are appended to `mvec'.
354 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
355 // Any stack space required is allocated via mcff.
357 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
362 std::vector<MachineInstr*>& mvec,
363 MachineCodeForInstruction& MI) const {
367 // Create instruction sequence to produce a zero-extended register value
368 // from an arbitrary sized value (sized in bits, not bytes).
369 // The generated instructions are appended to `mvec'.
370 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
371 // Any stack space required is allocated via mcff.
373 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
377 unsigned srcSizeInBits,
378 std::vector<MachineInstr*>& mvec,
379 MachineCodeForInstruction& mcfi) const {
384 typedef TargetInstrInfo MachineInstrInfo;