1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class CalleeSavedInfo;
28 class MachineFunction;
30 class MachineLocation;
33 class TargetRegisterClass;
36 /// TargetRegisterDesc - This record contains all of the information known about
37 /// a particular register. The AliasSet field (if not null) contains a pointer
38 /// to a Zero terminated array of registers that this register aliases. This is
39 /// needed for architectures like X86 which have AL alias AX alias EAX.
40 /// Registers that this does not apply to simply should set this to null.
41 /// The SubRegs field is a zero terminated array of registers that are
42 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
43 /// The SuperRegs field is a zero terminated array of registers that are
44 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
47 struct TargetRegisterDesc {
48 const char *Name; // Assembly language name for the register
49 const unsigned *AliasSet; // Register Alias Set, described above
50 const unsigned *SubRegs; // Sub-register set, described above
51 const unsigned *ImmSubRegs; // Immediate sub-register set, described above
52 const unsigned *SuperRegs; // Super-register set, described above
55 class TargetRegisterClass {
57 typedef const unsigned* iterator;
58 typedef const unsigned* const_iterator;
60 typedef const MVT::ValueType* vt_iterator;
61 typedef const TargetRegisterClass* const * sc_iterator;
65 const vt_iterator VTs;
66 const sc_iterator SubClasses;
67 const sc_iterator SuperClasses;
68 const sc_iterator SubRegClasses;
69 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
70 const iterator RegsBegin, RegsEnd;
72 TargetRegisterClass(unsigned id,
73 const MVT::ValueType *vts,
74 const TargetRegisterClass * const *subcs,
75 const TargetRegisterClass * const *supcs,
76 const TargetRegisterClass * const *subregcs,
77 unsigned RS, unsigned Al, iterator RB, iterator RE)
78 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
79 SubRegClasses(subregcs),
80 RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
81 virtual ~TargetRegisterClass() {} // Allow subclasses
83 /// getID() - Return the register class ID number.
85 unsigned getID() const { return ID; }
87 /// begin/end - Return all of the registers in this class.
89 iterator begin() const { return RegsBegin; }
90 iterator end() const { return RegsEnd; }
92 /// getNumRegs - Return the number of registers in this class.
94 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
96 /// getRegister - Return the specified register in the class.
98 unsigned getRegister(unsigned i) const {
99 assert(i < getNumRegs() && "Register number out of range!");
103 /// contains - Return true if the specified register is included in this
105 bool contains(unsigned Reg) const {
106 for (iterator I = begin(), E = end(); I != E; ++I)
107 if (*I == Reg) return true;
111 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
113 bool hasType(MVT::ValueType vt) const {
114 for(int i = 0; VTs[i] != MVT::Other; ++i)
120 /// vt_begin / vt_end - Loop over all of the value types that can be
121 /// represented by values in this register class.
122 vt_iterator vt_begin() const {
126 vt_iterator vt_end() const {
128 while (*I != MVT::Other) ++I;
132 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
133 /// sub-register class of this TargetRegisterClass.
134 bool hasSubRegClass(const TargetRegisterClass *cs) const {
135 for (int i = 0; SubClasses[i] != NULL; ++i)
136 if (SubClasses[i] == cs)
141 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
142 /// this register class.
143 sc_iterator subclasses_begin() const {
147 sc_iterator subclasses_end() const {
148 sc_iterator I = SubClasses;
149 while (*I != NULL) ++I;
153 /// hasSuperRegClass - return true if the specified TargetRegisterClass is a
154 /// super-register class of this TargetRegisterClass.
155 bool hasSuperRegClass(const TargetRegisterClass *cs) const {
156 for (int i = 0; SuperClasses[i] != NULL; ++i)
157 if (SuperClasses[i] == cs)
162 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
163 /// of this register class.
164 sc_iterator superclasses_begin() const {
168 sc_iterator superclasses_end() const {
169 sc_iterator I = SuperClasses;
170 while (*I != NULL) ++I;
174 /// hasSubRegForClass - return true if the specified TargetRegisterClass is a
175 /// class of a sub-register class for this TargetRegisterClass.
176 bool hasSubRegForClass(const TargetRegisterClass *cs) const {
177 for (int i = 0; SubRegClasses[i] != NULL; ++i)
178 if (SubRegClasses[i] == cs)
183 /// hasClassForSubReg - return true if the specified TargetRegisterClass is a
184 /// class of a sub-register class for this TargetRegisterClass.
185 bool hasClassForSubReg(unsigned SubReg) const {
187 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
193 /// getClassForSubReg - return theTargetRegisterClass for the sub-register
194 /// at idx for this TargetRegisterClass.
195 sc_iterator getClassForSubReg(unsigned SubReg) const {
197 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
199 return &SubRegClasses[i];
203 /// subregclasses_begin / subregclasses_end - Loop over all of
204 /// the subregister classes of this register class.
205 sc_iterator subregclasses_begin() const {
206 return SubRegClasses;
209 sc_iterator subregclasses_end() const {
210 sc_iterator I = SubRegClasses;
211 while (*I != NULL) ++I;
215 /// allocation_order_begin/end - These methods define a range of registers
216 /// which specify the registers in this class that are valid to register
217 /// allocate, and the preferred order to allocate them in. For example,
218 /// callee saved registers should be at the end of the list, because it is
219 /// cheaper to allocate caller saved registers.
221 /// These methods take a MachineFunction argument, which can be used to tune
222 /// the allocatable registers based on the characteristics of the function.
223 /// One simple example is that the frame pointer register can be used if
224 /// frame-pointer-elimination is performed.
226 /// By default, these methods return all registers in the class.
228 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
231 virtual iterator allocation_order_end(const MachineFunction &MF) const {
237 /// getSize - Return the size of the register in bytes, which is also the size
238 /// of a stack slot allocated to hold a spilled copy of this register.
239 unsigned getSize() const { return RegSize; }
241 /// getAlignment - Return the minimum required alignment for a register of
243 unsigned getAlignment() const { return Alignment; }
247 /// MRegisterInfo base class - We assume that the target defines a static array
248 /// of TargetRegisterDesc objects that represent all of the machine registers
249 /// that the target has. As such, we simply have to track a pointer to this
250 /// array so that we can turn register number into a register descriptor.
252 class MRegisterInfo {
254 typedef const TargetRegisterClass * const * regclass_iterator;
256 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
257 unsigned NumRegs; // Number of entries in the array
259 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
261 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
263 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
264 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
265 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
266 virtual ~MRegisterInfo();
269 enum { // Define some target independent constants
270 /// NoRegister - This physical register is not a real target register. It
271 /// is useful as a sentinal.
274 /// FirstVirtualRegister - This is the first register number that is
275 /// considered to be a 'virtual' register, which is part of the SSA
276 /// namespace. This must be the same for all targets, which means that each
277 /// target is limited to 1024 registers.
278 FirstVirtualRegister = 1024
281 /// isPhysicalRegister - Return true if the specified register number is in
282 /// the physical register namespace.
283 static bool isPhysicalRegister(unsigned Reg) {
284 assert(Reg && "this is not a register!");
285 return Reg < FirstVirtualRegister;
288 /// isVirtualRegister - Return true if the specified register number is in
289 /// the virtual register namespace.
290 static bool isVirtualRegister(unsigned Reg) {
291 assert(Reg && "this is not a register!");
292 return Reg >= FirstVirtualRegister;
295 /// getAllocatableSet - Returns a bitset indexed by register number
296 /// indicating if a register is allocatable or not. If a register class is
297 /// specified, returns the subset for the class.
298 BitVector getAllocatableSet(MachineFunction &MF,
299 const TargetRegisterClass *RC = NULL) const;
301 const TargetRegisterDesc &operator[](unsigned RegNo) const {
302 assert(RegNo < NumRegs &&
303 "Attempting to access record for invalid register number!");
307 /// Provide a get method, equivalent to [], but more useful if we have a
308 /// pointer to this object.
310 const TargetRegisterDesc &get(unsigned RegNo) const {
311 return operator[](RegNo);
314 /// getAliasSet - Return the set of registers aliased by the specified
315 /// register, or a null list of there are none. The list returned is zero
318 const unsigned *getAliasSet(unsigned RegNo) const {
319 return get(RegNo).AliasSet;
322 /// getSubRegisters - Return the set of registers that are sub-registers of
323 /// the specified register, or a null list of there are none. The list
324 /// returned is zero terminated.
326 const unsigned *getSubRegisters(unsigned RegNo) const {
327 return get(RegNo).SubRegs;
330 /// getImmediateSubRegisters - Return the set of registers that are immediate
331 /// sub-registers of the specified register, or a null list of there are none.
332 /// The list returned is zero terminated.
334 const unsigned *getImmediateSubRegisters(unsigned RegNo) const {
335 return get(RegNo).ImmSubRegs;
338 /// getSuperRegisters - Return the set of registers that are super-registers
339 /// of the specified register, or a null list of there are none. The list
340 /// returned is zero terminated.
342 const unsigned *getSuperRegisters(unsigned RegNo) const {
343 return get(RegNo).SuperRegs;
346 /// getName - Return the symbolic target specific name for the specified
347 /// physical register.
348 const char *getName(unsigned RegNo) const {
349 return get(RegNo).Name;
352 /// getNumRegs - Return the number of registers this target has
353 /// (useful for sizing arrays holding per register information)
354 unsigned getNumRegs() const {
358 /// areAliases - Returns true if the two registers alias each other,
360 bool areAliases(unsigned regA, unsigned regB) const {
361 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
362 if (*Alias == regB) return true;
366 /// regsOverlap - Returns true if the two registers are equal or alias
367 /// each other. The registers may be virtual register.
368 bool regsOverlap(unsigned regA, unsigned regB) const {
372 if (isVirtualRegister(regA) || isVirtualRegister(regB))
374 return areAliases(regA, regB);
377 /// isSubRegister - Returns true if regB is a sub-register of regA.
379 bool isSubRegister(unsigned regA, unsigned regB) const {
380 for (const unsigned *SR = getSubRegisters(regA); *SR; ++SR)
381 if (*SR == regB) return true;
385 /// isSuperRegister - Returns true if regB is a super-register of regA.
387 bool isSuperRegister(unsigned regA, unsigned regB) const {
388 for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR)
389 if (*SR == regB) return true;
393 /// getCalleeSavedRegs - Return a null-terminated list of all of the
394 /// callee saved registers on this target. The register should be in the
395 /// order of desired callee-save stack frame offset. The first register is
396 /// closed to the incoming stack pointer if stack grows down, and vice versa.
397 virtual const unsigned* getCalleeSavedRegs() const = 0;
399 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
400 /// register classes to spill each callee saved register with. The order and
401 /// length of this list match the getCalleeSaveRegs() list.
402 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const =0;
404 /// getReservedRegs - Returns a bitset indexed by physical register number
405 /// indicating if a register is a special register that has particular uses and
406 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
407 /// register scavenger to determine what registers are free.
408 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
410 /// getSubReg - Returns the physical register number of sub-register "Index"
411 /// for physical register RegNo.
412 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
414 //===--------------------------------------------------------------------===//
415 // Register Class Information
418 /// Register class iterators
420 regclass_iterator regclass_begin() const { return RegClassBegin; }
421 regclass_iterator regclass_end() const { return RegClassEnd; }
423 unsigned getNumRegClasses() const {
424 return regclass_end()-regclass_begin();
427 /// getRegClass - Returns the register class associated with the enumeration
428 /// value. See class TargetOperandInfo.
429 const TargetRegisterClass *getRegClass(unsigned i) const {
430 assert(i <= getNumRegClasses() && "Register Class ID out of range");
431 return i ? RegClassBegin[i - 1] : NULL;
434 //===--------------------------------------------------------------------===//
435 // Interfaces used by the register allocator and stack frame
436 // manipulation passes to move data around between registers,
437 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
440 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved
441 /// registers and returns true if it isn't possible / profitable to do so by
442 /// issuing a series of store instructions via storeRegToStackSlot(). Returns
444 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
445 MachineBasicBlock::iterator MI,
446 const std::vector<CalleeSavedInfo> &CSI) const {
450 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
451 /// saved registers and returns true if it isn't possible / profitable to do
452 /// so by issuing a series of load instructions via loadRegToStackSlot().
453 /// Returns false otherwise.
454 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
455 MachineBasicBlock::iterator MI,
456 const std::vector<CalleeSavedInfo> &CSI) const {
460 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
461 MachineBasicBlock::iterator MI,
462 unsigned SrcReg, int FrameIndex,
463 const TargetRegisterClass *RC) const = 0;
465 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
466 MachineBasicBlock::iterator MI,
467 unsigned DestReg, int FrameIndex,
468 const TargetRegisterClass *RC) const = 0;
470 virtual void copyRegToReg(MachineBasicBlock &MBB,
471 MachineBasicBlock::iterator MI,
472 unsigned DestReg, unsigned SrcReg,
473 const TargetRegisterClass *RC) const = 0;
475 /// reMaterialize - Re-issue the specified 'original' instruction at the
476 /// specific location targeting a new destination register.
477 virtual void reMaterialize(MachineBasicBlock &MBB,
478 MachineBasicBlock::iterator MI,
480 const MachineInstr *Orig) const = 0;
482 /// foldMemoryOperand - Attempt to fold a load or store of the
483 /// specified stack slot into the specified machine instruction for
484 /// the specified operand. If this is possible, a new instruction
485 /// is returned with the specified operand folded, otherwise NULL is
486 /// returned. The client is responsible for removing the old
487 /// instruction and adding the new one in the instruction stream
488 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
490 int FrameIndex) const {
494 /// targetHandlesStackFrameRounding - Returns true if the target is responsible
495 /// for rounding up the stack frame (probably at emitPrologue time).
496 virtual bool targetHandlesStackFrameRounding() const {
500 /// requiresRegisterScavenging - returns true if the target requires (and
501 /// can make use of) the register scavenger.
502 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
506 /// hasFP - Return true if the specified function should have a dedicated frame
507 /// pointer register. For most targets this is true only if the function has
508 /// variable sized allocas or if frame pointer elimination is disabled.
509 virtual bool hasFP(const MachineFunction &MF) const = 0;
511 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
512 // not required, we reserve argument space for call sites in the function
513 // immediately on entry to the current function. This eliminates the need for
514 // add/sub sp brackets around call sites. Returns true if the call frame is
515 // included as part of the stack frame.
516 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
520 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
521 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
522 /// targets use pseudo instructions in order to abstract away the difference
523 /// between operating with a frame pointer and operating without, through the
524 /// use of these two instructions.
526 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
527 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
530 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
531 /// code insertion to eliminate call frame setup and destroy pseudo
532 /// instructions (but only if the Target is using them). It is responsible
533 /// for eliminating these instructions, replacing them with concrete
534 /// instructions. This method need only be implemented if using call frame
535 /// setup/destroy pseudo instructions.
538 eliminateCallFramePseudoInstr(MachineFunction &MF,
539 MachineBasicBlock &MBB,
540 MachineBasicBlock::iterator MI) const {
541 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
542 "eliminateCallFramePseudoInstr must be implemented if using"
543 " call frame setup/destroy pseudo instructions!");
544 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
547 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
548 /// before PrologEpilogInserter scans the physical registers used to determine
549 /// what callee saved registers should be spilled. This method is optional.
550 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
551 RegScavenger *RS = NULL) const {
555 /// processFunctionBeforeFrameFinalized - This method is called immediately
556 /// before the specified functions frame layout (MF.getFrameInfo()) is
557 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
558 /// replaced with direct constants. This method is optional.
560 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
563 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
564 /// frame indices from instructions which may use them. The instruction
565 /// referenced by the iterator contains an MO_FrameIndex operand which must be
566 /// eliminated by this method. This method may modify or replace the
567 /// specified instruction, as long as it keeps the iterator pointing the the
568 /// finished product. SPAdj is the SP adjustment due to call frame setup
569 /// instruction. The return value is the number of instructions added to
570 /// (negative if removed from) the basic block.
572 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
573 int SPAdj, RegScavenger *RS=NULL) const = 0;
575 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
576 /// the function. The return value is the number of instructions
577 /// added to (negative if removed from) the basic block (entry for prologue).
579 virtual void emitPrologue(MachineFunction &MF) const = 0;
580 virtual void emitEpilogue(MachineFunction &MF,
581 MachineBasicBlock &MBB) const = 0;
583 //===--------------------------------------------------------------------===//
584 /// Debug information queries.
586 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
587 /// number. Returns -1 if there is no equivalent value.
588 virtual int getDwarfRegNum(unsigned RegNum) const = 0;
590 /// getFrameRegister - This method should return the register used as a base
591 /// for values allocated in the current stack frame.
592 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
594 /// getRARegister - This method should return the register where the return
595 /// address can be found.
596 virtual unsigned getRARegister() const = 0;
598 /// getLocation - This method should return the actual location of a frame
599 /// variable given the frame index. The location is returned in ML.
600 /// Subclasses should override this method for special handling of frame
601 /// variables and call MRegisterInfo::getLocation for the default action.
602 virtual void getLocation(MachineFunction &MF, unsigned Index,
603 MachineLocation &ML) const;
605 /// getInitialFrameState - Returns a list of machine moves that are assumed
606 /// on entry to all functions. Note that LabelID is ignored (assumed to be
607 /// the beginning of the function.)
608 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
611 // This is useful when building IndexedMaps keyed on virtual registers
612 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
613 unsigned operator()(unsigned Reg) const {
614 return Reg - MRegisterInfo::FirstVirtualRegister;
618 } // End llvm namespace