1 //=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_MC_MCREGISTERINFO_H
17 #define LLVM_MC_MCREGISTERINFO_H
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/Support/ErrorHandling.h"
25 /// MCRegisterClass - Base class of TargetRegisterClass.
26 class MCRegisterClass {
28 typedef const unsigned* iterator;
29 typedef const unsigned* const_iterator;
33 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
35 const bool Allocatable;
36 const iterator RegsBegin, RegsEnd;
37 const unsigned char *const RegSet;
38 const unsigned RegSetSize;
40 MCRegisterClass(unsigned id, const char *name,
41 unsigned RS, unsigned Al, int CC, bool Allocable,
42 iterator RB, iterator RE, const unsigned char *Bits,
44 : ID(id), Name(name), RegSize(RS), Alignment(Al), CopyCost(CC),
45 Allocatable(Allocable), RegsBegin(RB), RegsEnd(RE), RegSet(Bits),
46 RegSetSize(NumBytes) {
47 for (iterator i = RegsBegin; i != RegsEnd; ++i)
48 assert(contains(*i) && "Bit field corrupted.");
51 /// getID() - Return the register class ID number.
53 unsigned getID() const { return ID; }
55 /// getName() - Return the register class name for debugging.
57 const char *getName() const { return Name; }
59 /// begin/end - Return all of the registers in this class.
61 iterator begin() const { return RegsBegin; }
62 iterator end() const { return RegsEnd; }
64 /// getNumRegs - Return the number of registers in this class.
66 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
68 /// getRegister - Return the specified register in the class.
70 unsigned getRegister(unsigned i) const {
71 assert(i < getNumRegs() && "Register number out of range!");
75 /// contains - Return true if the specified register is included in this
76 /// register class. This does not include virtual registers.
77 bool contains(unsigned Reg) const {
78 unsigned InByte = Reg % 8;
79 unsigned Byte = Reg / 8;
80 if (Byte >= RegSetSize)
82 return (RegSet[Byte] & (1 << InByte)) != 0;
85 /// contains - Return true if both registers are in this class.
86 bool contains(unsigned Reg1, unsigned Reg2) const {
87 return contains(Reg1) && contains(Reg2);
90 /// getSize - Return the size of the register in bytes, which is also the size
91 /// of a stack slot allocated to hold a spilled copy of this register.
92 unsigned getSize() const { return RegSize; }
94 /// getAlignment - Return the minimum required alignment for a register of
96 unsigned getAlignment() const { return Alignment; }
98 /// getCopyCost - Return the cost of copying a value between two registers in
99 /// this class. A negative number means the register class is very expensive
100 /// to copy e.g. status flag register classes.
101 int getCopyCost() const { return CopyCost; }
103 /// isAllocatable - Return true if this register class may be used to create
104 /// virtual registers.
105 bool isAllocatable() const { return Allocatable; }
108 /// MCRegisterDesc - This record contains all of the information known about
109 /// a particular register. The Overlaps field contains a pointer to a zero
110 /// terminated array of registers that this register aliases, starting with
111 /// itself. This is needed for architectures like X86 which have AL alias AX
112 /// alias EAX. The SubRegs field is a zero terminated array of registers that
113 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers of
114 /// AX. The SuperRegs field is a zero terminated array of registers that are
115 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
118 struct MCRegisterDesc {
119 const char *Name; // Printable name for the reg (for debugging)
120 const unsigned *Overlaps; // Overlapping registers, described above
121 const unsigned *SubRegs; // Sub-register set, described above
122 const unsigned *SuperRegs; // Super-register set, described above
125 /// MCRegisterInfo base class - We assume that the target defines a static
126 /// array of MCRegisterDesc objects that represent all of the machine
127 /// registers that the target has. As such, we simply have to track a pointer
128 /// to this array so that we can turn register number into a register
131 /// Note this class is designed to be a base class of TargetRegisterInfo, which
132 /// is the interface used by codegen. However, specific targets *should never*
133 /// specialize this class. MCRegisterInfo should only contain getters to access
134 /// TableGen generated physical register data. It must not be extended with
137 class MCRegisterInfo {
139 typedef const MCRegisterClass *regclass_iterator;
141 const MCRegisterDesc *Desc; // Pointer to the descriptor array
142 unsigned NumRegs; // Number of entries in the array
143 unsigned RAReg; // Return address register
144 const MCRegisterClass *Classes; // Pointer to the regclass array
145 unsigned NumClasses; // Number of entries in the array
146 DenseMap<unsigned, int> L2DwarfRegs; // LLVM to Dwarf regs mapping
147 DenseMap<unsigned, int> EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
148 DenseMap<unsigned, unsigned> Dwarf2LRegs; // Dwarf to LLVM regs mapping
149 DenseMap<unsigned, unsigned> EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
150 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
153 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
154 /// auto-generated routines. *DO NOT USE*.
155 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
156 const MCRegisterClass *C, unsigned NC) {
164 /// mapLLVMRegToDwarfReg - Used to initialize LLVM register to Dwarf
165 /// register number mapping. Called by TableGen auto-generated routines.
167 void mapLLVMRegToDwarfReg(unsigned LLVMReg, int DwarfReg, bool isEH) {
169 EHL2DwarfRegs[LLVMReg] = DwarfReg;
171 L2DwarfRegs[LLVMReg] = DwarfReg;
174 /// mapDwarfRegToLLVMReg - Used to initialize Dwarf register to LLVM
175 /// register number mapping. Called by TableGen auto-generated routines.
177 void mapDwarfRegToLLVMReg(unsigned DwarfReg, unsigned LLVMReg, bool isEH) {
179 EHDwarf2LRegs[DwarfReg] = LLVMReg;
181 Dwarf2LRegs[DwarfReg] = LLVMReg;
184 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
185 /// number mapping. By default the SEH register number is just the same
186 /// as the LLVM register number.
187 /// FIXME: TableGen these numbers. Currently this requires target specific
188 /// initialization code.
189 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
190 L2SEHRegs[LLVMReg] = SEHReg;
193 /// getRARegister - This method should return the register where the return
194 /// address can be found.
195 unsigned getRARegister() const {
199 const MCRegisterDesc &operator[](unsigned RegNo) const {
200 assert(RegNo < NumRegs &&
201 "Attempting to access record for invalid register number!");
205 /// Provide a get method, equivalent to [], but more useful if we have a
206 /// pointer to this object.
208 const MCRegisterDesc &get(unsigned RegNo) const {
209 return operator[](RegNo);
212 /// getAliasSet - Return the set of registers aliased by the specified
213 /// register, or a null list of there are none. The list returned is zero
216 const unsigned *getAliasSet(unsigned RegNo) const {
217 // The Overlaps set always begins with Reg itself.
218 return get(RegNo).Overlaps + 1;
221 /// getOverlaps - Return a list of registers that overlap Reg, including
222 /// itself. This is the same as the alias set except Reg is included in the
224 /// These are exactly the registers in { x | regsOverlap(x, Reg) }.
226 const unsigned *getOverlaps(unsigned RegNo) const {
227 return get(RegNo).Overlaps;
230 /// getSubRegisters - Return the list of registers that are sub-registers of
231 /// the specified register, or a null list of there are none. The list
232 /// returned is zero terminated and sorted according to super-sub register
233 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
235 const unsigned *getSubRegisters(unsigned RegNo) const {
236 return get(RegNo).SubRegs;
239 /// getSuperRegisters - Return the list of registers that are super-registers
240 /// of the specified register, or a null list of there are none. The list
241 /// returned is zero terminated and sorted according to super-sub register
242 /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX.
244 const unsigned *getSuperRegisters(unsigned RegNo) const {
245 return get(RegNo).SuperRegs;
248 /// getName - Return the human-readable symbolic target-specific name for the
249 /// specified physical register.
250 const char *getName(unsigned RegNo) const {
251 return get(RegNo).Name;
254 /// getNumRegs - Return the number of registers this target has (useful for
255 /// sizing arrays holding per register information)
256 unsigned getNumRegs() const {
260 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
261 /// number. Returns -1 if there is no equivalent value. The second
262 /// parameter allows targets to use different numberings for EH info and
264 int getDwarfRegNum(unsigned RegNum, bool isEH) const {
265 const DenseMap<unsigned, int> &M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
266 const DenseMap<unsigned, int>::const_iterator I = M.find(RegNum);
267 if (I == M.end()) return -1;
271 /// getLLVMRegNum - Map a dwarf register back to a target register.
273 int getLLVMRegNum(unsigned RegNum, bool isEH) const {
274 const DenseMap<unsigned, unsigned> &M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
275 const DenseMap<unsigned, unsigned>::const_iterator I = M.find(RegNum);
277 llvm_unreachable("Invalid RegNum");
282 /// getSEHRegNum - Map a target register to an equivalent SEH register
283 /// number. Returns LLVM register number if there is no equivalent value.
284 int getSEHRegNum(unsigned RegNum) const {
285 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum);
286 if (I == L2SEHRegs.end()) return (int)RegNum;
290 regclass_iterator regclass_begin() const { return Classes; }
291 regclass_iterator regclass_end() const { return Classes+NumClasses; }
293 unsigned getNumRegClasses() const {
294 return (unsigned)(regclass_end()-regclass_begin());
297 /// getRegClass - Returns the register class associated with the enumeration
298 /// value. See class MCOperandInfo.
299 const MCRegisterClass getRegClass(unsigned i) const {
300 assert(i < getNumRegClasses() && "Register Class ID out of range");
305 } // End llvm namespace