1 //===-- llvm/Mc/McInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MCOperandInfo and MCInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_MC_MCINSTRDESC_H
16 #define LLVM_MC_MCINSTRDESC_H
18 #include "llvm/Support/DataTypes.h"
22 //===----------------------------------------------------------------------===//
23 // Machine Operand Flags and Description
24 //===----------------------------------------------------------------------===//
27 // Operand constraints
28 enum OperandConstraint {
29 TIED_TO = 0, // Must be allocated the same register as.
30 EARLY_CLOBBER // Operand is an early clobber register operand
33 /// OperandFlags - These are flags set on operands, but should be considered
34 /// private, all access should go through the MCOperandInfo accessors.
35 /// See the accessors for a description of what these are.
37 LookupPtrRegClass = 0,
42 /// Operand Type - Operands are tagged with one of the values of this enum.
52 /// MCOperandInfo - This holds information about one operand of a machine
53 /// instruction, indicating the register class for register operands, etc.
57 /// RegClass - This specifies the register class enumeration of the operand
58 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
59 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
60 /// get a dynamic register class.
63 /// Flags - These are flags from the MCOI::OperandFlags enum.
66 /// Lower 16 bits are used to specify which constraints are set. The higher 16
67 /// bits are used to specify the value of constraints (4 bits each).
70 /// OperandType - Information about the type of the operand.
71 MCOI::OperandType OperandType;
72 /// Currently no other information.
74 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
75 /// requires a callback to look up its register class.
76 bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);}
78 /// isPredicate - Set if this is one of the operands that made up of
79 /// the predicate operand that controls an isPredicable() instruction.
80 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
82 /// isOptionalDef - Set if this operand is a optional def.
84 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
88 //===----------------------------------------------------------------------===//
89 // Machine Instruction Flags and Description
90 //===----------------------------------------------------------------------===//
92 /// MCInstrDesc flags - These should be considered private to the
93 /// implementation of the MCInstrDesc class. Clients should use the predicate
94 /// methods on MCInstrDesc, not use these directly. These all correspond to
95 /// bitfields in the MCInstrDesc::Flags field.
116 UnmodeledSideEffects,
128 /// MCInstrDesc - Describe properties that are true of each instruction in the
129 /// target description file. This captures information about side effects,
130 /// register use and many other things. There is one instance of this struct
131 /// for each target instruction class, and the MachineInstr class points to
132 /// this struct directly to describe itself.
135 unsigned short Opcode; // The opcode number
136 unsigned short NumOperands; // Num of args (may be more if variable_ops)
137 unsigned short NumDefs; // Num of args that are definitions
138 unsigned short SchedClass; // enum identifying instr sched class
139 unsigned short Size; // Number of bytes in encoding.
140 const char * Name; // Name of the instruction record in td file
141 unsigned Flags; // Flags identifying machine instr class
142 uint64_t TSFlags; // Target Specific Flag values
143 const unsigned *ImplicitUses; // Registers implicitly read by this instr
144 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
145 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
147 /// getOperandConstraint - Returns the value of the specific constraint if
148 /// it is set. Returns -1 if it is not set.
149 int getOperandConstraint(unsigned OpNum,
150 MCOI::OperandConstraint Constraint) const {
151 if (OpNum < NumOperands &&
152 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
153 unsigned Pos = 16 + Constraint * 4;
154 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
159 /// getOpcode - Return the opcode number for this descriptor.
160 unsigned getOpcode() const {
164 /// getName - Return the name of the record in the .td file for this
165 /// instruction, for example "ADD8ri".
166 const char *getName() const {
170 /// getNumOperands - Return the number of declared MachineOperands for this
171 /// MachineInstruction. Note that variadic (isVariadic() returns true)
172 /// instructions may have additional operands at the end of the list, and note
173 /// that the machine instruction may include implicit register def/uses as
175 unsigned getNumOperands() const {
179 /// getNumDefs - Return the number of MachineOperands that are register
180 /// definitions. Register definitions always occur at the start of the
181 /// machine operand list. This is the number of "outs" in the .td file,
182 /// and does not include implicit defs.
183 unsigned getNumDefs() const {
187 /// isVariadic - Return true if this instruction can have a variable number of
188 /// operands. In this case, the variable operands will be after the normal
189 /// operands but before the implicit definitions and uses (if any are
191 bool isVariadic() const {
192 return Flags & (1 << MCID::Variadic);
195 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
196 /// ARM instructions which can set condition code if 's' bit is set.
197 bool hasOptionalDef() const {
198 return Flags & (1 << MCID::HasOptionalDef);
201 /// getImplicitUses - Return a list of registers that are potentially
202 /// read by any instance of this machine instruction. For example, on X86,
203 /// the "adc" instruction adds two register operands and adds the carry bit in
204 /// from the flags register. In this case, the instruction is marked as
205 /// implicitly reading the flags. Likewise, the variable shift instruction on
206 /// X86 is marked as implicitly reading the 'CL' register, which it always
209 /// This method returns null if the instruction has no implicit uses.
210 const unsigned *getImplicitUses() const {
214 /// getNumImplicitUses - Return the number of implicit uses this instruction
216 unsigned getNumImplicitUses() const {
217 if (ImplicitUses == 0) return 0;
219 for (; ImplicitUses[i]; ++i) /*empty*/;
223 /// getImplicitDefs - Return a list of registers that are potentially
224 /// written by any instance of this machine instruction. For example, on X86,
225 /// many instructions implicitly set the flags register. In this case, they
226 /// are marked as setting the FLAGS. Likewise, many instructions always
227 /// deposit their result in a physical register. For example, the X86 divide
228 /// instruction always deposits the quotient and remainder in the EAX/EDX
229 /// registers. For that instruction, this will return a list containing the
230 /// EAX/EDX/EFLAGS registers.
232 /// This method returns null if the instruction has no implicit defs.
233 const unsigned *getImplicitDefs() const {
237 /// getNumImplicitDefs - Return the number of implicit defs this instruction
239 unsigned getNumImplicitDefs() const {
240 if (ImplicitDefs == 0) return 0;
242 for (; ImplicitDefs[i]; ++i) /*empty*/;
246 /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
247 /// uses the specified physical register.
248 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
249 if (const unsigned *ImpUses = ImplicitUses)
250 for (; *ImpUses; ++ImpUses)
251 if (*ImpUses == Reg) return true;
255 /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
256 /// defines the specified physical register.
257 bool hasImplicitDefOfPhysReg(unsigned Reg) const {
258 if (const unsigned *ImpDefs = ImplicitDefs)
259 for (; *ImpDefs; ++ImpDefs)
260 if (*ImpDefs == Reg) return true;
264 /// getSchedClass - Return the scheduling class for this instruction. The
265 /// scheduling class is an index into the InstrItineraryData table. This
266 /// returns zero if there is no known scheduling information for the
269 unsigned getSchedClass() const {
273 /// getSize - Return the number of bytes in the encoding of this instruction,
274 /// or zero if the encoding size cannot be known from the opcode.
275 unsigned getSize() const {
279 /// isPseudo - Return true if this is a pseudo instruction that doesn't
280 /// correspond to a real machine instruction.
282 bool isPseudo() const {
283 return Flags & (1 << MCID::Pseudo);
286 bool isReturn() const {
287 return Flags & (1 << MCID::Return);
290 bool isCall() const {
291 return Flags & (1 << MCID::Call);
294 /// isBarrier - Returns true if the specified instruction stops control flow
295 /// from executing the instruction immediately following it. Examples include
296 /// unconditional branches and return instructions.
297 bool isBarrier() const {
298 return Flags & (1 << MCID::Barrier);
301 /// findFirstPredOperandIdx() - Find the index of the first operand in the
302 /// operand list that is used to represent the predicate. It returns -1 if
304 int findFirstPredOperandIdx() const {
305 if (isPredicable()) {
306 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
307 if (OpInfo[i].isPredicate())
313 /// isTerminator - Returns true if this instruction part of the terminator for
314 /// a basic block. Typically this is things like return and branch
317 /// Various passes use this to insert code into the bottom of a basic block,
318 /// but before control flow occurs.
319 bool isTerminator() const {
320 return Flags & (1 << MCID::Terminator);
323 /// isBranch - Returns true if this is a conditional, unconditional, or
324 /// indirect branch. Predicates below can be used to discriminate between
325 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
326 /// get more information.
327 bool isBranch() const {
328 return Flags & (1 << MCID::Branch);
331 /// isIndirectBranch - Return true if this is an indirect branch, such as a
332 /// branch through a register.
333 bool isIndirectBranch() const {
334 return Flags & (1 << MCID::IndirectBranch);
337 /// isConditionalBranch - Return true if this is a branch which may fall
338 /// through to the next instruction or may transfer control flow to some other
339 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
340 /// information about this branch.
341 bool isConditionalBranch() const {
342 return isBranch() & !isBarrier() & !isIndirectBranch();
345 /// isUnconditionalBranch - Return true if this is a branch which always
346 /// transfers control flow to some other block. The
347 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
348 /// about this branch.
349 bool isUnconditionalBranch() const {
350 return isBranch() & isBarrier() & !isIndirectBranch();
353 // isPredicable - Return true if this instruction has a predicate operand that
354 // controls execution. It may be set to 'always', or may be set to other
355 /// values. There are various methods in TargetInstrInfo that can be used to
356 /// control and modify the predicate in this instruction.
357 bool isPredicable() const {
358 return Flags & (1 << MCID::Predicable);
361 /// isCompare - Return true if this instruction is a comparison.
362 bool isCompare() const {
363 return Flags & (1 << MCID::Compare);
366 /// isMoveImmediate - Return true if this instruction is a move immediate
367 /// (including conditional moves) instruction.
368 bool isMoveImmediate() const {
369 return Flags & (1 << MCID::MoveImm);
372 /// isBitcast - Return true if this instruction is a bitcast instruction.
374 bool isBitcast() const {
375 return Flags & (1 << MCID::Bitcast);
378 /// isNotDuplicable - Return true if this instruction cannot be safely
379 /// duplicated. For example, if the instruction has a unique labels attached
380 /// to it, duplicating it would cause multiple definition errors.
381 bool isNotDuplicable() const {
382 return Flags & (1 << MCID::NotDuplicable);
385 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
386 /// which must be filled by the code generator.
387 bool hasDelaySlot() const {
388 return Flags & (1 << MCID::DelaySlot);
391 /// canFoldAsLoad - Return true for instructions that can be folded as
392 /// memory operands in other instructions. The most common use for this
393 /// is instructions that are simple loads from memory that don't modify
394 /// the loaded value in any way, but it can also be used for instructions
395 /// that can be expressed as constant-pool loads, such as V_SETALLONES
396 /// on x86, to allow them to be folded when it is beneficial.
397 /// This should only be set on instructions that return a value in their
398 /// only virtual register definition.
399 bool canFoldAsLoad() const {
400 return Flags & (1 << MCID::FoldableAsLoad);
403 //===--------------------------------------------------------------------===//
404 // Side Effect Analysis
405 //===--------------------------------------------------------------------===//
407 /// mayLoad - Return true if this instruction could possibly read memory.
408 /// Instructions with this flag set are not necessarily simple load
409 /// instructions, they may load a value and modify it, for example.
410 bool mayLoad() const {
411 return Flags & (1 << MCID::MayLoad);
415 /// mayStore - Return true if this instruction could possibly modify memory.
416 /// Instructions with this flag set are not necessarily simple store
417 /// instructions, they may store a modified value based on their operands, or
418 /// may not actually modify anything, for example.
419 bool mayStore() const {
420 return Flags & (1 << MCID::MayStore);
423 /// hasUnmodeledSideEffects - Return true if this instruction has side
424 /// effects that are not modeled by other flags. This does not return true
425 /// for instructions whose effects are captured by:
427 /// 1. Their operand list and implicit definition/use list. Register use/def
428 /// info is explicit for instructions.
429 /// 2. Memory accesses. Use mayLoad/mayStore.
430 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
432 /// Examples of side effects would be modifying 'invisible' machine state like
433 /// a control register, flushing a cache, modifying a register invisible to
436 bool hasUnmodeledSideEffects() const {
437 return Flags & (1 << MCID::UnmodeledSideEffects);
440 //===--------------------------------------------------------------------===//
441 // Flags that indicate whether an instruction can be modified by a method.
442 //===--------------------------------------------------------------------===//
444 /// isCommutable - Return true if this may be a 2- or 3-address
445 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
446 /// result if Y and Z are exchanged. If this flag is set, then the
447 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
450 /// Note that this flag may be set on instructions that are only commutable
451 /// sometimes. In these cases, the call to commuteInstruction will fail.
452 /// Also note that some instructions require non-trivial modification to
454 bool isCommutable() const {
455 return Flags & (1 << MCID::Commutable);
458 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
459 /// which can be changed into a 3-address instruction if needed. Doing this
460 /// transformation can be profitable in the register allocator, because it
461 /// means that the instruction can use a 2-address form if possible, but
462 /// degrade into a less efficient form if the source and dest register cannot
463 /// be assigned to the same register. For example, this allows the x86
464 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
465 /// is the same speed as the shift but has bigger code size.
467 /// If this returns true, then the target must implement the
468 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
469 /// is allowed to fail if the transformation isn't valid for this specific
470 /// instruction (e.g. shl reg, 4 on x86).
472 bool isConvertibleTo3Addr() const {
473 return Flags & (1 << MCID::ConvertibleTo3Addr);
476 /// usesCustomInsertionHook - Return true if this instruction requires
477 /// custom insertion support when the DAG scheduler is inserting it into a
478 /// machine basic block. If this is true for the instruction, it basically
479 /// means that it is a pseudo instruction used at SelectionDAG time that is
480 /// expanded out into magic code by the target when MachineInstrs are formed.
482 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
483 /// is used to insert this into the MachineBasicBlock.
484 bool usesCustomInsertionHook() const {
485 return Flags & (1 << MCID::UsesCustomInserter);
488 /// hasPostISelHook - Return true if this instruction requires *adjustment*
489 /// after instruction selection by calling a target hook. For example, this
490 /// can be used to fill in ARM 's' optional operand depending on whether
491 /// the conditional flag register is used.
492 bool hasPostISelHook() const {
493 return Flags & (1 << MCID::HasPostISelHook);
496 /// isRematerializable - Returns true if this instruction is a candidate for
497 /// remat. This flag is deprecated, please don't use it anymore. If this
498 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
499 /// verify the instruction is really rematable.
500 bool isRematerializable() const {
501 return Flags & (1 << MCID::Rematerializable);
504 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
505 /// less) than a move instruction. This is useful during certain types of
506 /// optimizations (e.g., remat during two-address conversion or machine licm)
507 /// where we would like to remat or hoist the instruction, but not if it costs
508 /// more than moving the instruction into the appropriate register. Note, we
509 /// are not marking copies from and to the same register class with this flag.
510 bool isAsCheapAsAMove() const {
511 return Flags & (1 << MCID::CheapAsAMove);
514 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
515 /// have special register allocation requirements that are not captured by the
516 /// operand register classes. e.g. ARM::STRD's two source registers must be an
517 /// even / odd pair, ARM::STM registers have to be in ascending order.
518 /// Post-register allocation passes should not attempt to change allocations
519 /// for sources of instructions with this flag.
520 bool hasExtraSrcRegAllocReq() const {
521 return Flags & (1 << MCID::ExtraSrcRegAllocReq);
524 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
525 /// have special register allocation requirements that are not captured by the
526 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
527 /// even / odd pair, ARM::LDM registers have to be in ascending order.
528 /// Post-register allocation passes should not attempt to change allocations
529 /// for definitions of instructions with this flag.
530 bool hasExtraDefRegAllocReq() const {
531 return Flags & (1 << MCID::ExtraDefRegAllocReq);
535 } // end namespace llvm