1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MCOperandInfo and MCInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_MC_MCINSTRDESC_H
16 #define LLVM_MC_MCINSTRDESC_H
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/DataTypes.h"
25 //===----------------------------------------------------------------------===//
26 // Machine Operand Flags and Description
27 //===----------------------------------------------------------------------===//
30 // Operand constraints
31 enum OperandConstraint {
32 TIED_TO = 0, // Must be allocated the same register as.
33 EARLY_CLOBBER // Operand is an early clobber register operand
36 /// OperandFlags - These are flags set on operands, but should be considered
37 /// private, all access should go through the MCOperandInfo accessors.
38 /// See the accessors for a description of what these are.
40 LookupPtrRegClass = 0,
45 /// Operand Type - Operands are tagged with one of the values of this enum.
55 /// MCOperandInfo - This holds information about one operand of a machine
56 /// instruction, indicating the register class for register operands, etc.
60 /// RegClass - This specifies the register class enumeration of the operand
61 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
62 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
63 /// get a dynamic register class.
66 /// Flags - These are flags from the MCOI::OperandFlags enum.
69 /// OperandType - Information about the type of the operand.
72 /// Lower 16 bits are used to specify which constraints are set. The higher 16
73 /// bits are used to specify the value of constraints (4 bits each).
75 /// Currently no other information.
77 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
78 /// requires a callback to look up its register class.
79 bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);}
81 /// isPredicate - Set if this is one of the operands that made up of
82 /// the predicate operand that controls an isPredicable() instruction.
83 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
85 /// isOptionalDef - Set if this operand is a optional def.
87 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
91 //===----------------------------------------------------------------------===//
92 // Machine Instruction Flags and Description
93 //===----------------------------------------------------------------------===//
95 /// MCInstrDesc flags - These should be considered private to the
96 /// implementation of the MCInstrDesc class. Clients should use the predicate
97 /// methods on MCInstrDesc, not use these directly. These all correspond to
98 /// bitfields in the MCInstrDesc::Flags field.
120 UnmodeledSideEffects,
133 /// MCInstrDesc - Describe properties that are true of each instruction in the
134 /// target description file. This captures information about side effects,
135 /// register use and many other things. There is one instance of this struct
136 /// for each target instruction class, and the MachineInstr class points to
137 /// this struct directly to describe itself.
140 unsigned short Opcode; // The opcode number
141 unsigned short NumOperands; // Num of args (may be more if variable_ops)
142 unsigned short NumDefs; // Num of args that are definitions
143 unsigned short SchedClass; // enum identifying instr sched class
144 unsigned short Size; // Number of bytes in encoding.
145 unsigned Flags; // Flags identifying machine instr class
146 uint64_t TSFlags; // Target Specific Flag values
147 const uint16_t *ImplicitUses; // Registers implicitly read by this instr
148 const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
149 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
150 uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any
151 // A complex method to determine is a certain is deprecated or not, and return
152 // the reason for deprecation.
153 bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);
155 /// \brief Returns the value of the specific constraint if
156 /// it is set. Returns -1 if it is not set.
157 int getOperandConstraint(unsigned OpNum,
158 MCOI::OperandConstraint Constraint) const {
159 if (OpNum < NumOperands &&
160 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
161 unsigned Pos = 16 + Constraint * 4;
162 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
167 /// \brief Returns true if a certain instruction is deprecated and if so
168 /// returns the reason in \p Info.
169 bool getDeprecatedInfo(MCInst &MI, MCSubtargetInfo &STI,
170 std::string &Info) const {
171 if (ComplexDeprecationInfo)
172 return ComplexDeprecationInfo(MI, STI, Info);
173 if ((DeprecatedFeatureMask & STI.getFeatureBits()) != 0) {
174 // FIXME: it would be nice to include the subtarget feature here.
181 /// \brief Return the opcode number for this descriptor.
182 unsigned getOpcode() const {
186 /// \brief Return the number of declared MachineOperands for this
187 /// MachineInstruction. Note that variadic (isVariadic() returns true)
188 /// instructions may have additional operands at the end of the list, and note
189 /// that the machine instruction may include implicit register def/uses as
191 unsigned getNumOperands() const {
195 /// \brief Return the number of MachineOperands that are register
196 /// definitions. Register definitions always occur at the start of the
197 /// machine operand list. This is the number of "outs" in the .td file,
198 /// and does not include implicit defs.
199 unsigned getNumDefs() const {
203 /// \brief Return flags of this instruction.
204 unsigned getFlags() const { return Flags; }
206 /// \brief Return true if this instruction can have a variable number of
207 /// operands. In this case, the variable operands will be after the normal
208 /// operands but before the implicit definitions and uses (if any are
210 bool isVariadic() const {
211 return Flags & (1 << MCID::Variadic);
214 /// \brief Set if this instruction has an optional definition, e.g.
215 /// ARM instructions which can set condition code if 's' bit is set.
216 bool hasOptionalDef() const {
217 return Flags & (1 << MCID::HasOptionalDef);
220 /// \brief Return true if this is a pseudo instruction that doesn't
221 /// correspond to a real machine instruction.
223 bool isPseudo() const {
224 return Flags & (1 << MCID::Pseudo);
227 /// \brief Return true if the instruction is a return.
228 bool isReturn() const {
229 return Flags & (1 << MCID::Return);
232 /// \brief Return true if the instruction is a call.
233 bool isCall() const {
234 return Flags & (1 << MCID::Call);
237 /// \brief Returns true if the specified instruction stops control flow
238 /// from executing the instruction immediately following it. Examples include
239 /// unconditional branches and return instructions.
240 bool isBarrier() const {
241 return Flags & (1 << MCID::Barrier);
244 /// \brief Returns true if this instruction part of the terminator for
245 /// a basic block. Typically this is things like return and branch
248 /// Various passes use this to insert code into the bottom of a basic block,
249 /// but before control flow occurs.
250 bool isTerminator() const {
251 return Flags & (1 << MCID::Terminator);
254 /// \brief Returns true if this is a conditional, unconditional, or
255 /// indirect branch. Predicates below can be used to discriminate between
256 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
257 /// get more information.
258 bool isBranch() const {
259 return Flags & (1 << MCID::Branch);
262 /// \brief Return true if this is an indirect branch, such as a
263 /// branch through a register.
264 bool isIndirectBranch() const {
265 return Flags & (1 << MCID::IndirectBranch);
268 /// \brief Return true if this is a branch which may fall
269 /// through to the next instruction or may transfer control flow to some other
270 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
271 /// information about this branch.
272 bool isConditionalBranch() const {
273 return isBranch() & !isBarrier() & !isIndirectBranch();
276 /// \brief Return true if this is a branch which always
277 /// transfers control flow to some other block. The
278 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
279 /// about this branch.
280 bool isUnconditionalBranch() const {
281 return isBranch() & isBarrier() & !isIndirectBranch();
284 /// \brief Return true if this is a branch or an instruction which directly
285 /// writes to the program counter. Considered 'may' affect rather than
286 /// 'does' affect as things like predication are not taken into account.
287 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const {
288 if (isBranch() || isCall() || isReturn() || isIndirectBranch())
290 unsigned PC = RI.getProgramCounter();
293 if (hasDefOfPhysReg(MI, PC, RI))
295 // A variadic instruction may define PC in the variable operand list.
296 // There's currently no indication of which entries in a variable
297 // list are defs and which are uses. While that's the case, this function
298 // needs to assume they're defs in order to be conservatively correct.
299 for (int i = NumOperands, e = MI.getNumOperands(); i != e; ++i) {
300 if (MI.getOperand(i).isReg() &&
301 RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
307 /// \brief Return true if this instruction has a predicate operand
308 /// that controls execution. It may be set to 'always', or may be set to other
309 /// values. There are various methods in TargetInstrInfo that can be used to
310 /// control and modify the predicate in this instruction.
311 bool isPredicable() const {
312 return Flags & (1 << MCID::Predicable);
315 /// \brief Return true if this instruction is a comparison.
316 bool isCompare() const {
317 return Flags & (1 << MCID::Compare);
320 /// \brief Return true if this instruction is a move immediate
321 /// (including conditional moves) instruction.
322 bool isMoveImmediate() const {
323 return Flags & (1 << MCID::MoveImm);
326 /// \brief Return true if this instruction is a bitcast instruction.
327 bool isBitcast() const {
328 return Flags & (1 << MCID::Bitcast);
331 /// \brief Return true if this is a select instruction.
332 bool isSelect() const {
333 return Flags & (1 << MCID::Select);
336 /// \brief Return true if this instruction cannot be safely
337 /// duplicated. For example, if the instruction has a unique labels attached
338 /// to it, duplicating it would cause multiple definition errors.
339 bool isNotDuplicable() const {
340 return Flags & (1 << MCID::NotDuplicable);
343 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
344 /// which must be filled by the code generator.
345 bool hasDelaySlot() const {
346 return Flags & (1 << MCID::DelaySlot);
349 /// canFoldAsLoad - Return true for instructions that can be folded as
350 /// memory operands in other instructions. The most common use for this
351 /// is instructions that are simple loads from memory that don't modify
352 /// the loaded value in any way, but it can also be used for instructions
353 /// that can be expressed as constant-pool loads, such as V_SETALLONES
354 /// on x86, to allow them to be folded when it is beneficial.
355 /// This should only be set on instructions that return a value in their
356 /// only virtual register definition.
357 bool canFoldAsLoad() const {
358 return Flags & (1 << MCID::FoldableAsLoad);
361 /// \brief Return true if this instruction behaves
362 /// the same way as the generic REG_SEQUENCE instructions.
364 /// dX VMOVDRR rY, rZ
366 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
368 /// Note that for the optimizers to be able to take advantage of
369 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
370 /// override accordingly.
371 bool isRegSequenceLike() const { return Flags & (1 << MCID::RegSequence); }
373 //===--------------------------------------------------------------------===//
374 // Side Effect Analysis
375 //===--------------------------------------------------------------------===//
377 /// \brief Return true if this instruction could possibly read memory.
378 /// Instructions with this flag set are not necessarily simple load
379 /// instructions, they may load a value and modify it, for example.
380 bool mayLoad() const {
381 return Flags & (1 << MCID::MayLoad);
385 /// \brief Return true if this instruction could possibly modify memory.
386 /// Instructions with this flag set are not necessarily simple store
387 /// instructions, they may store a modified value based on their operands, or
388 /// may not actually modify anything, for example.
389 bool mayStore() const {
390 return Flags & (1 << MCID::MayStore);
393 /// hasUnmodeledSideEffects - Return true if this instruction has side
394 /// effects that are not modeled by other flags. This does not return true
395 /// for instructions whose effects are captured by:
397 /// 1. Their operand list and implicit definition/use list. Register use/def
398 /// info is explicit for instructions.
399 /// 2. Memory accesses. Use mayLoad/mayStore.
400 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
402 /// Examples of side effects would be modifying 'invisible' machine state like
403 /// a control register, flushing a cache, modifying a register invisible to
406 bool hasUnmodeledSideEffects() const {
407 return Flags & (1 << MCID::UnmodeledSideEffects);
410 //===--------------------------------------------------------------------===//
411 // Flags that indicate whether an instruction can be modified by a method.
412 //===--------------------------------------------------------------------===//
414 /// isCommutable - Return true if this may be a 2- or 3-address
415 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
416 /// result if Y and Z are exchanged. If this flag is set, then the
417 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
420 /// Note that this flag may be set on instructions that are only commutable
421 /// sometimes. In these cases, the call to commuteInstruction will fail.
422 /// Also note that some instructions require non-trivial modification to
424 bool isCommutable() const {
425 return Flags & (1 << MCID::Commutable);
428 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
429 /// which can be changed into a 3-address instruction if needed. Doing this
430 /// transformation can be profitable in the register allocator, because it
431 /// means that the instruction can use a 2-address form if possible, but
432 /// degrade into a less efficient form if the source and dest register cannot
433 /// be assigned to the same register. For example, this allows the x86
434 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
435 /// is the same speed as the shift but has bigger code size.
437 /// If this returns true, then the target must implement the
438 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
439 /// is allowed to fail if the transformation isn't valid for this specific
440 /// instruction (e.g. shl reg, 4 on x86).
442 bool isConvertibleTo3Addr() const {
443 return Flags & (1 << MCID::ConvertibleTo3Addr);
446 /// usesCustomInsertionHook - Return true if this instruction requires
447 /// custom insertion support when the DAG scheduler is inserting it into a
448 /// machine basic block. If this is true for the instruction, it basically
449 /// means that it is a pseudo instruction used at SelectionDAG time that is
450 /// expanded out into magic code by the target when MachineInstrs are formed.
452 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
453 /// is used to insert this into the MachineBasicBlock.
454 bool usesCustomInsertionHook() const {
455 return Flags & (1 << MCID::UsesCustomInserter);
458 /// hasPostISelHook - Return true if this instruction requires *adjustment*
459 /// after instruction selection by calling a target hook. For example, this
460 /// can be used to fill in ARM 's' optional operand depending on whether
461 /// the conditional flag register is used.
462 bool hasPostISelHook() const {
463 return Flags & (1 << MCID::HasPostISelHook);
466 /// isRematerializable - Returns true if this instruction is a candidate for
467 /// remat. This flag is only used in TargetInstrInfo method
468 /// isTriviallyRematerializable.
470 /// If this flag is set, the isReallyTriviallyReMaterializable()
471 /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
472 /// the instruction is really rematable.
473 bool isRematerializable() const {
474 return Flags & (1 << MCID::Rematerializable);
477 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
478 /// less) than a move instruction. This is useful during certain types of
479 /// optimizations (e.g., remat during two-address conversion or machine licm)
480 /// where we would like to remat or hoist the instruction, but not if it costs
481 /// more than moving the instruction into the appropriate register. Note, we
482 /// are not marking copies from and to the same register class with this flag.
484 /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
485 /// for different subtargets.
486 bool isAsCheapAsAMove() const {
487 return Flags & (1 << MCID::CheapAsAMove);
490 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
491 /// have special register allocation requirements that are not captured by the
492 /// operand register classes. e.g. ARM::STRD's two source registers must be an
493 /// even / odd pair, ARM::STM registers have to be in ascending order.
494 /// Post-register allocation passes should not attempt to change allocations
495 /// for sources of instructions with this flag.
496 bool hasExtraSrcRegAllocReq() const {
497 return Flags & (1 << MCID::ExtraSrcRegAllocReq);
500 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
501 /// have special register allocation requirements that are not captured by the
502 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
503 /// even / odd pair, ARM::LDM registers have to be in ascending order.
504 /// Post-register allocation passes should not attempt to change allocations
505 /// for definitions of instructions with this flag.
506 bool hasExtraDefRegAllocReq() const {
507 return Flags & (1 << MCID::ExtraDefRegAllocReq);
511 /// getImplicitUses - Return a list of registers that are potentially
512 /// read by any instance of this machine instruction. For example, on X86,
513 /// the "adc" instruction adds two register operands and adds the carry bit in
514 /// from the flags register. In this case, the instruction is marked as
515 /// implicitly reading the flags. Likewise, the variable shift instruction on
516 /// X86 is marked as implicitly reading the 'CL' register, which it always
519 /// This method returns null if the instruction has no implicit uses.
520 const uint16_t *getImplicitUses() const {
524 /// \brief Return the number of implicit uses this instruction has.
525 unsigned getNumImplicitUses() const {
526 if (!ImplicitUses) return 0;
528 for (; ImplicitUses[i]; ++i) /*empty*/;
532 /// getImplicitDefs - Return a list of registers that are potentially
533 /// written by any instance of this machine instruction. For example, on X86,
534 /// many instructions implicitly set the flags register. In this case, they
535 /// are marked as setting the FLAGS. Likewise, many instructions always
536 /// deposit their result in a physical register. For example, the X86 divide
537 /// instruction always deposits the quotient and remainder in the EAX/EDX
538 /// registers. For that instruction, this will return a list containing the
539 /// EAX/EDX/EFLAGS registers.
541 /// This method returns null if the instruction has no implicit defs.
542 const uint16_t *getImplicitDefs() const {
546 /// \brief Return the number of implicit defs this instruct has.
547 unsigned getNumImplicitDefs() const {
548 if (!ImplicitDefs) return 0;
550 for (; ImplicitDefs[i]; ++i) /*empty*/;
554 /// \brief Return true if this instruction implicitly
555 /// uses the specified physical register.
556 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
557 if (const uint16_t *ImpUses = ImplicitUses)
558 for (; *ImpUses; ++ImpUses)
559 if (*ImpUses == Reg) return true;
563 /// \brief Return true if this instruction implicitly
564 /// defines the specified physical register.
565 bool hasImplicitDefOfPhysReg(unsigned Reg,
566 const MCRegisterInfo *MRI = nullptr) const {
567 if (const uint16_t *ImpDefs = ImplicitDefs)
568 for (; *ImpDefs; ++ImpDefs)
569 if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
574 /// \brief Return true if this instruction defines the specified physical
575 /// register, either explicitly or implicitly.
576 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
577 const MCRegisterInfo &RI) const {
578 for (int i = 0, e = NumDefs; i != e; ++i)
579 if (MI.getOperand(i).isReg() &&
580 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
582 return hasImplicitDefOfPhysReg(Reg, &RI);
585 /// \brief Return the scheduling class for this instruction. The
586 /// scheduling class is an index into the InstrItineraryData table. This
587 /// returns zero if there is no known scheduling information for the
589 unsigned getSchedClass() const {
593 /// \brief Return the number of bytes in the encoding of this instruction,
594 /// or zero if the encoding size cannot be known from the opcode.
595 unsigned getSize() const {
599 /// \brief Find the index of the first operand in the
600 /// operand list that is used to represent the predicate. It returns -1 if
602 int findFirstPredOperandIdx() const {
603 if (isPredicable()) {
604 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
605 if (OpInfo[i].isPredicate())
612 } // end namespace llvm