1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines all of the ARM-specific intrinsics.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
19 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
20 Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
23 //===----------------------------------------------------------------------===//
24 // Saturating Arithmentic
26 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
27 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
28 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
29 [IntrNoMem, Commutative]>;
30 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
31 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
32 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
33 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
34 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
35 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
38 //===----------------------------------------------------------------------===//
41 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
42 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
43 Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
44 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
45 Intrinsic<[], [llvm_i32_ty], []>;
46 def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
48 def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
52 //===----------------------------------------------------------------------===//
53 // Advanced SIMD (NEON)
55 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
57 // The following classes do not correspond directly to GCC builtins.
58 class Neon_1Arg_Intrinsic
59 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
60 class Neon_1Arg_Narrow_Intrinsic
61 : Intrinsic<[llvm_anyvector_ty],
62 [LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
63 class Neon_2Arg_Intrinsic
64 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
66 class Neon_2Arg_Narrow_Intrinsic
67 : Intrinsic<[llvm_anyvector_ty],
68 [LLVMExtendedElementVectorType<0>,
69 LLVMExtendedElementVectorType<0>],
71 class Neon_2Arg_Long_Intrinsic
72 : Intrinsic<[llvm_anyvector_ty],
73 [LLVMTruncatedElementVectorType<0>,
74 LLVMTruncatedElementVectorType<0>],
76 class Neon_2Arg_Wide_Intrinsic
77 : Intrinsic<[llvm_anyvector_ty],
78 [LLVMMatchType<0>, LLVMTruncatedElementVectorType<0>],
80 class Neon_3Arg_Intrinsic
81 : Intrinsic<[llvm_anyvector_ty],
82 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
84 class Neon_3Arg_Long_Intrinsic
85 : Intrinsic<[llvm_anyvector_ty],
87 LLVMTruncatedElementVectorType<0>,
88 LLVMTruncatedElementVectorType<0>],
90 class Neon_CvtFxToFP_Intrinsic
91 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
92 class Neon_CvtFPToFx_Intrinsic
93 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
95 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
96 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
97 // Overall, the classes range from 2 to 6 v8i8 arguments.
98 class Neon_Tbl2Arg_Intrinsic
99 : Intrinsic<[llvm_v8i8_ty],
100 [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
101 class Neon_Tbl3Arg_Intrinsic
102 : Intrinsic<[llvm_v8i8_ty],
103 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
104 class Neon_Tbl4Arg_Intrinsic
105 : Intrinsic<[llvm_v8i8_ty],
106 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
108 class Neon_Tbl5Arg_Intrinsic
109 : Intrinsic<[llvm_v8i8_ty],
110 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
111 llvm_v8i8_ty], [IntrNoMem]>;
112 class Neon_Tbl6Arg_Intrinsic
113 : Intrinsic<[llvm_v8i8_ty],
114 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
115 llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
120 let Properties = [IntrNoMem, Commutative] in {
123 def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
124 def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
125 def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
126 def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
127 def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
128 def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
129 def int_arm_neon_vaddhn : Neon_2Arg_Narrow_Intrinsic;
130 def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
131 def int_arm_neon_vaddls : Neon_2Arg_Long_Intrinsic;
132 def int_arm_neon_vaddlu : Neon_2Arg_Long_Intrinsic;
133 def int_arm_neon_vaddws : Neon_2Arg_Wide_Intrinsic;
134 def int_arm_neon_vaddwu : Neon_2Arg_Wide_Intrinsic;
137 def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
138 def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
139 def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
140 def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
141 def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
142 def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
143 def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
145 // Vector Multiply and Accumulate/Subtract.
146 def int_arm_neon_vmlals : Neon_3Arg_Long_Intrinsic;
147 def int_arm_neon_vmlalu : Neon_3Arg_Long_Intrinsic;
148 def int_arm_neon_vmlsls : Neon_3Arg_Long_Intrinsic;
149 def int_arm_neon_vmlslu : Neon_3Arg_Long_Intrinsic;
150 def int_arm_neon_vqdmlal : Neon_3Arg_Long_Intrinsic;
151 def int_arm_neon_vqdmlsl : Neon_3Arg_Long_Intrinsic;
154 def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
155 def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
158 def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
159 def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
161 // Vector Reciprocal Step.
162 def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
164 // Vector Reciprocal Square Root Step.
165 def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
169 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
170 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
171 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
172 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
173 def int_arm_neon_vsubhn : Neon_2Arg_Narrow_Intrinsic;
174 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
175 def int_arm_neon_vsubls : Neon_2Arg_Long_Intrinsic;
176 def int_arm_neon_vsublu : Neon_2Arg_Long_Intrinsic;
177 def int_arm_neon_vsubws : Neon_2Arg_Wide_Intrinsic;
178 def int_arm_neon_vsubwu : Neon_2Arg_Wide_Intrinsic;
180 // Vector Absolute Compare.
181 let TargetPrefix = "arm" in {
182 def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
183 [llvm_v2f32_ty, llvm_v2f32_ty],
185 def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
186 [llvm_v4f32_ty, llvm_v4f32_ty],
188 def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
189 [llvm_v2f32_ty, llvm_v2f32_ty],
191 def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
192 [llvm_v4f32_ty, llvm_v4f32_ty],
196 // Vector Absolute Differences.
197 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
198 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
199 def int_arm_neon_vabdls : Neon_2Arg_Long_Intrinsic;
200 def int_arm_neon_vabdlu : Neon_2Arg_Long_Intrinsic;
202 // Vector Absolute Difference and Accumulate.
203 def int_arm_neon_vabas : Neon_3Arg_Intrinsic;
204 def int_arm_neon_vabau : Neon_3Arg_Intrinsic;
205 def int_arm_neon_vabals : Neon_3Arg_Long_Intrinsic;
206 def int_arm_neon_vabalu : Neon_3Arg_Long_Intrinsic;
208 // Vector Pairwise Add.
209 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
211 // Vector Pairwise Add Long.
212 // Note: This is different than the other "long" NEON intrinsics because
213 // the result vector has half as many elements as the source vector.
214 // The source and destination vector types must be specified separately.
215 let TargetPrefix = "arm" in {
216 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
218 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
222 // Vector Pairwise Add and Accumulate Long.
223 // Note: This is similar to vpaddl but the destination vector also appears
224 // as the first argument.
225 let TargetPrefix = "arm" in {
226 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
227 [LLVMMatchType<0>, llvm_anyvector_ty],
229 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
230 [LLVMMatchType<0>, llvm_anyvector_ty],
234 // Vector Pairwise Maximum and Minimum.
235 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
236 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
237 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
238 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
242 // The various saturating and rounding vector shift operations need to be
243 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
244 // operation cannot be safely translated to LLVM's shift operators. VSHL can
245 // be used for both left and right shifts, or even combinations of the two,
246 // depending on the signs of the shift amounts. It also has well-defined
247 // behavior for shift amounts that LLVM leaves undefined. Only basic shifts
248 // by constants can be represented with LLVM's shift operators.
250 // The shift counts for these intrinsics are always vectors, even for constant
251 // shifts, where the constant is replicated. For consistency with VSHL (and
252 // other variable shift instructions), left shifts have positive shift counts
253 // and right shifts have negative shift counts. This convention is also used
254 // for constant right shift intrinsics, and to help preserve sanity, the
255 // intrinsic names use "shift" instead of either "shl" or "shr". Where
256 // applicable, signed and unsigned versions of the intrinsics are
257 // distinguished with "s" and "u" suffixes. A few NEON shift instructions,
258 // such as VQSHLU, take signed operands but produce unsigned results; these
259 // use a "su" suffix.
262 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
263 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
264 def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic;
265 def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic;
266 def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic;
268 // Vector Rounding Shift.
269 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
270 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
271 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
273 // Vector Saturating Shift.
274 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
275 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
276 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
277 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
278 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
279 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
281 // Vector Saturating Rounding Shift.
282 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
283 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
284 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
285 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
286 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
288 // Vector Shift and Insert.
289 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
291 // Vector Absolute Value and Saturating Absolute Value.
292 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
293 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
295 // Vector Saturating Negate.
296 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
298 // Vector Count Leading Sign/Zero Bits.
299 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
300 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
302 // Vector Count One Bits.
303 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
305 // Vector Reciprocal Estimate.
306 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
308 // Vector Reciprocal Square Root Estimate.
309 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
311 // Vector Conversions Between Floating-point and Fixed-point.
312 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
313 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
314 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
315 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
317 // Narrowing and Lengthening Vector Moves.
318 def int_arm_neon_vmovn : Neon_1Arg_Narrow_Intrinsic;
319 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
320 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
321 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
323 // Vector Table Lookup.
324 // The first 1-4 arguments are the table.
325 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
326 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
327 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
328 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
330 // Vector Table Extension.
331 // Some elements of the destination vector may not be updated, so the original
332 // value of that vector is passed as the first argument. The next 1-4
333 // arguments after that are the table.
334 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
335 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
336 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
337 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
339 let TargetPrefix = "arm" in {
341 // De-interleaving vector loads from N-element structures.
342 // Source operands are the address and alignment.
343 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
344 [llvm_ptr_ty, llvm_i32_ty],
346 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
347 [llvm_ptr_ty, llvm_i32_ty],
349 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
351 [llvm_ptr_ty, llvm_i32_ty],
353 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
354 LLVMMatchType<0>, LLVMMatchType<0>],
355 [llvm_ptr_ty, llvm_i32_ty],
358 // Vector load N-element structure to one lane.
359 // Source operands are: the address, the N input vectors (since only one
360 // lane is assigned), the lane number, and the alignment.
361 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
362 [llvm_ptr_ty, LLVMMatchType<0>,
363 LLVMMatchType<0>, llvm_i32_ty,
364 llvm_i32_ty], [IntrReadArgMem]>;
365 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
367 [llvm_ptr_ty, LLVMMatchType<0>,
368 LLVMMatchType<0>, LLVMMatchType<0>,
369 llvm_i32_ty, llvm_i32_ty],
371 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
372 LLVMMatchType<0>, LLVMMatchType<0>],
373 [llvm_ptr_ty, LLVMMatchType<0>,
374 LLVMMatchType<0>, LLVMMatchType<0>,
375 LLVMMatchType<0>, llvm_i32_ty,
376 llvm_i32_ty], [IntrReadArgMem]>;
378 // Interleaving vector stores from N-element structures.
379 // Source operands are: the address, the N vectors, and the alignment.
380 def int_arm_neon_vst1 : Intrinsic<[],
381 [llvm_ptr_ty, llvm_anyvector_ty,
382 llvm_i32_ty], [IntrReadWriteArgMem]>;
383 def int_arm_neon_vst2 : Intrinsic<[],
384 [llvm_ptr_ty, llvm_anyvector_ty,
385 LLVMMatchType<0>, llvm_i32_ty],
386 [IntrReadWriteArgMem]>;
387 def int_arm_neon_vst3 : Intrinsic<[],
388 [llvm_ptr_ty, llvm_anyvector_ty,
389 LLVMMatchType<0>, LLVMMatchType<0>,
390 llvm_i32_ty], [IntrReadWriteArgMem]>;
391 def int_arm_neon_vst4 : Intrinsic<[],
392 [llvm_ptr_ty, llvm_anyvector_ty,
393 LLVMMatchType<0>, LLVMMatchType<0>,
394 LLVMMatchType<0>, llvm_i32_ty],
395 [IntrReadWriteArgMem]>;
397 // Vector store N-element structure from one lane.
398 // Source operands are: the address, the N vectors, the lane number, and
400 def int_arm_neon_vst2lane : Intrinsic<[],
401 [llvm_ptr_ty, llvm_anyvector_ty,
402 LLVMMatchType<0>, llvm_i32_ty,
403 llvm_i32_ty], [IntrReadWriteArgMem]>;
404 def int_arm_neon_vst3lane : Intrinsic<[],
405 [llvm_ptr_ty, llvm_anyvector_ty,
406 LLVMMatchType<0>, LLVMMatchType<0>,
407 llvm_i32_ty, llvm_i32_ty],
408 [IntrReadWriteArgMem]>;
409 def int_arm_neon_vst4lane : Intrinsic<[],
410 [llvm_ptr_ty, llvm_anyvector_ty,
411 LLVMMatchType<0>, LLVMMatchType<0>,
412 LLVMMatchType<0>, llvm_i32_ty,
413 llvm_i32_ty], [IntrReadWriteArgMem]>;