include/llvm/IR/IntrinsicsARM.td

   1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines all of the ARM-specific intrinsics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14
  15 //===----------------------------------------------------------------------===//
  16 // TLS
  17
  18 let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
  19
  20 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
  21             Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
  22
  23 // A space-consuming intrinsic primarily for testing ARMConstantIslands. The
  24 // first argument is the number of bytes this "instruction" takes up, the second
  25 // and return value are essentially chains, used to force ordering during ISel.
  26 def int_arm_space : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
  27
  28 //===----------------------------------------------------------------------===//
  29 // Saturating Arithmetic
  30
  31 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
  32     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
  33     [IntrNoMem, Commutative]>;
  34 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
  35     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  36 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
  37     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  38 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
  39     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  40
  41 //===----------------------------------------------------------------------===//
  42 // Load, Store and Clear exclusive
  43
  44 def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
  45 def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
  46
  47 def int_arm_ldaex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
  48 def int_arm_stlex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
  49
  50 def int_arm_clrex : Intrinsic<[]>;
  51
  52 def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
  53     llvm_ptr_ty]>;
  54 def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
  55
  56 def int_arm_stlexd : Intrinsic<[llvm_i32_ty],
  57                                [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty]>;
  58 def int_arm_ldaexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
  59
  60 //===----------------------------------------------------------------------===//
  61 // Data barrier instructions
  62 def int_arm_dmb : GCCBuiltin<"__builtin_arm_dmb">, MSBuiltin<"__dmb">,
  63                   Intrinsic<[], [llvm_i32_ty]>;
  64 def int_arm_dsb : GCCBuiltin<"__builtin_arm_dsb">, MSBuiltin<"__dsb">,
  65                   Intrinsic<[], [llvm_i32_ty]>;
  66 def int_arm_isb : GCCBuiltin<"__builtin_arm_isb">, MSBuiltin<"__isb">,
  67                   Intrinsic<[], [llvm_i32_ty]>;
  68
  69 //===----------------------------------------------------------------------===//
  70 // VFP
  71
  72 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
  73                        Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
  74 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
  75                        Intrinsic<[], [llvm_i32_ty], []>;
  76 def int_arm_vcvtr     : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  77                                   [IntrNoMem]>;
  78 def int_arm_vcvtru    : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  79                                   [IntrNoMem]>;
  80
  81 //===----------------------------------------------------------------------===//
  82 // Coprocessor
  83
  84 // Move to coprocessor
  85 def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
  86                   MSBuiltin<"_MoveToCoprocessor">,
  87    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  88                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  89 def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
  90                    MSBuiltin<"_MoveToCoprocessor2">,
  91    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  92                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  93
  94 // Move from coprocessor
  95 def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
  96                   MSBuiltin<"_MoveFromCoprocessor">,
  97    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  98                              llvm_i32_ty, llvm_i32_ty], []>;
  99 def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
 100                    MSBuiltin<"_MoveFromCoprocessor2">,
 101    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 102                              llvm_i32_ty, llvm_i32_ty], []>;
 103
 104 // Coprocessor data processing
 105 def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
 106    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 107                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
 108 def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
 109    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 110                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
 111
 112 // Move from two registers to coprocessor
 113 def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
 114    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 115                   llvm_i32_ty, llvm_i32_ty], []>;
 116 def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
 117    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 118                   llvm_i32_ty, llvm_i32_ty], []>;
 119
 120 //===----------------------------------------------------------------------===//
 121 // CRC32
 122
 123 def int_arm_crc32b  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 124     [IntrNoMem]>;
 125 def int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 126     [IntrNoMem]>;
 127 def int_arm_crc32h  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 128     [IntrNoMem]>;
 129 def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 130     [IntrNoMem]>;
 131 def int_arm_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 132     [IntrNoMem]>;
 133 def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 134     [IntrNoMem]>;
 135
 136 //===----------------------------------------------------------------------===//
 137 // HINT
 138
 139 def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
 140 def int_arm_dbg : Intrinsic<[], [llvm_i32_ty]>;
 141
 142 //===----------------------------------------------------------------------===//
 143 // RBIT
 144
 145 def int_arm_rbit : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
 146
 147 //===----------------------------------------------------------------------===//
 148 // UND (reserved undefined sequence)
 149
 150 def int_arm_undefined : Intrinsic<[], [llvm_i32_ty]>;
 151
 152 //===----------------------------------------------------------------------===//
 153 // Advanced SIMD (NEON)
 154
 155 // The following classes do not correspond directly to GCC builtins.
 156 class Neon_1Arg_Intrinsic
 157   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
 158 class Neon_1Arg_Narrow_Intrinsic
 159   : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
 160 class Neon_2Arg_Intrinsic
 161   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
 162               [IntrNoMem]>;
 163 class Neon_2Arg_Narrow_Intrinsic
 164   : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>, LLVMExtendedType<0>],
 165               [IntrNoMem]>;
 166 class Neon_2Arg_Long_Intrinsic
 167   : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
 168               [IntrNoMem]>;
 169 class Neon_3Arg_Intrinsic
 170   : Intrinsic<[llvm_anyvector_ty],
 171               [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 172               [IntrNoMem]>;
 173 class Neon_3Arg_Long_Intrinsic
 174   : Intrinsic<[llvm_anyvector_ty],
 175               [LLVMMatchType<0>, LLVMTruncatedType<0>, LLVMTruncatedType<0>],
 176               [IntrNoMem]>;
 177 class Neon_CvtFxToFP_Intrinsic
 178   : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
 179 class Neon_CvtFPToFx_Intrinsic
 180   : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
 181 class Neon_CvtFPtoInt_1Arg_Intrinsic
 182   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
 183
 184 class Neon_Compare_Intrinsic
 185   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
 186               [IntrNoMem]>;
 187
 188 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
 189 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
 190 // Overall, the classes range from 2 to 6 v8i8 arguments.
 191 class Neon_Tbl2Arg_Intrinsic
 192   : Intrinsic<[llvm_v8i8_ty],
 193               [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 194 class Neon_Tbl3Arg_Intrinsic
 195   : Intrinsic<[llvm_v8i8_ty],
 196               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 197 class Neon_Tbl4Arg_Intrinsic
 198   : Intrinsic<[llvm_v8i8_ty],
 199               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
 200               [IntrNoMem]>;
 201 class Neon_Tbl5Arg_Intrinsic
 202   : Intrinsic<[llvm_v8i8_ty],
 203               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 204                llvm_v8i8_ty], [IntrNoMem]>;
 205 class Neon_Tbl6Arg_Intrinsic
 206   : Intrinsic<[llvm_v8i8_ty],
 207               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 208                llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 209
 210 // Arithmetic ops
 211
 212 let Properties = [IntrNoMem, Commutative] in {
 213
 214   // Vector Add.
 215   def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
 216   def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
 217   def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
 218   def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
 219   def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
 220   def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
 221   def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
 222
 223   // Vector Multiply.
 224   def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
 225   def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
 226   def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
 227   def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
 228   def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
 229   def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
 230   def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
 231
 232   // Vector Maximum.
 233   def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
 234   def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
 235   def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
 236
 237   // Vector Minimum.
 238   def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
 239   def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
 240   def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
 241
 242   // Vector Reciprocal Step.
 243   def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
 244
 245   // Vector Reciprocal Square Root Step.
 246   def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
 247 }
 248
 249 // Vector Subtract.
 250 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
 251 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
 252 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
 253 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
 254 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
 255
 256 // Vector Absolute Compare.
 257 def int_arm_neon_vacge : Neon_Compare_Intrinsic;
 258 def int_arm_neon_vacgt : Neon_Compare_Intrinsic;
 259
 260 // Vector Absolute Differences.
 261 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
 262 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
 263
 264 // Vector Pairwise Add.
 265 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
 266
 267 // Vector Pairwise Add Long.
 268 // Note: This is different than the other "long" NEON intrinsics because
 269 // the result vector has half as many elements as the source vector.
 270 // The source and destination vector types must be specified separately.
 271 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 272                                      [IntrNoMem]>;
 273 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 274                                      [IntrNoMem]>;
 275
 276 // Vector Pairwise Add and Accumulate Long.
 277 // Note: This is similar to vpaddl but the destination vector also appears
 278 // as the first argument.
 279 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
 280                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 281                                      [IntrNoMem]>;
 282 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
 283                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 284                                      [IntrNoMem]>;
 285
 286 // Vector Pairwise Maximum and Minimum.
 287 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
 288 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
 289 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
 290 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
 291
 292 // Vector Shifts:
 293 //
 294 // The various saturating and rounding vector shift operations need to be
 295 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
 296 // operation cannot be safely translated to LLVM's shift operators.  VSHL can
 297 // be used for both left and right shifts, or even combinations of the two,
 298 // depending on the signs of the shift amounts.  It also has well-defined
 299 // behavior for shift amounts that LLVM leaves undefined.  Only basic shifts
 300 // by constants can be represented with LLVM's shift operators.
 301 //
 302 // The shift counts for these intrinsics are always vectors, even for constant
 303 // shifts, where the constant is replicated.  For consistency with VSHL (and
 304 // other variable shift instructions), left shifts have positive shift counts
 305 // and right shifts have negative shift counts.  This convention is also used
 306 // for constant right shift intrinsics, and to help preserve sanity, the
 307 // intrinsic names use "shift" instead of either "shl" or "shr".  Where
 308 // applicable, signed and unsigned versions of the intrinsics are
 309 // distinguished with "s" and "u" suffixes.  A few NEON shift instructions,
 310 // such as VQSHLU, take signed operands but produce unsigned results; these
 311 // use a "su" suffix.
 312
 313 // Vector Shift.
 314 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
 315 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
 316
 317 // Vector Rounding Shift.
 318 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
 319 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
 320 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
 321
 322 // Vector Saturating Shift.
 323 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
 324 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
 325 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
 326 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
 327 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
 328 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 329
 330 // Vector Saturating Rounding Shift.
 331 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
 332 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
 333 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
 334 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
 335 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 336
 337 // Vector Shift and Insert.
 338 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
 339
 340 // Vector Absolute Value and Saturating Absolute Value.
 341 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
 342 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
 343
 344 // Vector Saturating Negate.
 345 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
 346
 347 // Vector Count Leading Sign/Zero Bits.
 348 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
 349
 350 // Vector Reciprocal Estimate.
 351 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
 352
 353 // Vector Reciprocal Square Root Estimate.
 354 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
 355
 356 // Vector Conversions Between Floating-point and Integer
 357 def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
 358 def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
 359 def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 360 def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
 361 def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 362 def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
 363 def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 364 def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
 365
 366 // Vector Conversions Between Floating-point and Fixed-point.
 367 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
 368 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
 369 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
 370 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
 371
 372 // Vector Conversions Between Half-Precision and Single-Precision.
 373 def int_arm_neon_vcvtfp2hf
 374     : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 375 def int_arm_neon_vcvthf2fp
 376     : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
 377
 378 // Narrowing Saturating Vector Moves.
 379 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
 380 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
 381 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
 382
 383 // Vector Table Lookup.
 384 // The first 1-4 arguments are the table.
 385 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
 386 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
 387 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
 388 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
 389
 390 // Vector Table Extension.
 391 // Some elements of the destination vector may not be updated, so the original
 392 // value of that vector is passed as the first argument.  The next 1-4
 393 // arguments after that are the table.
 394 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
 395 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
 396 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
 397 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
 398
 399 // Vector Rounding
 400 def int_arm_neon_vrintn : Neon_1Arg_Intrinsic;
 401 def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
 402 def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
 403 def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
 404 def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
 405 def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
 406
 407 // De-interleaving vector loads from N-element structures.
 408 // Source operands are the address and alignment.
 409 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
 410                                   [llvm_ptr_ty, llvm_i32_ty],
 411                                   [IntrReadArgMem]>;
 412 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 413                                   [llvm_ptr_ty, llvm_i32_ty],
 414                                   [IntrReadArgMem]>;
 415 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 416                                    LLVMMatchType<0>],
 417                                   [llvm_ptr_ty, llvm_i32_ty],
 418                                   [IntrReadArgMem]>;
 419 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 420                                    LLVMMatchType<0>, LLVMMatchType<0>],
 421                                   [llvm_ptr_ty, llvm_i32_ty],
 422                                   [IntrReadArgMem]>;
 423
 424 // Vector load N-element structure to one lane.
 425 // Source operands are: the address, the N input vectors (since only one
 426 // lane is assigned), the lane number, and the alignment.
 427 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 428                                       [llvm_ptr_ty, LLVMMatchType<0>,
 429                                        LLVMMatchType<0>, llvm_i32_ty,
 430                                        llvm_i32_ty], [IntrReadArgMem]>;
 431 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 432                                        LLVMMatchType<0>],
 433                                       [llvm_ptr_ty, LLVMMatchType<0>,
 434                                        LLVMMatchType<0>, LLVMMatchType<0>,
 435                                        llvm_i32_ty, llvm_i32_ty],
 436                                       [IntrReadArgMem]>;
 437 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 438                                        LLVMMatchType<0>, LLVMMatchType<0>],
 439                                       [llvm_ptr_ty, LLVMMatchType<0>,
 440                                        LLVMMatchType<0>, LLVMMatchType<0>,
 441                                        LLVMMatchType<0>, llvm_i32_ty,
 442                                        llvm_i32_ty], [IntrReadArgMem]>;
 443
 444 // Interleaving vector stores from N-element structures.
 445 // Source operands are: the address, the N vectors, and the alignment.
 446 def int_arm_neon_vst1 : Intrinsic<[],
 447                                   [llvm_ptr_ty, llvm_anyvector_ty,
 448                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
 449 def int_arm_neon_vst2 : Intrinsic<[],
 450                                   [llvm_ptr_ty, llvm_anyvector_ty,
 451                                    LLVMMatchType<0>, llvm_i32_ty],
 452                                   [IntrReadWriteArgMem]>;
 453 def int_arm_neon_vst3 : Intrinsic<[],
 454                                   [llvm_ptr_ty, llvm_anyvector_ty,
 455                                    LLVMMatchType<0>, LLVMMatchType<0>,
 456                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
 457 def int_arm_neon_vst4 : Intrinsic<[],
 458                                   [llvm_ptr_ty, llvm_anyvector_ty,
 459                                    LLVMMatchType<0>, LLVMMatchType<0>,
 460                                    LLVMMatchType<0>, llvm_i32_ty],
 461                                   [IntrReadWriteArgMem]>;
 462
 463 // Vector store N-element structure from one lane.
 464 // Source operands are: the address, the N vectors, the lane number, and
 465 // the alignment.
 466 def int_arm_neon_vst2lane : Intrinsic<[],
 467                                       [llvm_ptr_ty, llvm_anyvector_ty,
 468                                        LLVMMatchType<0>, llvm_i32_ty,
 469                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
 470 def int_arm_neon_vst3lane : Intrinsic<[],
 471                                       [llvm_ptr_ty, llvm_anyvector_ty,
 472                                        LLVMMatchType<0>, LLVMMatchType<0>,
 473                                        llvm_i32_ty, llvm_i32_ty],
 474                                       [IntrReadWriteArgMem]>;
 475 def int_arm_neon_vst4lane : Intrinsic<[],
 476                                       [llvm_ptr_ty, llvm_anyvector_ty,
 477                                        LLVMMatchType<0>, LLVMMatchType<0>,
 478                                        LLVMMatchType<0>, llvm_i32_ty,
 479                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
 480
 481 // Vector bitwise select.
 482 def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
 483                         [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 484                         [IntrNoMem]>;
 485
 486
 487 // Crypto instructions
 488 class AES_1Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
 489                                      [llvm_v16i8_ty], [IntrNoMem]>;
 490 class AES_2Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
 491                                      [llvm_v16i8_ty, llvm_v16i8_ty],
 492                                      [IntrNoMem]>;
 493
 494 class SHA_1Arg_Intrinsic : Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
 495                                      [IntrNoMem]>;
 496 class SHA_2Arg_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 497                                      [llvm_v4i32_ty, llvm_v4i32_ty],
 498                                      [IntrNoMem]>;
 499 class SHA_3Arg_i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 500                                    [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
 501                                    [IntrNoMem]>;
 502 class SHA_3Arg_v4i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 503                                    [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v4i32_ty],
 504                                    [IntrNoMem]>;
 505
 506 def int_arm_neon_aesd : AES_2Arg_Intrinsic;
 507 def int_arm_neon_aese : AES_2Arg_Intrinsic;
 508 def int_arm_neon_aesimc : AES_1Arg_Intrinsic;
 509 def int_arm_neon_aesmc : AES_1Arg_Intrinsic;
 510 def int_arm_neon_sha1h : SHA_1Arg_Intrinsic;
 511 def int_arm_neon_sha1su1 : SHA_2Arg_Intrinsic;
 512 def int_arm_neon_sha256su0 : SHA_2Arg_Intrinsic;
 513 def int_arm_neon_sha1c : SHA_3Arg_i32_Intrinsic;
 514 def int_arm_neon_sha1m : SHA_3Arg_i32_Intrinsic;
 515 def int_arm_neon_sha1p : SHA_3Arg_i32_Intrinsic;
 516 def int_arm_neon_sha1su0: SHA_3Arg_v4i32_Intrinsic;
 517 def int_arm_neon_sha256h: SHA_3Arg_v4i32_Intrinsic;
 518 def int_arm_neon_sha256h2: SHA_3Arg_v4i32_Intrinsic;
 519 def int_arm_neon_sha256su1: SHA_3Arg_v4i32_Intrinsic;
 520
 521 } // end TargetPrefix