1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/BasicBlock.h"
19 #include "llvm/Pass.h"
20 #include "llvm/Constant.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
26 class SelectionDAGBuilder;
28 class MachineRegisterInfo;
29 class MachineBasicBlock;
30 class MachineFunction;
32 class MachineModuleInfo;
35 class TargetInstrInfo;
36 class FunctionLoweringInfo;
37 class ScheduleHazardRecognizer;
39 class ScheduleDAGSDNodes;
41 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
42 /// pattern-matching instruction selectors.
43 class SelectionDAGISel : public MachineFunctionPass {
45 const TargetMachine &TM;
47 FunctionLoweringInfo *FuncInfo;
49 MachineRegisterInfo *RegInfo;
51 SelectionDAGBuilder *SDB;
52 MachineBasicBlock *BB;
55 CodeGenOpt::Level OptLevel;
58 explicit SelectionDAGISel(TargetMachine &tm,
59 CodeGenOpt::Level OL = CodeGenOpt::Default);
60 virtual ~SelectionDAGISel();
62 TargetLowering &getTargetLowering() { return TLI; }
64 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
66 virtual bool runOnMachineFunction(MachineFunction &MF);
68 unsigned MakeReg(EVT VT);
70 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
71 virtual void InstructionSelect() = 0;
73 void SelectRootInit() {
74 DAGSize = CurDAG->AssignTopologicalOrder();
77 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
78 /// addressing mode, according to the specified constraint code. If this does
79 /// not match or is not implemented, return true. The resultant operands
80 /// (which will appear in the machine instruction) should be added to the
82 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
84 std::vector<SDValue> &OutOps) {
88 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
89 /// operand node N of U during instruction selection that starts at Root.
90 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
92 /// IsLegalToFold - Returns true if the specific operand node N of
93 /// U can be folded during instruction selection that starts at Root.
94 virtual bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root) const;
96 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
97 /// to use for this target when scheduling the DAG.
98 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
101 /// DAGSize - Size of DAG being instruction selected.
105 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
106 /// by tblgen. Others should not call it.
107 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
109 // Calls to these predicates are generated by tblgen.
110 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
111 int64_t DesiredMaskS) const;
112 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
113 int64_t DesiredMaskS) const;
116 /// CheckPatternPredicate - This function is generated by tblgen in the
117 /// target. It runs the specified pattern predicate and returns true if it
118 /// succeeds or false if it fails. The number is a private implementation
119 /// detail to the code tblgen produces.
120 virtual bool CheckPatternPredicate(unsigned PredNo) const {
121 assert(0 && "Tblgen should generate the implementation of this!");
125 /// CheckNodePredicate - This function is generated by tblgen in the
126 /// target. It runs node predicate #PredNo and returns true if it succeeds or
127 /// false if it fails. The number is a private implementation
128 /// detail to the code tblgen produces.
129 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
130 assert(0 && "Tblgen should generate the implementation of this!");
134 virtual bool CheckComplexPattern(SDNode *Root, SDValue N, unsigned PatternNo,
135 SmallVectorImpl<SDValue> &Result) {
136 assert(0 && "Tblgen should generate the implementation of this!");
140 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
141 assert(0 && "Tblgen shoudl generate this!");
146 // Calls to these functions are generated by tblgen.
147 SDNode *Select_INLINEASM(SDNode *N);
148 SDNode *Select_UNDEF(SDNode *N);
149 SDNode *Select_EH_LABEL(SDNode *N);
150 void CannotYetSelect(SDNode *N);
151 void CannotYetSelectIntrinsic(SDNode *N);
154 void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
155 MachineModuleInfo *MMI,
157 const TargetInstrInfo &TII);
158 void FinishBasicBlock();
160 void SelectBasicBlock(BasicBlock *LLVMBB,
161 BasicBlock::iterator Begin,
162 BasicBlock::iterator End,
164 void CodeGenAndEmitDAG();
165 void LowerArguments(BasicBlock *BB);
167 void ShrinkDemandedOps();
168 void ComputeLiveOutVRegInfo();
170 void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
172 bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
174 /// Create the scheduler. If a specific scheduler was specified
175 /// via the SchedulerRegistry, use it, otherwise select the
176 /// one preferred by the target.
178 ScheduleDAGSDNodes *CreateScheduler();
183 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */