1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/Pass.h"
19 #include "llvm/Constant.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
23 class SelectionDAGLowering;
25 class MachineRegisterInfo;
26 class MachineBasicBlock;
27 class MachineFunction;
30 class FunctionLoweringInfo;
31 class HazardRecognizer;
32 class CollectorMetadata;
34 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
35 /// pattern-matching instruction selectors.
36 class SelectionDAGISel : public FunctionPass {
39 MachineRegisterInfo *RegInfo;
41 MachineBasicBlock *BB;
43 CollectorMetadata *GCI;
45 std::vector<SDNode*> TopOrder;
48 explicit SelectionDAGISel(TargetLowering &tli, bool fast = false) :
49 FunctionPass((intptr_t)&ID), TLI(tli), GCI(0), FastISel(fast), DAGSize(0) {}
51 TargetLowering &getTargetLowering() { return TLI; }
53 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
55 virtual bool runOnFunction(Function &Fn);
57 unsigned MakeReg(MVT VT);
59 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
60 virtual void InstructionSelect(SelectionDAG &SD) = 0;
61 virtual void InstructionSelectPostProcessing(SelectionDAG &DAG) {}
63 virtual void SelectRootInit() {
64 DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);
67 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
68 /// addressing mode, according to the specified constraint code. If this does
69 /// not match or is not implemented, return true. The resultant operands
70 /// (which will appear in the machine instruction) should be added to the
72 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
74 std::vector<SDOperand> &OutOps,
79 /// CanBeFoldedBy - Returns true if the specific operand node N of U can be
80 /// folded during instruction selection that starts at Root?
81 virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const {
85 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
86 /// to use for this target when scheduling the DAG.
87 virtual HazardRecognizer *CreateTargetHazardRecognizer();
89 /// CaseBlock - This structure is used to communicate between SDLowering and
90 /// SDISel for the code generation of additional basic blocks needed by multi-
91 /// case switch statements.
93 CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
94 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
95 MachineBasicBlock *me)
96 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
97 TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
98 // CC - the condition code to use for the case block's setcc node
100 // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
101 // Emit by default LHS op RHS. MHS is used for range comparisons:
102 // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
103 Value *CmpLHS, *CmpMHS, *CmpRHS;
104 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
105 MachineBasicBlock *TrueBB, *FalseBB;
106 // ThisBB - the block into which to emit the code for the setcc and branches
107 MachineBasicBlock *ThisBB;
110 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
111 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
113 /// Reg - the virtual register containing the index of the jump table entry
116 /// JTI - the JumpTableIndex for this jump table in the function.
118 /// MBB - the MBB into which to emit the code for the indirect jump.
119 MachineBasicBlock *MBB;
120 /// Default - the MBB of the default bb, which is a successor of the range
121 /// check MBB. This is when updating PHI nodes in successors.
122 MachineBasicBlock *Default;
124 struct JumpTableHeader {
125 JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
127 First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
131 MachineBasicBlock *HeaderBB;
134 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
137 BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
138 Mask(M), ThisBB(T), TargetBB(Tr) { }
140 MachineBasicBlock* ThisBB;
141 MachineBasicBlock* TargetBB;
144 typedef SmallVector<BitTestCase, 3> BitTestInfo;
146 struct BitTestBlock {
147 BitTestBlock(uint64_t F, uint64_t R, Value* SV,
149 MachineBasicBlock* P, MachineBasicBlock* D,
150 const BitTestInfo& C):
151 First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
152 Parent(P), Default(D), Cases(C) { }
158 MachineBasicBlock *Parent;
159 MachineBasicBlock *Default;
164 /// DAGSize - Size of DAG being instruction selected.
168 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
169 /// by tblgen. Others should not call it.
170 void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
173 // Calls to these predicates are generated by tblgen.
174 bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
175 int64_t DesiredMaskS) const;
176 bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
177 int64_t DesiredMaskS) const;
180 void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
181 FunctionLoweringInfo &FuncInfo);
182 void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
183 FunctionLoweringInfo &FuncInfo,
184 alist<SDNode, LargestSDNode> &AllNodes);
186 void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
187 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
188 FunctionLoweringInfo &FuncInfo);
189 void CodeGenAndEmitDAG(SelectionDAG &DAG);
190 void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL);
192 void ComputeLiveOutVRegInfo(SelectionDAG &DAG);
194 /// Pick a safe ordering and emit instructions for each target node in the
196 void ScheduleAndEmitDAG(SelectionDAG &DAG);
198 /// SwitchCases - Vector of CaseBlock structures used to communicate
199 /// SwitchInst code generation information.
200 std::vector<CaseBlock> SwitchCases;
202 /// JTCases - Vector of JumpTable structures which holds necessary information
203 /// for emitting a jump tables during SwitchInst code generation.
204 std::vector<JumpTableBlock> JTCases;
206 std::vector<BitTestBlock> BitTestCases;
211 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */