1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/BasicBlock.h"
19 #include "llvm/Pass.h"
20 #include "llvm/Constant.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
26 class SelectionDAGBuilder;
28 class MachineRegisterInfo;
29 class MachineBasicBlock;
30 class MachineFunction;
32 class MachineModuleInfo;
34 class TargetInstrInfo;
35 class FunctionLoweringInfo;
36 class ScheduleHazardRecognizer;
38 class ScheduleDAGSDNodes;
40 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
41 /// pattern-matching instruction selectors.
42 class SelectionDAGISel : public MachineFunctionPass {
44 const TargetMachine &TM;
46 FunctionLoweringInfo *FuncInfo;
48 MachineRegisterInfo *RegInfo;
50 SelectionDAGBuilder *SDB;
51 MachineBasicBlock *BB;
54 CodeGenOpt::Level OptLevel;
57 explicit SelectionDAGISel(TargetMachine &tm,
58 CodeGenOpt::Level OL = CodeGenOpt::Default);
59 virtual ~SelectionDAGISel();
61 TargetLowering &getTargetLowering() { return TLI; }
63 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
65 virtual bool runOnMachineFunction(MachineFunction &MF);
67 unsigned MakeReg(EVT VT);
69 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
71 /// PreprocessISelDAG - This hook allows targets to hack on the graph before
72 /// instruction selection starts.
73 virtual void PreprocessISelDAG() {}
75 /// PostprocessISelDAG() - This hook allows the target to hack on the graph
76 /// right after selection.
77 virtual void PostprocessISelDAG() {}
79 /// Select - Main hook targets implement to select a node.
80 virtual SDNode *Select(SDNode *N) = 0;
82 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
83 /// addressing mode, according to the specified constraint code. If this does
84 /// not match or is not implemented, return true. The resultant operands
85 /// (which will appear in the machine instruction) should be added to the
87 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
89 std::vector<SDValue> &OutOps) {
93 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
94 /// operand node N of U during instruction selection that starts at Root.
95 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
97 /// IsLegalToFold - Returns true if the specific operand node N of
98 /// U can be folded during instruction selection that starts at Root.
99 bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
100 bool IgnoreChains = false) const;
102 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
103 /// to use for this target when scheduling the DAG.
104 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
107 // Opcodes used by the DAG state machine:
108 enum BuiltinOpcodes {
111 OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
112 OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
114 OPC_CaptureFlagInput,
118 OPC_CheckPatternPredicate,
124 OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
125 OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
126 OPC_CheckChild6Type, OPC_CheckChild7Type,
131 OPC_CheckAndImm, OPC_CheckOrImm,
132 OPC_CheckFoldableChainNode,
136 OPC_EmitConvertToTarget,
137 OPC_EmitMergeInputChains,
138 OPC_EmitMergeInputChains1_0,
139 OPC_EmitMergeInputChains1_1,
149 OPFL_None = 0, // Node has no chain or flag input and isn't variadic.
150 OPFL_Chain = 1, // Node has a chain input.
151 OPFL_FlagInput = 2, // Node has a flag input.
152 OPFL_FlagOutput = 4, // Node has a flag output.
153 OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
154 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs.
155 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs.
156 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs.
157 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs.
158 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs.
159 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs.
160 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs.
162 OPFL_VariadicInfo = OPFL_Variadic6
165 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
166 /// number of fixed arity values that should be skipped when copying from the
168 static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
169 return ((Flags&OPFL_VariadicInfo) >> 4)-1;
174 /// DAGSize - Size of DAG being instruction selected.
178 /// ISelPosition - Node iterator marking the current position of
179 /// instruction selection as it procedes through the topologically-sorted
181 SelectionDAG::allnodes_iterator ISelPosition;
184 /// ISelUpdater - helper class to handle updates of the
185 /// instruction selection graph.
186 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
187 SelectionDAG::allnodes_iterator &ISelPosition;
189 explicit ISelUpdater(SelectionDAG::allnodes_iterator &isp)
190 : ISelPosition(isp) {}
192 /// NodeDeleted - Handle nodes deleted from the graph. If the
193 /// node being deleted is the current ISelPosition node, update
196 virtual void NodeDeleted(SDNode *N, SDNode *E) {
197 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
201 /// NodeUpdated - Ignore updates for now.
202 virtual void NodeUpdated(SDNode *N) {}
205 /// ReplaceUses - replace all uses of the old node F with the use
206 /// of the new node T.
207 void ReplaceUses(SDValue F, SDValue T) {
208 ISelUpdater ISU(ISelPosition);
209 CurDAG->ReplaceAllUsesOfValueWith(F, T, &ISU);
212 /// ReplaceUses - replace all uses of the old nodes F with the use
213 /// of the new nodes T.
214 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
215 ISelUpdater ISU(ISelPosition);
216 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num, &ISU);
219 /// ReplaceUses - replace all uses of the old node F with the use
220 /// of the new node T.
221 void ReplaceUses(SDNode *F, SDNode *T) {
222 ISelUpdater ISU(ISelPosition);
223 CurDAG->ReplaceAllUsesWith(F, T, &ISU);
227 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
228 /// by tblgen. Others should not call it.
229 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
233 // Calls to these predicates are generated by tblgen.
234 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
235 int64_t DesiredMaskS) const;
236 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
237 int64_t DesiredMaskS) const;
240 /// CheckPatternPredicate - This function is generated by tblgen in the
241 /// target. It runs the specified pattern predicate and returns true if it
242 /// succeeds or false if it fails. The number is a private implementation
243 /// detail to the code tblgen produces.
244 virtual bool CheckPatternPredicate(unsigned PredNo) const {
245 assert(0 && "Tblgen should generate the implementation of this!");
249 /// CheckNodePredicate - This function is generated by tblgen in the target.
250 /// It runs node predicate number PredNo and returns true if it succeeds or
251 /// false if it fails. The number is a private implementation
252 /// detail to the code tblgen produces.
253 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
254 assert(0 && "Tblgen should generate the implementation of this!");
258 virtual bool CheckComplexPattern(SDNode *Root, SDValue N, unsigned PatternNo,
259 SmallVectorImpl<SDValue> &Result) {
260 assert(0 && "Tblgen should generate the implementation of this!");
264 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
265 assert(0 && "Tblgen shoudl generate this!");
269 SDNode *SelectCodeCommon(SDNode *NodeToMatch,
270 const unsigned char *MatcherTable,
275 // Calls to these functions are generated by tblgen.
276 SDNode *Select_INLINEASM(SDNode *N);
277 SDNode *Select_UNDEF(SDNode *N);
278 void CannotYetSelect(SDNode *N);
281 void DoInstructionSelection();
282 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs,
283 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo);
285 void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
286 MachineModuleInfo *MMI,
287 const TargetInstrInfo &TII);
288 void FinishBasicBlock();
290 void SelectBasicBlock(BasicBlock *LLVMBB,
291 BasicBlock::iterator Begin,
292 BasicBlock::iterator End,
294 void CodeGenAndEmitDAG();
295 void LowerArguments(BasicBlock *BB);
297 void ShrinkDemandedOps();
298 void ComputeLiveOutVRegInfo();
300 void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
302 bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
304 /// Create the scheduler. If a specific scheduler was specified
305 /// via the SchedulerRegistry, use it, otherwise select the
306 /// one preferred by the target.
308 ScheduleDAGSDNodes *CreateScheduler();
310 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
311 /// state machines that start with a OPC_SwitchOpcode node.
312 std::vector<unsigned> OpcodeOffset;
314 void UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
315 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
316 SDValue InputFlag,const SmallVectorImpl<SDNode*> &F,
323 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */