1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/Pass.h"
19 #include "llvm/CodeGen/ValueTypes.h"
23 class SelectionDAGLowering;
26 class MachineBasicBlock;
27 class MachineFunction;
30 class FunctionLoweringInfo;
32 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
33 /// pattern-matching instruction selectors.
34 class SelectionDAGISel : public FunctionPass {
39 MachineBasicBlock *BB;
41 SelectionDAGISel(TargetLowering &tli) : TLI(tli) {}
43 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
45 virtual bool runOnFunction(Function &Fn);
47 unsigned MakeReg(MVT::ValueType VT);
49 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
50 virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
52 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
53 /// addressing mode, according to the specified constraint code. If this does
54 /// not match or is not implemented, return true. The resultant operands
55 /// (which will appear in the machine instruction) should be added to the
57 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
59 std::vector<SDOperand> &OutOps,
65 /// Pick a safe ordering and emit instructions for each target node in the
67 void ScheduleAndEmitDAG(SelectionDAG &DAG);
69 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
70 /// by tblgen. Others should not call it.
71 void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
75 SDOperand CopyValueToVirtualRegister(SelectionDAGLowering &SDL,
76 Value *V, unsigned Reg);
77 void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
78 FunctionLoweringInfo &FuncInfo);
80 void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
81 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
82 FunctionLoweringInfo &FuncInfo);
83 void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
84 std::vector<SDOperand> &UnorderedChains);
89 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */