1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAGISEL_H
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/IR/BasicBlock.h"
21 #include "llvm/Target/TargetSubtargetInfo.h"
22 #include "llvm/Pass.h"
26 class SelectionDAGBuilder;
28 class MachineRegisterInfo;
29 class MachineBasicBlock;
30 class MachineFunction;
33 class TargetLibraryInfo;
34 class FunctionLoweringInfo;
35 class ScheduleHazardRecognizer;
37 class ScheduleDAGSDNodes;
40 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
41 /// pattern-matching instruction selectors.
42 class SelectionDAGISel : public MachineFunctionPass {
45 const TargetLibraryInfo *LibInfo;
46 FunctionLoweringInfo *FuncInfo;
48 MachineRegisterInfo *RegInfo;
50 SelectionDAGBuilder *SDB;
53 CodeGenOpt::Level OptLevel;
56 explicit SelectionDAGISel(TargetMachine &tm,
57 CodeGenOpt::Level OL = CodeGenOpt::Default);
58 virtual ~SelectionDAGISel();
60 const TargetLowering *getTargetLowering() const {
61 return TM.getSubtargetImpl()->getTargetLowering();
64 void getAnalysisUsage(AnalysisUsage &AU) const override;
66 bool runOnMachineFunction(MachineFunction &MF) override;
68 virtual void EmitFunctionEntryCode() {}
70 /// PreprocessISelDAG - This hook allows targets to hack on the graph before
71 /// instruction selection starts.
72 virtual void PreprocessISelDAG() {}
74 /// PostprocessISelDAG() - This hook allows the target to hack on the graph
75 /// right after selection.
76 virtual void PostprocessISelDAG() {}
78 /// Select - Main hook targets implement to select a node.
79 virtual SDNode *Select(SDNode *N) = 0;
81 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
82 /// addressing mode, according to the specified constraint code. If this does
83 /// not match or is not implemented, return true. The resultant operands
84 /// (which will appear in the machine instruction) should be added to the
86 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
88 std::vector<SDValue> &OutOps) {
92 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
93 /// operand node N of U during instruction selection that starts at Root.
94 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
96 /// IsLegalToFold - Returns true if the specific operand node N of
97 /// U can be folded during instruction selection that starts at Root.
98 /// FIXME: This is a static member function because the MSP430/X86
99 /// targets, which uses it during isel. This could become a proper member.
100 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
101 CodeGenOpt::Level OptLevel,
102 bool IgnoreChains = false);
104 // Opcodes used by the DAG state machine:
105 enum BuiltinOpcodes {
108 OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
109 OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
111 OPC_CaptureGlueInput,
115 OPC_CheckChild0Same, OPC_CheckChild1Same,
116 OPC_CheckChild2Same, OPC_CheckChild3Same,
117 OPC_CheckPatternPredicate,
123 OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
124 OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
125 OPC_CheckChild6Type, OPC_CheckChild7Type,
127 OPC_CheckChild0Integer, OPC_CheckChild1Integer, OPC_CheckChild2Integer,
128 OPC_CheckChild3Integer, OPC_CheckChild4Integer,
132 OPC_CheckAndImm, OPC_CheckOrImm,
133 OPC_CheckFoldableChainNode,
138 OPC_EmitConvertToTarget,
139 OPC_EmitMergeInputChains,
140 OPC_EmitMergeInputChains1_0,
141 OPC_EmitMergeInputChains1_1,
151 OPFL_None = 0, // Node has no chain or glue input and isn't variadic.
152 OPFL_Chain = 1, // Node has a chain input.
153 OPFL_GlueInput = 2, // Node has a glue input.
154 OPFL_GlueOutput = 4, // Node has a glue output.
155 OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
156 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs.
157 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs.
158 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs.
159 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs.
160 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs.
161 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs.
162 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs.
164 OPFL_VariadicInfo = OPFL_Variadic6
167 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
168 /// number of fixed arity values that should be skipped when copying from the
170 static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
171 return ((Flags&OPFL_VariadicInfo) >> 4)-1;
176 /// DAGSize - Size of DAG being instruction selected.
180 /// ReplaceUses - replace all uses of the old node F with the use
181 /// of the new node T.
182 void ReplaceUses(SDValue F, SDValue T) {
183 CurDAG->ReplaceAllUsesOfValueWith(F, T);
186 /// ReplaceUses - replace all uses of the old nodes F with the use
187 /// of the new nodes T.
188 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
189 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num);
192 /// ReplaceUses - replace all uses of the old node F with the use
193 /// of the new node T.
194 void ReplaceUses(SDNode *F, SDNode *T) {
195 CurDAG->ReplaceAllUsesWith(F, T);
199 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
200 /// by tblgen. Others should not call it.
201 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
205 // Calls to these predicates are generated by tblgen.
206 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
207 int64_t DesiredMaskS) const;
208 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
209 int64_t DesiredMaskS) const;
212 /// CheckPatternPredicate - This function is generated by tblgen in the
213 /// target. It runs the specified pattern predicate and returns true if it
214 /// succeeds or false if it fails. The number is a private implementation
215 /// detail to the code tblgen produces.
216 virtual bool CheckPatternPredicate(unsigned PredNo) const {
217 llvm_unreachable("Tblgen should generate the implementation of this!");
220 /// CheckNodePredicate - This function is generated by tblgen in the target.
221 /// It runs node predicate number PredNo and returns true if it succeeds or
222 /// false if it fails. The number is a private implementation
223 /// detail to the code tblgen produces.
224 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
225 llvm_unreachable("Tblgen should generate the implementation of this!");
228 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
230 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
231 llvm_unreachable("Tblgen should generate the implementation of this!");
234 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
235 llvm_unreachable("Tblgen should generate this!");
238 SDNode *SelectCodeCommon(SDNode *NodeToMatch,
239 const unsigned char *MatcherTable,
242 /// \brief Return true if complex patterns for this target can mutate the
244 virtual bool ComplexPatternFuncMutatesDAG() const {
250 // Calls to these functions are generated by tblgen.
251 SDNode *Select_INLINEASM(SDNode *N);
252 SDNode *Select_READ_REGISTER(SDNode *N);
253 SDNode *Select_WRITE_REGISTER(SDNode *N);
254 SDNode *Select_UNDEF(SDNode *N);
255 void CannotYetSelect(SDNode *N);
258 void DoInstructionSelection();
259 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs,
260 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
262 void PrepareEHLandingPad();
264 /// \brief Perform instruction selection on all basic blocks in the function.
265 void SelectAllBasicBlocks(const Function &Fn);
267 /// \brief Perform instruction selection on a single basic block, for
268 /// instructions between \p Begin and \p End. \p HadTailCall will be set
269 /// to true if a call in the block was translated as a tail call.
270 void SelectBasicBlock(BasicBlock::const_iterator Begin,
271 BasicBlock::const_iterator End,
273 void FinishBasicBlock();
275 void CodeGenAndEmitDAG();
277 /// \brief Generate instructions for lowering the incoming arguments of the
279 void LowerArguments(const Function &F);
281 void ComputeLiveOutVRegInfo();
283 /// Create the scheduler. If a specific scheduler was specified
284 /// via the SchedulerRegistry, use it, otherwise select the
285 /// one preferred by the target.
287 ScheduleDAGSDNodes *CreateScheduler();
289 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
290 /// state machines that start with a OPC_SwitchOpcode node.
291 std::vector<unsigned> OpcodeOffset;
293 void UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
294 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
295 SDValue InputGlue, const SmallVectorImpl<SDNode*> &F,
302 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */