1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/BasicBlock.h"
19 #include "llvm/Pass.h"
20 #include "llvm/Constant.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
25 class SelectionDAGLowering;
27 class MachineRegisterInfo;
28 class MachineBasicBlock;
29 class MachineFunction;
31 class MachineModuleInfo;
33 class TargetInstrInfo;
34 class FunctionLoweringInfo;
35 class HazardRecognizer;
39 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
40 /// pattern-matching instruction selectors.
41 class SelectionDAGISel : public FunctionPass {
44 MachineRegisterInfo *RegInfo;
45 FunctionLoweringInfo *FuncInfo;
47 SelectionDAGLowering *SDL;
48 MachineBasicBlock *BB;
54 explicit SelectionDAGISel(TargetLowering &tli, bool fast = false);
55 virtual ~SelectionDAGISel();
57 TargetLowering &getTargetLowering() { return TLI; }
59 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
61 virtual bool runOnFunction(Function &Fn);
63 unsigned MakeReg(MVT VT);
65 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
66 virtual void InstructionSelect() = 0;
68 void SelectRootInit() {
69 DAGSize = CurDAG->AssignTopologicalOrder();
72 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
73 /// addressing mode, according to the specified constraint code. If this does
74 /// not match or is not implemented, return true. The resultant operands
75 /// (which will appear in the machine instruction) should be added to the
77 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
79 std::vector<SDValue> &OutOps) {
83 /// IsLegalAndProfitableToFold - Returns true if the specific operand node N of
84 /// U can be folded during instruction selection that starts at Root and
85 /// folding N is profitable.
87 bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const {
91 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
92 /// to use for this target when scheduling the DAG.
93 virtual HazardRecognizer *CreateTargetHazardRecognizer();
96 /// DAGSize - Size of DAG being instruction selected.
100 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
101 /// by tblgen. Others should not call it.
102 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
104 // Calls to these predicates are generated by tblgen.
105 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
106 int64_t DesiredMaskS) const;
107 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
108 int64_t DesiredMaskS) const;
111 void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
112 MachineModuleInfo *MMI,
113 const TargetInstrInfo &TII);
114 void FinishBasicBlock();
116 void SelectBasicBlock(BasicBlock *LLVMBB,
117 BasicBlock::iterator Begin,
118 BasicBlock::iterator End);
119 void CodeGenAndEmitDAG();
120 void LowerArguments(BasicBlock *BB);
122 void ComputeLiveOutVRegInfo();
124 void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
126 bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
128 /// Pick a safe ordering for instructions for each target node in the
130 ScheduleDAG *Schedule();
135 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */