1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/BasicBlock.h"
19 #include "llvm/Pass.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
25 class SelectionDAGBuilder;
27 class MachineRegisterInfo;
28 class MachineBasicBlock;
29 class MachineFunction;
32 class TargetInstrInfo;
33 class FunctionLoweringInfo;
34 class ScheduleHazardRecognizer;
36 class ScheduleDAGSDNodes;
38 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
39 /// pattern-matching instruction selectors.
40 class SelectionDAGISel : public MachineFunctionPass {
42 const TargetMachine &TM;
44 FunctionLoweringInfo *FuncInfo;
46 MachineRegisterInfo *RegInfo;
48 SelectionDAGBuilder *SDB;
49 MachineBasicBlock *BB;
52 CodeGenOpt::Level OptLevel;
55 explicit SelectionDAGISel(TargetMachine &tm,
56 CodeGenOpt::Level OL = CodeGenOpt::Default);
57 virtual ~SelectionDAGISel();
59 TargetLowering &getTargetLowering() { return TLI; }
61 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
63 virtual bool runOnMachineFunction(MachineFunction &MF);
65 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
67 /// PreprocessISelDAG - This hook allows targets to hack on the graph before
68 /// instruction selection starts.
69 virtual void PreprocessISelDAG() {}
71 /// PostprocessISelDAG() - This hook allows the target to hack on the graph
72 /// right after selection.
73 virtual void PostprocessISelDAG() {}
75 /// Select - Main hook targets implement to select a node.
76 virtual SDNode *Select(SDNode *N) = 0;
78 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
79 /// addressing mode, according to the specified constraint code. If this does
80 /// not match or is not implemented, return true. The resultant operands
81 /// (which will appear in the machine instruction) should be added to the
83 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
85 std::vector<SDValue> &OutOps) {
89 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
90 /// operand node N of U during instruction selection that starts at Root.
91 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
93 /// IsLegalToFold - Returns true if the specific operand node N of
94 /// U can be folded during instruction selection that starts at Root.
95 bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
96 bool IgnoreChains = false) const;
98 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
99 /// to use for this target when scheduling the DAG.
100 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
103 // Opcodes used by the DAG state machine:
104 enum BuiltinOpcodes {
107 OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
108 OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
110 OPC_CaptureFlagInput,
114 OPC_CheckPatternPredicate,
120 OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
121 OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
122 OPC_CheckChild6Type, OPC_CheckChild7Type,
127 OPC_CheckAndImm, OPC_CheckOrImm,
128 OPC_CheckFoldableChainNode,
132 OPC_EmitConvertToTarget,
133 OPC_EmitMergeInputChains,
134 OPC_EmitMergeInputChains1_0,
135 OPC_EmitMergeInputChains1_1,
145 OPFL_None = 0, // Node has no chain or flag input and isn't variadic.
146 OPFL_Chain = 1, // Node has a chain input.
147 OPFL_FlagInput = 2, // Node has a flag input.
148 OPFL_FlagOutput = 4, // Node has a flag output.
149 OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
150 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs.
151 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs.
152 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs.
153 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs.
154 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs.
155 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs.
156 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs.
158 OPFL_VariadicInfo = OPFL_Variadic6
161 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
162 /// number of fixed arity values that should be skipped when copying from the
164 static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
165 return ((Flags&OPFL_VariadicInfo) >> 4)-1;
170 /// DAGSize - Size of DAG being instruction selected.
174 /// ISelPosition - Node iterator marking the current position of
175 /// instruction selection as it procedes through the topologically-sorted
177 SelectionDAG::allnodes_iterator ISelPosition;
180 /// ISelUpdater - helper class to handle updates of the
181 /// instruction selection graph.
182 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
183 SelectionDAG::allnodes_iterator &ISelPosition;
185 explicit ISelUpdater(SelectionDAG::allnodes_iterator &isp)
186 : ISelPosition(isp) {}
188 /// NodeDeleted - Handle nodes deleted from the graph. If the
189 /// node being deleted is the current ISelPosition node, update
192 virtual void NodeDeleted(SDNode *N, SDNode *E) {
193 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
197 /// NodeUpdated - Ignore updates for now.
198 virtual void NodeUpdated(SDNode *N) {}
201 /// ReplaceUses - replace all uses of the old node F with the use
202 /// of the new node T.
203 void ReplaceUses(SDValue F, SDValue T) {
204 ISelUpdater ISU(ISelPosition);
205 CurDAG->ReplaceAllUsesOfValueWith(F, T, &ISU);
208 /// ReplaceUses - replace all uses of the old nodes F with the use
209 /// of the new nodes T.
210 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
211 ISelUpdater ISU(ISelPosition);
212 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num, &ISU);
215 /// ReplaceUses - replace all uses of the old node F with the use
216 /// of the new node T.
217 void ReplaceUses(SDNode *F, SDNode *T) {
218 ISelUpdater ISU(ISelPosition);
219 CurDAG->ReplaceAllUsesWith(F, T, &ISU);
223 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
224 /// by tblgen. Others should not call it.
225 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
229 // Calls to these predicates are generated by tblgen.
230 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
231 int64_t DesiredMaskS) const;
232 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
233 int64_t DesiredMaskS) const;
236 /// CheckPatternPredicate - This function is generated by tblgen in the
237 /// target. It runs the specified pattern predicate and returns true if it
238 /// succeeds or false if it fails. The number is a private implementation
239 /// detail to the code tblgen produces.
240 virtual bool CheckPatternPredicate(unsigned PredNo) const {
241 assert(0 && "Tblgen should generate the implementation of this!");
245 /// CheckNodePredicate - This function is generated by tblgen in the target.
246 /// It runs node predicate number PredNo and returns true if it succeeds or
247 /// false if it fails. The number is a private implementation
248 /// detail to the code tblgen produces.
249 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
250 assert(0 && "Tblgen should generate the implementation of this!");
254 virtual bool CheckComplexPattern(SDNode *Root, SDValue N, unsigned PatternNo,
255 SmallVectorImpl<SDValue> &Result) {
256 assert(0 && "Tblgen should generate the implementation of this!");
260 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
261 assert(0 && "Tblgen shoudl generate this!");
265 SDNode *SelectCodeCommon(SDNode *NodeToMatch,
266 const unsigned char *MatcherTable,
271 // Calls to these functions are generated by tblgen.
272 SDNode *Select_INLINEASM(SDNode *N);
273 SDNode *Select_UNDEF(SDNode *N);
274 void CannotYetSelect(SDNode *N);
277 void DoInstructionSelection();
278 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs,
279 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo);
281 void PrepareEHLandingPad(MachineBasicBlock *BB);
282 void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
283 const TargetInstrInfo &TII);
284 void FinishBasicBlock();
286 void SelectBasicBlock(BasicBlock *LLVMBB,
287 BasicBlock::iterator Begin,
288 BasicBlock::iterator End,
290 void CodeGenAndEmitDAG();
291 void LowerArguments(BasicBlock *BB);
293 void ShrinkDemandedOps();
294 void ComputeLiveOutVRegInfo();
296 void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
298 bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
300 /// Create the scheduler. If a specific scheduler was specified
301 /// via the SchedulerRegistry, use it, otherwise select the
302 /// one preferred by the target.
304 ScheduleDAGSDNodes *CreateScheduler();
306 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
307 /// state machines that start with a OPC_SwitchOpcode node.
308 std::vector<unsigned> OpcodeOffset;
310 void UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
311 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
312 SDValue InputFlag,const SmallVectorImpl<SDNode*> &F,
319 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */