1 //==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAGInstrs class, which implements
11 // scheduling for a MachineInstr-based dependency graph.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
16 #define LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
18 #include "llvm/ADT/SparseSet.h"
19 #include "llvm/ADT/SparseMultiSet.h"
20 #include "llvm/CodeGen/ScheduleDAG.h"
21 #include "llvm/CodeGen/TargetSchedule.h"
22 #include "llvm/Support/Compiler.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
26 class MachineFrameInfo;
27 class MachineLoopInfo;
28 class MachineDominatorTree;
30 class RegPressureTracker;
32 /// An individual mapping from virtual register number to SUnit.
37 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
39 unsigned getSparseSetIndex() const {
40 return TargetRegisterInfo::virtReg2Index(VirtReg);
44 /// Record a physical register access.
45 /// For non data-dependent uses, OpIdx == -1.
46 struct PhysRegSUOper {
51 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
53 unsigned getSparseSetIndex() const { return Reg; }
56 /// Use a SparseMultiSet to track physical registers. Storage is only
57 /// allocated once for the pass. It can be cleared in constant time and reused
58 /// without any frees.
59 typedef SparseMultiSet<PhysRegSUOper, llvm::identity<unsigned>, uint16_t>
62 /// Use SparseSet as a SparseMap by relying on the fact that it never
63 /// compares ValueT's, only unsigned keys. This allows the set to be cleared
64 /// between scheduling regions in constant time as long as ValueT does not
65 /// require a destructor.
66 typedef SparseSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2SUnitMap;
68 /// Track local uses of virtual registers. These uses are gathered by the DAG
69 /// builder and may be consulted by the scheduler to avoid iterating an entire
71 typedef SparseMultiSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2UseMap;
73 /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
75 class ScheduleDAGInstrs : public ScheduleDAG {
77 const MachineLoopInfo &MLI;
78 const MachineDominatorTree &MDT;
79 const MachineFrameInfo *MFI;
81 /// Live Intervals provides reaching defs in preRA scheduling.
84 /// TargetSchedModel provides an interface to the machine model.
85 TargetSchedModel SchedModel;
87 /// isPostRA flag indicates vregs cannot be present.
90 /// The standard DAG builder does not normally include terminators as DAG
91 /// nodes because it does not create the necessary dependencies to prevent
92 /// reordering. A specialized scheduler can overide
93 /// TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate
94 /// it has taken responsibility for scheduling the terminator correctly.
95 bool CanHandleTerminators;
97 /// State specific to the current scheduling region.
98 /// ------------------------------------------------
100 /// The block in which to insert instructions
101 MachineBasicBlock *BB;
103 /// The beginning of the range to be scheduled.
104 MachineBasicBlock::iterator RegionBegin;
106 /// The end of the range to be scheduled.
107 MachineBasicBlock::iterator RegionEnd;
109 /// Instructions in this region (distance(RegionBegin, RegionEnd)).
110 unsigned NumRegionInstrs;
112 /// After calling BuildSchedGraph, each machine instruction in the current
113 /// scheduling region is mapped to an SUnit.
114 DenseMap<MachineInstr*, SUnit*> MISUnitMap;
116 /// After calling BuildSchedGraph, each vreg used in the scheduling region
117 /// is mapped to a set of SUnits. These include all local vreg uses, not
118 /// just the uses for a singly defined vreg.
119 VReg2UseMap VRegUses;
121 /// State internal to DAG building.
122 /// -------------------------------
124 /// Defs, Uses - Remember where defs and uses of each register are as we
125 /// iterate upward through the instructions. This is allocated here instead
126 /// of inside BuildSchedGraph to avoid the need for it to be initialized and
127 /// destructed for each block.
131 /// Track the last instructon in this region defining each virtual register.
132 VReg2SUnitMap VRegDefs;
134 /// PendingLoads - Remember where unknown loads are after the most recent
135 /// unknown store, as we iterate. As with Defs and Uses, this is here
136 /// to minimize construction/destruction.
137 std::vector<SUnit *> PendingLoads;
139 /// DbgValues - Remember instruction that precedes DBG_VALUE.
140 /// These are generated by buildSchedGraph but persist so they can be
141 /// referenced when emitting the final schedule.
142 typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
144 DbgValueVector DbgValues;
145 MachineInstr *FirstDbgValue;
148 explicit ScheduleDAGInstrs(MachineFunction &mf,
149 const MachineLoopInfo &mli,
150 const MachineDominatorTree &mdt,
152 LiveIntervals *LIS = 0);
154 virtual ~ScheduleDAGInstrs() {}
156 /// \brief Expose LiveIntervals for use in DAG mutators and such.
157 LiveIntervals *getLIS() const { return LIS; }
159 /// \brief Get the machine model for instruction scheduling.
160 const TargetSchedModel *getSchedModel() const { return &SchedModel; }
162 /// \brief Resolve and cache a resolved scheduling class for an SUnit.
163 const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
164 if (!SU->SchedClass && SchedModel.hasInstrSchedModel())
165 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
166 return SU->SchedClass;
169 /// begin - Return an iterator to the top of the current scheduling region.
170 MachineBasicBlock::iterator begin() const { return RegionBegin; }
172 /// end - Return an iterator to the bottom of the current scheduling region.
173 MachineBasicBlock::iterator end() const { return RegionEnd; }
175 /// newSUnit - Creates a new SUnit and return a ptr to it.
176 SUnit *newSUnit(MachineInstr *MI);
178 /// getSUnit - Return an existing SUnit for this MI, or NULL.
179 SUnit *getSUnit(MachineInstr *MI) const;
181 /// startBlock - Prepare to perform scheduling in the given block.
182 virtual void startBlock(MachineBasicBlock *BB);
184 /// finishBlock - Clean up after scheduling in the given block.
185 virtual void finishBlock();
187 /// Initialize the scheduler state for the next scheduling region.
188 virtual void enterRegion(MachineBasicBlock *bb,
189 MachineBasicBlock::iterator begin,
190 MachineBasicBlock::iterator end,
191 unsigned regioninstrs);
193 /// Notify that the scheduler has finished scheduling the current region.
194 virtual void exitRegion();
196 /// buildSchedGraph - Build SUnits from the MachineBasicBlock that we are
198 void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker = 0);
200 /// addSchedBarrierDeps - Add dependencies from instructions in the current
201 /// list of instructions being scheduled to scheduling barrier. We want to
202 /// make sure instructions which define registers that are either used by
203 /// the terminator or are live-out are properly scheduled. This is
204 /// especially important when the definition latency of the return value(s)
205 /// are too high to be hidden by the branch or when the liveout registers
206 /// used by instructions in the fallthrough block.
207 void addSchedBarrierDeps();
209 /// schedule - Order nodes according to selected style, filling
210 /// in the Sequence member.
212 /// Typically, a scheduling algorithm will implement schedule() without
213 /// overriding enterRegion() or exitRegion().
214 virtual void schedule() = 0;
216 /// finalizeSchedule - Allow targets to perform final scheduling actions at
217 /// the level of the whole MachineFunction. By default does nothing.
218 virtual void finalizeSchedule() {}
220 virtual void dumpNode(const SUnit *SU) const;
222 /// Return a label for a DAG node that points to an instruction.
223 virtual std::string getGraphNodeLabel(const SUnit *SU) const;
225 /// Return a label for the region of code covered by the DAG.
226 virtual std::string getDAGName() const;
230 void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx);
231 void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
232 void addVRegDefDeps(SUnit *SU, unsigned OperIdx);
233 void addVRegUseDeps(SUnit *SU, unsigned OperIdx);
236 /// newSUnit - Creates a new SUnit and return a ptr to it.
237 inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) {
239 const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
241 SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
242 assert((Addr == 0 || Addr == &SUnits[0]) &&
243 "SUnits std::vector reallocated on the fly!");
244 SUnits.back().OrigNode = &SUnits.back();
245 return &SUnits.back();
248 /// getSUnit - Return an existing SUnit for this MI, or NULL.
249 inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const {
250 DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI);
251 if (I == MISUnitMap.end())