1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
28 class TargetRegisterClass;
34 /// Target-Independent Code Generator Pass Configuration Options.
36 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
37 /// to the internals of other CodeGen passes.
38 class TargetPassConfig : public ImmutablePass {
42 bool Initialized; // Flagged after all passes are configured.
44 // Target Pass Options
45 // Targets provide a default setting, user flags override.
49 /// Default setting for -enable-tail-merge on this target.
53 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
57 virtual ~TargetPassConfig();
61 /// Get the right type of TargetMachine for this target.
62 template<typename TMC> TMC &getTM() const {
63 return *static_cast<TMC*>(TM);
66 const TargetLowering *getTargetLowering() const {
67 return TM->getTargetLowering();
70 void setInitialized() { Initialized = true; }
72 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
74 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
76 bool getEnableTailMerge() const { return EnableTailMerge; }
77 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
79 bool getOptimizeRegAlloc() const;
81 /// Add common target configurable passes that perform LLVM IR to IR
82 /// transforms following machine independent optimization.
83 virtual void addIRPasses();
85 /// Add common passes that perform LLVM IR to IR transforms in preparation for
86 /// instruction selection.
87 virtual void addISelPrepare();
89 /// addInstSelector - This method should install an instruction selector pass,
90 /// which converts from LLVM code to machine instructions.
91 virtual bool addInstSelector() {
95 /// Add the complete, standard set of LLVM CodeGen passes.
96 /// Fully developed targets will not generally override this.
97 virtual void addMachinePasses();
100 // Helper to verify the analysis is really immutable.
101 void setOpt(bool &Opt, bool Val);
103 /// Methods with trivial inline returns are convenient points in the common
104 /// codegen pass pipeline where targets may insert passes. Methods with
105 /// out-of-line standard implementations are major CodeGen stages called by
106 /// addMachinePasses. Some targets may override major stages when inserting
107 /// passes is insufficient, but maintaining overriden stages is more work.
110 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
111 /// passes (which are run just before instruction selector).
112 virtual bool addPreISel() {
116 /// addMachineSSAOptimization - Add standard passes that optimize machine
117 /// instructions in SSA form.
118 virtual void addMachineSSAOptimization();
120 /// addPreRegAlloc - This method may be implemented by targets that want to
121 /// run passes immediately before register allocation. This should return
122 /// true if -print-machineinstrs should print after these passes.
123 virtual bool addPreRegAlloc() {
127 /// createTargetRegisterAllocator - Create the register allocator pass for
128 /// this target at the current optimization level.
129 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
131 /// addFastRegAlloc - Add the minimum set of target-independent passes that
132 /// are required for fast register allocation.
133 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
135 // addOptimizedRegAlloc - Add passes related to register allocation.
136 // LLVMTargetMachine provides standard regalloc passes for most targets.
137 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
139 /// addPostRegAlloc - This method may be implemented by targets that want
140 /// to run passes after register allocation but before prolog-epilog
141 /// insertion. This should return true if -print-machineinstrs should print
142 /// after these passes.
143 virtual bool addPostRegAlloc() {
147 /// Add passes that optimize machine instructions after register allocation.
148 virtual void addMachineLateOptimization();
150 /// addPreSched2 - This method may be implemented by targets that want to
151 /// run passes after prolog-epilog insertion and before the second instruction
152 /// scheduling pass. This should return true if -print-machineinstrs should
153 /// print after these passes.
154 virtual bool addPreSched2() {
158 /// Add standard basic block placement passes.
159 virtual void addBlockPlacement();
161 /// addPreEmitPass - This pass may be implemented by targets that want to run
162 /// passes immediately before machine code is emitted. This should return
163 /// true if -print-machineinstrs should print out the code after the passes.
164 virtual bool addPreEmitPass() {
168 /// Utilities for targets to add passes to the pass manager.
171 /// Add a target-independent CodeGen pass at this point in the pipeline.
172 void addPass(char &ID);
174 /// addMachinePasses helper to create the target-selected or overriden
176 FunctionPass *createRegAllocPass(bool Optimized);
178 /// printNoVerify - Add a pass to dump the machine function, if debugging is
181 void printNoVerify(const char *Banner) const;
183 /// printAndVerify - Add a pass to dump then verify the machine function, if
184 /// those steps are enabled.
186 void printAndVerify(const char *Banner) const;
190 /// List of target independent CodeGen pass IDs.
192 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
193 /// work well with unreachable basic blocks (what live ranges make sense for a
194 /// block that cannot be reached?). As such, a code generator should either
195 /// not instruction select unreachable blocks, or run this pass as its
196 /// last LLVM modifying pass to clean up blocks that are not reachable from
198 FunctionPass *createUnreachableBlockEliminationPass();
200 /// MachineFunctionPrinter pass - This pass prints out the machine function to
201 /// the given stream as a debugging tool.
202 MachineFunctionPass *
203 createMachineFunctionPrinterPass(raw_ostream &OS,
204 const std::string &Banner ="");
206 /// MachineLoopInfo - This pass is a loop analysis pass.
207 extern char &MachineLoopInfoID;
209 /// MachineLoopRanges - This pass is an on-demand loop coverage analysis.
210 extern char &MachineLoopRangesID;
212 /// MachineDominators - This pass is a machine dominators analysis pass.
213 extern char &MachineDominatorsID;
215 /// EdgeBundles analysis - Bundle machine CFG edges.
216 extern char &EdgeBundlesID;
218 /// LiveVariables pass - This pass computes the set of blocks in which each
219 /// variable is life and sets machine operand kill flags.
220 extern char &LiveVariablesID;
222 /// PHIElimination - This pass eliminates machine instruction PHI nodes
223 /// by inserting copy instructions. This destroys SSA information, but is the
224 /// desired input for some register allocators. This pass is "required" by
225 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
226 extern char &PHIEliminationID;
228 /// StrongPHIElimination - This pass eliminates machine instruction PHI
229 /// nodes by inserting copy instructions. This destroys SSA information, but
230 /// is the desired input for some register allocators. This pass is
231 /// "required" by these register allocator like this:
232 /// AU.addRequiredID(PHIEliminationID);
233 /// This pass is still in development
234 extern char &StrongPHIEliminationID;
236 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
237 extern char &LiveStacksID;
239 /// TwoAddressInstruction - This pass reduces two-address instructions to
240 /// use two operands. This destroys SSA information but it is desired by
241 /// register allocators.
242 extern char &TwoAddressInstructionPassID;
244 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
245 extern char &ProcessImplicitDefsID;
247 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
248 extern char &RegisterCoalescerID;
250 /// MachineScheduler - This pass schedules machine instructions.
251 extern char &MachineSchedulerID;
253 /// SpillPlacement analysis. Suggest optimal placement of spill code between
255 extern char &SpillPlacementID;
257 /// UnreachableMachineBlockElimination - This pass removes unreachable
258 /// machine basic blocks.
259 extern char &UnreachableMachineBlockElimID;
261 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
262 extern char &DeadMachineInstructionElimID;
264 /// FastRegisterAllocation Pass - This pass register allocates as fast as
265 /// possible. It is best suited for debug code where live ranges are short.
267 FunctionPass *createFastRegisterAllocator();
269 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
270 /// register allocator using the basic regalloc framework.
272 FunctionPass *createBasicRegisterAllocator();
274 /// Greedy register allocation pass - This pass implements a global register
275 /// allocator for optimized builds.
277 FunctionPass *createGreedyRegisterAllocator();
279 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
280 /// Quadratic Prograaming (PBQP) based register allocator.
282 FunctionPass *createDefaultPBQPRegisterAllocator();
284 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
285 /// and eliminates abstract frame references.
286 extern char &PrologEpilogCodeInserterID;
288 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
289 /// register allocation.
290 extern char &ExpandPostRAPseudosID;
292 /// createPostRAScheduler - This pass performs post register allocation
294 extern char &PostRASchedulerID;
296 /// BranchFolding - This pass performs machine code CFG based
297 /// optimizations to delete branches to branches, eliminate branches to
298 /// successor blocks (creating fall throughs), and eliminating branches over
300 extern char &BranchFolderPassID;
302 /// TailDuplicate - Duplicate blocks with unconditional branches
303 /// into tails of their predecessors.
304 extern char &TailDuplicateID;
306 /// IfConverter - This pass performs machine code if conversion.
307 extern char &IfConverterID;
309 /// MachineBlockPlacement - This pass places basic blocks based on branch
311 extern char &MachineBlockPlacementID;
313 /// MachineBlockPlacementStats - This pass collects statistics about the
314 /// basic block placement using branch probabilities and block frequency
316 extern char &MachineBlockPlacementStatsID;
318 /// Code Placement - This pass optimize code placement and aligns loop
319 /// headers to target specific alignment boundary.
320 extern char &CodePlacementOptID;
322 /// GCLowering Pass - Performs target-independent LLVM IR transformations for
323 /// highly portable strategies.
325 FunctionPass *createGCLoweringPass();
327 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
328 /// in machine code. Must be added very late during code generation, just
329 /// prior to output, and importantly after all CFG transformations (such as
331 extern char &GCMachineCodeAnalysisID;
333 /// Deleter Pass - Releases GC metadata.
335 FunctionPass *createGCInfoDeleter();
337 /// Creates a pass to print GC metadata.
339 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
341 /// MachineCSE - This pass performs global CSE on machine instructions.
342 extern char &MachineCSEID;
344 /// MachineLICM - This pass performs LICM on machine instructions.
345 extern char &MachineLICMID;
347 /// MachineSinking - This pass performs sinking on machine instructions.
348 extern char &MachineSinkingID;
350 /// MachineCopyPropagation - This pass performs copy propagation on
351 /// machine instructions.
352 extern char &MachineCopyPropagationID;
354 /// PeepholeOptimizer - This pass performs peephole optimizations -
355 /// like extension and comparison eliminations.
356 extern char &PeepholeOptimizerID;
358 /// OptimizePHIs - This pass optimizes machine instruction PHIs
359 /// to take advantage of opportunities created during DAG legalization.
360 extern char &OptimizePHIsID;
362 /// StackSlotColoring - This pass performs stack slot coloring.
363 extern char &StackSlotColoringID;
365 /// createStackProtectorPass - This pass adds stack protectors to functions.
367 FunctionPass *createStackProtectorPass(const TargetLowering *tli);
369 /// createMachineVerifierPass - This pass verifies cenerated machine code
370 /// instructions for correctness.
372 FunctionPass *createMachineVerifierPass(const char *Banner = 0);
374 /// createDwarfEHPass - This pass mulches exception handling code into a form
375 /// adapted to code generation. Required if using dwarf exception handling.
376 FunctionPass *createDwarfEHPass(const TargetMachine *tm);
378 /// createSjLjEHPass - This pass adapts exception handling code to use
379 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
381 FunctionPass *createSjLjEHPass(const TargetLowering *tli);
383 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
384 /// slots relative to one another and allocates base registers to access them
385 /// when it is estimated by the target to be out of range of normal frame
386 /// pointer or stack pointer index addressing.
387 extern char &LocalStackSlotAllocationID;
389 /// ExpandISelPseudos - This pass expands pseudo-instructions.
390 extern char &ExpandISelPseudosID;
392 /// createExecutionDependencyFixPass - This pass fixes execution time
393 /// problems with dependent instructions, such as switching execution
394 /// domains to match.
396 /// The pass will examine instructions using and defining registers in RC.
398 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
400 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
401 extern char &UnpackMachineBundlesID;
403 /// FinalizeMachineBundles - This pass finalize machine instruction
404 /// bundles (created earlier, e.g. during pre-RA scheduling).
405 extern char &FinalizeMachineBundlesID;
407 } // End llvm namespace