1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/IndexedMap.h"
19 #include "llvm/ADT/iterator_range.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBundle.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
29 /// MachineRegisterInfo - Keep track of information for virtual and physical
30 /// registers, including vreg register classes, use/def chains for registers,
32 class MachineRegisterInfo {
35 virtual void anchor();
37 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
39 virtual ~Delegate() {}
43 const MachineFunction *MF;
44 Delegate *TheDelegate;
46 /// IsSSA - True when the machine function is in SSA form and virtual
47 /// registers have a single def.
50 /// TracksLiveness - True while register liveness is being tracked accurately.
51 /// Basic block live-in lists, kill flags, and implicit defs may not be
52 /// accurate when after this flag is cleared.
55 /// VRegInfo - Information we keep for each virtual register.
57 /// Each element in this list contains the register class of the vreg and the
58 /// start of the use/def list for the register.
59 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
60 VirtReg2IndexFunctor> VRegInfo;
62 /// RegAllocHints - This vector records register allocation hints for virtual
63 /// registers. For each virtual register, it keeps a register and hint type
64 /// pair making up the allocation hint. Hint type is target specific except
65 /// for the value 0 which means the second value of the pair is the preferred
66 /// register for allocation. For example, if the hint is <0, 1024>, it means
67 /// the allocator should prefer the physical register allocated to the virtual
68 /// register of the hint.
69 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
71 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
72 /// physical registers.
73 std::vector<MachineOperand *> PhysRegUseDefLists;
75 /// getRegUseDefListHead - Return the head pointer for the register use/def
76 /// list for the specified virtual or physical register.
77 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
78 if (TargetRegisterInfo::isVirtualRegister(RegNo))
79 return VRegInfo[RegNo].second;
80 return PhysRegUseDefLists[RegNo];
83 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
84 if (TargetRegisterInfo::isVirtualRegister(RegNo))
85 return VRegInfo[RegNo].second;
86 return PhysRegUseDefLists[RegNo];
89 /// Get the next element in the use-def chain.
90 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
91 assert(MO && MO->isReg() && "This is not a register operand!");
92 return MO->Contents.Reg.Next;
95 /// UsedRegUnits - This is a bit vector that is computed and set by the
96 /// register allocator, and must be kept up to date by passes that run after
97 /// register allocation (though most don't modify this). This is used
98 /// so that the code generator knows which callee save registers to save and
99 /// for other target specific uses.
100 /// This vector has bits set for register units that are modified in the
101 /// current function. It doesn't include registers clobbered by function
102 /// calls with register mask operands.
103 BitVector UsedRegUnits;
105 /// UsedPhysRegMask - Additional used physregs including aliases.
106 /// This bit vector represents all the registers clobbered by function calls.
107 /// It can model things that UsedRegUnits can't, such as function calls that
108 /// clobber ymm7 but preserve the low half in xmm7.
109 BitVector UsedPhysRegMask;
111 /// ReservedRegs - This is a bit vector of reserved registers. The target
112 /// may change its mind about which registers should be reserved. This
113 /// vector is the frozen set of reserved registers when register allocation
115 BitVector ReservedRegs;
117 /// Keep track of the physical registers that are live in to the function.
118 /// Live in values are typically arguments in registers. LiveIn values are
119 /// allowed to have virtual registers associated with them, stored in the
121 std::vector<std::pair<unsigned, unsigned> > LiveIns;
123 MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
124 void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
126 explicit MachineRegisterInfo(const MachineFunction *MF);
128 const TargetRegisterInfo *getTargetRegisterInfo() const {
129 return MF->getSubtarget().getRegisterInfo();
132 void resetDelegate(Delegate *delegate) {
133 // Ensure another delegate does not take over unless the current
134 // delegate first unattaches itself. If we ever need to multicast
135 // notifications, we will need to change to using a list.
136 assert(TheDelegate == delegate &&
137 "Only the current delegate can perform reset!");
138 TheDelegate = nullptr;
141 void setDelegate(Delegate *delegate) {
142 assert(delegate && !TheDelegate &&
143 "Attempted to set delegate to null, or to change it without "
144 "first resetting it!");
146 TheDelegate = delegate;
149 //===--------------------------------------------------------------------===//
151 //===--------------------------------------------------------------------===//
153 // isSSA - Returns true when the machine function is in SSA form. Early
154 // passes require the machine function to be in SSA form where every virtual
155 // register has a single defining instruction.
157 // The TwoAddressInstructionPass and PHIElimination passes take the machine
158 // function out of SSA form when they introduce multiple defs per virtual
160 bool isSSA() const { return IsSSA; }
162 // leaveSSA - Indicates that the machine function is no longer in SSA form.
163 void leaveSSA() { IsSSA = false; }
165 /// tracksLiveness - Returns true when tracking register liveness accurately.
167 /// While this flag is true, register liveness information in basic block
168 /// live-in lists and machine instruction operands is accurate. This means it
169 /// can be used to change the code in ways that affect the values in
170 /// registers, for example by the register scavenger.
172 /// When this flag is false, liveness is no longer reliable.
173 bool tracksLiveness() const { return TracksLiveness; }
175 /// invalidateLiveness - Indicates that register liveness is no longer being
176 /// tracked accurately.
178 /// This should be called by late passes that invalidate the liveness
180 void invalidateLiveness() { TracksLiveness = false; }
182 //===--------------------------------------------------------------------===//
184 //===--------------------------------------------------------------------===//
186 // Strictly for use by MachineInstr.cpp.
187 void addRegOperandToUseList(MachineOperand *MO);
189 // Strictly for use by MachineInstr.cpp.
190 void removeRegOperandFromUseList(MachineOperand *MO);
192 // Strictly for use by MachineInstr.cpp.
193 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
195 /// Verify the sanity of the use list for Reg.
196 void verifyUseList(unsigned Reg) const;
198 /// Verify the use list of all registers.
199 void verifyUseLists() const;
201 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
202 /// and uses of a register within the MachineFunction that corresponds to this
203 /// MachineRegisterInfo object.
204 template<bool Uses, bool Defs, bool SkipDebug,
205 bool ByOperand, bool ByInstr, bool ByBundle>
206 class defusechain_iterator;
207 template<bool Uses, bool Defs, bool SkipDebug,
208 bool ByOperand, bool ByInstr, bool ByBundle>
209 class defusechain_instr_iterator;
211 // Make it a friend so it can access getNextOperandForReg().
212 template<bool, bool, bool, bool, bool, bool>
213 friend class defusechain_iterator;
214 template<bool, bool, bool, bool, bool, bool>
215 friend class defusechain_instr_iterator;
219 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
221 typedef defusechain_iterator<true,true,false,true,false,false>
223 reg_iterator reg_begin(unsigned RegNo) const {
224 return reg_iterator(getRegUseDefListHead(RegNo));
226 static reg_iterator reg_end() { return reg_iterator(nullptr); }
228 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const {
229 return iterator_range<reg_iterator>(reg_begin(Reg), reg_end());
232 /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
233 /// of the specified register, stepping by MachineInstr.
234 typedef defusechain_instr_iterator<true,true,false,false,true,false>
236 reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
237 return reg_instr_iterator(getRegUseDefListHead(RegNo));
239 static reg_instr_iterator reg_instr_end() {
240 return reg_instr_iterator(nullptr);
243 inline iterator_range<reg_instr_iterator>
244 reg_instructions(unsigned Reg) const {
245 return iterator_range<reg_instr_iterator>(reg_instr_begin(Reg),
249 /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
250 /// of the specified register, stepping by bundle.
251 typedef defusechain_instr_iterator<true,true,false,false,false,true>
253 reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
254 return reg_bundle_iterator(getRegUseDefListHead(RegNo));
256 static reg_bundle_iterator reg_bundle_end() {
257 return reg_bundle_iterator(nullptr);
260 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
261 return iterator_range<reg_bundle_iterator>(reg_bundle_begin(Reg),
265 /// reg_empty - Return true if there are no instructions using or defining the
266 /// specified register (it may be live-in).
267 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
269 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
270 /// of the specified register, skipping those marked as Debug.
271 typedef defusechain_iterator<true,true,true,true,false,false>
273 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
274 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
276 static reg_nodbg_iterator reg_nodbg_end() {
277 return reg_nodbg_iterator(nullptr);
280 inline iterator_range<reg_nodbg_iterator>
281 reg_nodbg_operands(unsigned Reg) const {
282 return iterator_range<reg_nodbg_iterator>(reg_nodbg_begin(Reg),
286 /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
287 /// all defs and uses of the specified register, stepping by MachineInstr,
288 /// skipping those marked as Debug.
289 typedef defusechain_instr_iterator<true,true,true,false,true,false>
290 reg_instr_nodbg_iterator;
291 reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const {
292 return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
294 static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
295 return reg_instr_nodbg_iterator(nullptr);
298 inline iterator_range<reg_instr_nodbg_iterator>
299 reg_nodbg_instructions(unsigned Reg) const {
300 return iterator_range<reg_instr_nodbg_iterator>(reg_instr_nodbg_begin(Reg),
301 reg_instr_nodbg_end());
304 /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
305 /// all defs and uses of the specified register, stepping by bundle,
306 /// skipping those marked as Debug.
307 typedef defusechain_instr_iterator<true,true,true,false,false,true>
308 reg_bundle_nodbg_iterator;
309 reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const {
310 return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
312 static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
313 return reg_bundle_nodbg_iterator(nullptr);
316 inline iterator_range<reg_bundle_nodbg_iterator>
317 reg_nodbg_bundles(unsigned Reg) const {
318 return iterator_range<reg_bundle_nodbg_iterator>(reg_bundle_nodbg_begin(Reg),
319 reg_bundle_nodbg_end());
322 /// reg_nodbg_empty - Return true if the only instructions using or defining
323 /// Reg are Debug instructions.
324 bool reg_nodbg_empty(unsigned RegNo) const {
325 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
328 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
329 typedef defusechain_iterator<false,true,false,true,false,false>
331 def_iterator def_begin(unsigned RegNo) const {
332 return def_iterator(getRegUseDefListHead(RegNo));
334 static def_iterator def_end() { return def_iterator(nullptr); }
336 inline iterator_range<def_iterator> def_operands(unsigned Reg) const {
337 return iterator_range<def_iterator>(def_begin(Reg), def_end());
340 /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
341 /// specified register, stepping by MachineInst.
342 typedef defusechain_instr_iterator<false,true,false,false,true,false>
344 def_instr_iterator def_instr_begin(unsigned RegNo) const {
345 return def_instr_iterator(getRegUseDefListHead(RegNo));
347 static def_instr_iterator def_instr_end() {
348 return def_instr_iterator(nullptr);
351 inline iterator_range<def_instr_iterator>
352 def_instructions(unsigned Reg) const {
353 return iterator_range<def_instr_iterator>(def_instr_begin(Reg),
357 /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
358 /// specified register, stepping by bundle.
359 typedef defusechain_instr_iterator<false,true,false,false,false,true>
361 def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
362 return def_bundle_iterator(getRegUseDefListHead(RegNo));
364 static def_bundle_iterator def_bundle_end() {
365 return def_bundle_iterator(nullptr);
368 inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const {
369 return iterator_range<def_bundle_iterator>(def_bundle_begin(Reg),
373 /// def_empty - Return true if there are no instructions defining the
374 /// specified register (it may be live-in).
375 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
377 /// hasOneDef - Return true if there is exactly one instruction defining the
378 /// specified register.
379 bool hasOneDef(unsigned RegNo) const {
380 def_iterator DI = def_begin(RegNo);
383 return ++DI == def_end();
386 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
387 typedef defusechain_iterator<true,false,false,true,false,false>
389 use_iterator use_begin(unsigned RegNo) const {
390 return use_iterator(getRegUseDefListHead(RegNo));
392 static use_iterator use_end() { return use_iterator(nullptr); }
394 inline iterator_range<use_iterator> use_operands(unsigned Reg) const {
395 return iterator_range<use_iterator>(use_begin(Reg), use_end());
398 /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
399 /// specified register, stepping by MachineInstr.
400 typedef defusechain_instr_iterator<true,false,false,false,true,false>
402 use_instr_iterator use_instr_begin(unsigned RegNo) const {
403 return use_instr_iterator(getRegUseDefListHead(RegNo));
405 static use_instr_iterator use_instr_end() {
406 return use_instr_iterator(nullptr);
409 inline iterator_range<use_instr_iterator>
410 use_instructions(unsigned Reg) const {
411 return iterator_range<use_instr_iterator>(use_instr_begin(Reg),
415 /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
416 /// specified register, stepping by bundle.
417 typedef defusechain_instr_iterator<true,false,false,false,false,true>
419 use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
420 return use_bundle_iterator(getRegUseDefListHead(RegNo));
422 static use_bundle_iterator use_bundle_end() {
423 return use_bundle_iterator(nullptr);
426 inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const {
427 return iterator_range<use_bundle_iterator>(use_bundle_begin(Reg),
431 /// use_empty - Return true if there are no instructions using the specified
433 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
435 /// hasOneUse - Return true if there is exactly one instruction using the
436 /// specified register.
437 bool hasOneUse(unsigned RegNo) const {
438 use_iterator UI = use_begin(RegNo);
441 return ++UI == use_end();
444 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
445 /// specified register, skipping those marked as Debug.
446 typedef defusechain_iterator<true,false,true,true,false,false>
448 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
449 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
451 static use_nodbg_iterator use_nodbg_end() {
452 return use_nodbg_iterator(nullptr);
455 inline iterator_range<use_nodbg_iterator>
456 use_nodbg_operands(unsigned Reg) const {
457 return iterator_range<use_nodbg_iterator>(use_nodbg_begin(Reg),
461 /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
462 /// all uses of the specified register, stepping by MachineInstr, skipping
463 /// those marked as Debug.
464 typedef defusechain_instr_iterator<true,false,true,false,true,false>
465 use_instr_nodbg_iterator;
466 use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const {
467 return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
469 static use_instr_nodbg_iterator use_instr_nodbg_end() {
470 return use_instr_nodbg_iterator(nullptr);
473 inline iterator_range<use_instr_nodbg_iterator>
474 use_nodbg_instructions(unsigned Reg) const {
475 return iterator_range<use_instr_nodbg_iterator>(use_instr_nodbg_begin(Reg),
476 use_instr_nodbg_end());
479 /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
480 /// all uses of the specified register, stepping by bundle, skipping
481 /// those marked as Debug.
482 typedef defusechain_instr_iterator<true,false,true,false,false,true>
483 use_bundle_nodbg_iterator;
484 use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const {
485 return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
487 static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
488 return use_bundle_nodbg_iterator(nullptr);
491 inline iterator_range<use_bundle_nodbg_iterator>
492 use_nodbg_bundles(unsigned Reg) const {
493 return iterator_range<use_bundle_nodbg_iterator>(use_bundle_nodbg_begin(Reg),
494 use_bundle_nodbg_end());
497 /// use_nodbg_empty - Return true if there are no non-Debug instructions
498 /// using the specified register.
499 bool use_nodbg_empty(unsigned RegNo) const {
500 return use_nodbg_begin(RegNo) == use_nodbg_end();
503 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
504 /// instruction using the specified register.
505 bool hasOneNonDBGUse(unsigned RegNo) const;
507 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
508 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
509 /// except that it also changes any definitions of the register as well.
511 /// Note that it is usually necessary to first constrain ToReg's register
512 /// class to match the FromReg constraints using:
514 /// constrainRegClass(ToReg, getRegClass(FromReg))
516 /// That function will return NULL if the virtual registers have incompatible
519 /// Note that if ToReg is a physical register the function will replace and
520 /// apply sub registers to ToReg in order to obtain a final/proper physical
522 void replaceRegWith(unsigned FromReg, unsigned ToReg);
524 /// getVRegDef - Return the machine instr that defines the specified virtual
525 /// register or null if none is found. This assumes that the code is in SSA
526 /// form, so there should only be one definition.
527 MachineInstr *getVRegDef(unsigned Reg) const;
529 /// getUniqueVRegDef - Return the unique machine instr that defines the
530 /// specified virtual register or null if none is found. If there are
531 /// multiple definitions or no definition, return null.
532 MachineInstr *getUniqueVRegDef(unsigned Reg) const;
534 /// clearKillFlags - Iterate over all the uses of the given register and
535 /// clear the kill flag from the MachineOperand. This function is used by
536 /// optimization passes which extend register lifetimes and need only
537 /// preserve conservative kill flag information.
538 void clearKillFlags(unsigned Reg) const;
541 void dumpUses(unsigned RegNo) const;
544 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
545 /// throughout the function. It is safe to move instructions that read such
547 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
549 /// Get an iterator over the pressure sets affected by the given physical or
550 /// virtual register. If RegUnit is physical, it must be a register unit (from
551 /// MCRegUnitIterator).
552 PSetIterator getPressureSets(unsigned RegUnit) const;
554 //===--------------------------------------------------------------------===//
555 // Virtual Register Info
556 //===--------------------------------------------------------------------===//
558 /// getRegClass - Return the register class of the specified virtual register.
560 const TargetRegisterClass *getRegClass(unsigned Reg) const {
561 return VRegInfo[Reg].first;
564 /// setRegClass - Set the register class of the specified virtual register.
566 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
568 /// constrainRegClass - Constrain the register class of the specified virtual
569 /// register to be a common subclass of RC and the current register class,
570 /// but only if the new class has at least MinNumRegs registers. Return the
571 /// new register class, or NULL if no such class exists.
572 /// This should only be used when the constraint is known to be trivial, like
573 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
575 const TargetRegisterClass *constrainRegClass(unsigned Reg,
576 const TargetRegisterClass *RC,
577 unsigned MinNumRegs = 0);
579 /// recomputeRegClass - Try to find a legal super-class of Reg's register
580 /// class that still satisfies the constraints from the instructions using
581 /// Reg. Returns true if Reg was upgraded.
583 /// This method can be used after constraints have been removed from a
584 /// virtual register, for example after removing instructions or splitting
587 bool recomputeRegClass(unsigned Reg, const TargetMachine&);
589 /// createVirtualRegister - Create and return a new virtual register in the
590 /// function with the specified register class.
592 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
594 /// getNumVirtRegs - Return the number of virtual registers created.
596 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
598 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
599 void clearVirtRegs();
601 /// setRegAllocationHint - Specify a register allocation hint for the
602 /// specified virtual register.
603 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
604 RegAllocHints[Reg].first = Type;
605 RegAllocHints[Reg].second = PrefReg;
608 /// getRegAllocationHint - Return the register allocation hint for the
609 /// specified virtual register.
610 std::pair<unsigned, unsigned>
611 getRegAllocationHint(unsigned Reg) const {
612 return RegAllocHints[Reg];
615 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
616 /// standard simple hint (Type == 0) is not set.
617 unsigned getSimpleHint(unsigned Reg) const {
618 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);
619 return Hint.first ? 0 : Hint.second;
622 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
623 /// specified register as undefined which causes the DBG_VALUE to be
624 /// deleted during LiveDebugVariables analysis.
625 void markUsesInDebugValueAsUndef(unsigned Reg) const;
627 //===--------------------------------------------------------------------===//
628 // Physical Register Use Info
629 //===--------------------------------------------------------------------===//
631 /// isPhysRegUsed - Return true if the specified register is used in this
632 /// function. Also check for clobbered aliases and registers clobbered by
633 /// function calls with register mask operands.
635 /// This only works after register allocation. It is primarily used by
636 /// PrologEpilogInserter to determine which callee-saved registers need
638 bool isPhysRegUsed(unsigned Reg) const {
639 if (UsedPhysRegMask.test(Reg))
641 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
642 Units.isValid(); ++Units)
643 if (UsedRegUnits.test(*Units))
648 /// Mark the specified register unit as used in this function.
649 /// This should only be called during and after register allocation.
650 void setRegUnitUsed(unsigned RegUnit) {
651 UsedRegUnits.set(RegUnit);
654 /// setPhysRegUsed - Mark the specified register used in this function.
655 /// This should only be called during and after register allocation.
656 void setPhysRegUsed(unsigned Reg) {
657 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
658 Units.isValid(); ++Units)
659 UsedRegUnits.set(*Units);
662 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
663 /// This corresponds to the bit mask attached to register mask operands.
664 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
665 UsedPhysRegMask.setBitsNotInMask(RegMask);
668 /// setPhysRegUnused - Mark the specified register unused in this function.
669 /// This should only be called during and after register allocation.
670 void setPhysRegUnused(unsigned Reg) {
671 UsedPhysRegMask.reset(Reg);
672 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
673 Units.isValid(); ++Units)
674 UsedRegUnits.reset(*Units);
678 //===--------------------------------------------------------------------===//
679 // Reserved Register Info
680 //===--------------------------------------------------------------------===//
682 // The set of reserved registers must be invariant during register
683 // allocation. For example, the target cannot suddenly decide it needs a
684 // frame pointer when the register allocator has already used the frame
685 // pointer register for something else.
687 // These methods can be used by target hooks like hasFP() to avoid changing
688 // the reserved register set during register allocation.
690 /// freezeReservedRegs - Called by the register allocator to freeze the set
691 /// of reserved registers before allocation begins.
692 void freezeReservedRegs(const MachineFunction&);
694 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
695 /// to ensure the set of reserved registers stays constant.
696 bool reservedRegsFrozen() const {
697 return !ReservedRegs.empty();
700 /// canReserveReg - Returns true if PhysReg can be used as a reserved
701 /// register. Any register can be reserved before freezeReservedRegs() is
703 bool canReserveReg(unsigned PhysReg) const {
704 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
707 /// getReservedRegs - Returns a reference to the frozen set of reserved
708 /// registers. This method should always be preferred to calling
709 /// TRI::getReservedRegs() when possible.
710 const BitVector &getReservedRegs() const {
711 assert(reservedRegsFrozen() &&
712 "Reserved registers haven't been frozen yet. "
713 "Use TRI::getReservedRegs().");
717 /// isReserved - Returns true when PhysReg is a reserved register.
719 /// Reserved registers may belong to an allocatable register class, but the
720 /// target has explicitly requested that they are not used.
722 bool isReserved(unsigned PhysReg) const {
723 return getReservedRegs().test(PhysReg);
726 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
727 /// register class and it hasn't been reserved.
729 /// Allocatable registers may show up in the allocation order of some virtual
730 /// register, so a register allocator needs to track its liveness and
732 bool isAllocatable(unsigned PhysReg) const {
733 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
734 !isReserved(PhysReg);
737 //===--------------------------------------------------------------------===//
739 //===--------------------------------------------------------------------===//
741 /// addLiveIn - Add the specified register as a live-in. Note that it
742 /// is an error to add the same register to the same set more than once.
743 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
744 LiveIns.push_back(std::make_pair(Reg, vreg));
747 // Iteration support for the live-ins set. It's kept in sorted order
748 // by register number.
749 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
751 livein_iterator livein_begin() const { return LiveIns.begin(); }
752 livein_iterator livein_end() const { return LiveIns.end(); }
753 bool livein_empty() const { return LiveIns.empty(); }
755 bool isLiveIn(unsigned Reg) const;
757 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
758 /// corresponding live-in physical register.
759 unsigned getLiveInPhysReg(unsigned VReg) const;
761 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
762 /// corresponding live-in physical register.
763 unsigned getLiveInVirtReg(unsigned PReg) const;
765 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
766 /// into the given entry block.
767 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
768 const TargetRegisterInfo &TRI,
769 const TargetInstrInfo &TII);
771 /// Returns a mask covering all bits that can appear in lane masks of
772 /// subregisters of the virtual register @p Reg.
773 unsigned getMaxLaneMaskForVReg(unsigned Reg) const;
775 /// defusechain_iterator - This class provides iterator support for machine
776 /// operands in the function that use or define a specific register. If
777 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
778 /// returns defs. If neither are true then you are silly and it always
779 /// returns end(). If SkipDebug is true it skips uses marked Debug
780 /// when incrementing.
781 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
782 bool ByOperand, bool ByInstr, bool ByBundle>
783 class defusechain_iterator
784 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
786 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
787 // If the first node isn't one we're interested in, advance to one that
788 // we are interested in.
790 if ((!ReturnUses && op->isUse()) ||
791 (!ReturnDefs && op->isDef()) ||
792 (SkipDebug && op->isDebug()))
796 friend class MachineRegisterInfo;
799 assert(Op && "Cannot increment end iterator!");
800 Op = getNextOperandForReg(Op);
802 // All defs come before the uses, so stop def_iterator early.
808 assert(!Op->isDebug() && "Can't have debug defs");
811 // If this is an operand we don't care about, skip it.
812 while (Op && ((!ReturnDefs && Op->isDef()) ||
813 (SkipDebug && Op->isDebug())))
814 Op = getNextOperandForReg(Op);
818 typedef std::iterator<std::forward_iterator_tag,
819 MachineInstr, ptrdiff_t>::reference reference;
820 typedef std::iterator<std::forward_iterator_tag,
821 MachineInstr, ptrdiff_t>::pointer pointer;
823 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
824 defusechain_iterator() : Op(nullptr) {}
826 bool operator==(const defusechain_iterator &x) const {
829 bool operator!=(const defusechain_iterator &x) const {
830 return !operator==(x);
833 /// atEnd - return true if this iterator is equal to reg_end() on the value.
834 bool atEnd() const { return Op == nullptr; }
836 // Iterator traversal: forward iteration only
837 defusechain_iterator &operator++() { // Preincrement
838 assert(Op && "Cannot increment end iterator!");
842 MachineInstr *P = Op->getParent();
845 } while (Op && Op->getParent() == P);
846 } else if (ByBundle) {
847 MachineInstr *P = getBundleStart(Op->getParent());
850 } while (Op && getBundleStart(Op->getParent()) == P);
855 defusechain_iterator operator++(int) { // Postincrement
856 defusechain_iterator tmp = *this; ++*this; return tmp;
859 /// getOperandNo - Return the operand # of this MachineOperand in its
861 unsigned getOperandNo() const {
862 assert(Op && "Cannot dereference end iterator!");
863 return Op - &Op->getParent()->getOperand(0);
866 // Retrieve a reference to the current operand.
867 MachineOperand &operator*() const {
868 assert(Op && "Cannot dereference end iterator!");
872 MachineOperand *operator->() const {
873 assert(Op && "Cannot dereference end iterator!");
878 /// defusechain_iterator - This class provides iterator support for machine
879 /// operands in the function that use or define a specific register. If
880 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
881 /// returns defs. If neither are true then you are silly and it always
882 /// returns end(). If SkipDebug is true it skips uses marked Debug
883 /// when incrementing.
884 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
885 bool ByOperand, bool ByInstr, bool ByBundle>
886 class defusechain_instr_iterator
887 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
889 explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
890 // If the first node isn't one we're interested in, advance to one that
891 // we are interested in.
893 if ((!ReturnUses && op->isUse()) ||
894 (!ReturnDefs && op->isDef()) ||
895 (SkipDebug && op->isDebug()))
899 friend class MachineRegisterInfo;
902 assert(Op && "Cannot increment end iterator!");
903 Op = getNextOperandForReg(Op);
905 // All defs come before the uses, so stop def_iterator early.
911 assert(!Op->isDebug() && "Can't have debug defs");
914 // If this is an operand we don't care about, skip it.
915 while (Op && ((!ReturnDefs && Op->isDef()) ||
916 (SkipDebug && Op->isDebug())))
917 Op = getNextOperandForReg(Op);
921 typedef std::iterator<std::forward_iterator_tag,
922 MachineInstr, ptrdiff_t>::reference reference;
923 typedef std::iterator<std::forward_iterator_tag,
924 MachineInstr, ptrdiff_t>::pointer pointer;
926 defusechain_instr_iterator(const defusechain_instr_iterator &I) : Op(I.Op){}
927 defusechain_instr_iterator() : Op(nullptr) {}
929 bool operator==(const defusechain_instr_iterator &x) const {
932 bool operator!=(const defusechain_instr_iterator &x) const {
933 return !operator==(x);
936 /// atEnd - return true if this iterator is equal to reg_end() on the value.
937 bool atEnd() const { return Op == nullptr; }
939 // Iterator traversal: forward iteration only
940 defusechain_instr_iterator &operator++() { // Preincrement
941 assert(Op && "Cannot increment end iterator!");
945 MachineInstr *P = Op->getParent();
948 } while (Op && Op->getParent() == P);
949 } else if (ByBundle) {
950 MachineInstr *P = getBundleStart(Op->getParent());
953 } while (Op && getBundleStart(Op->getParent()) == P);
958 defusechain_instr_iterator operator++(int) { // Postincrement
959 defusechain_instr_iterator tmp = *this; ++*this; return tmp;
962 // Retrieve a reference to the current operand.
963 MachineInstr &operator*() const {
964 assert(Op && "Cannot dereference end iterator!");
965 if (ByBundle) return *(getBundleStart(Op->getParent()));
966 return *Op->getParent();
969 MachineInstr *operator->() const {
970 assert(Op && "Cannot dereference end iterator!");
971 if (ByBundle) return getBundleStart(Op->getParent());
972 return Op->getParent();
977 /// Iterate over the pressure sets affected by the given physical or virtual
978 /// register. If Reg is physical, it must be a register unit (from
979 /// MCRegUnitIterator).
984 PSetIterator(): PSet(nullptr), Weight(0) {}
985 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
986 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
987 if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
988 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
989 PSet = TRI->getRegClassPressureSets(RC);
990 Weight = TRI->getRegClassWeight(RC).RegWeight;
993 PSet = TRI->getRegUnitPressureSets(RegUnit);
994 Weight = TRI->getRegUnitWeight(RegUnit);
999 bool isValid() const { return PSet; }
1001 unsigned getWeight() const { return Weight; }
1003 unsigned operator*() const { return *PSet; }
1006 assert(isValid() && "Invalid PSetIterator.");
1013 inline PSetIterator MachineRegisterInfo::
1014 getPressureSets(unsigned RegUnit) const {
1015 return PSetIterator(RegUnit, this);
1018 } // End llvm namespace