1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "llvm/ADT/BitVector.h"
23 /// MachineRegisterInfo - Keep track of information for virtual and physical
24 /// registers, including vreg register classes, use/def chains for registers,
26 class MachineRegisterInfo {
27 /// VRegInfo - Information we keep for each virtual register. The entries in
28 /// this vector are actually converted to vreg numbers by adding the
29 /// TargetRegisterInfo::FirstVirtualRegister delta to their index.
31 /// Each element in this list contains the register class of the vreg and the
32 /// start of the use/def list for the register.
33 std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo;
35 /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to
36 /// virtual registers. For each target register class, it keeps a list of
37 /// virtual registers belonging to the class.
38 std::vector<std::vector<unsigned> > RegClass2VRegMap;
40 /// RegAllocHints - This vector records register allocation hints for virtual
41 /// registers. For each virtual register, it keeps a register and hint type
42 /// pair making up the allocation hint. Hint type is target specific except
43 /// for the value 0 which means the second value of the pair is the preferred
44 /// register for allocation. For example, if the hint is <0, 1024>, it means
45 /// the allocator should prefer the physical register allocated to the virtual
46 /// register of the hint.
47 std::vector<std::pair<unsigned, unsigned> > RegAllocHints;
49 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
50 /// physical registers.
51 MachineOperand **PhysRegUseDefLists;
53 /// UsedPhysRegs - This is a bit vector that is computed and set by the
54 /// register allocator, and must be kept up to date by passes that run after
55 /// register allocation (though most don't modify this). This is used
56 /// so that the code generator knows which callee save registers to save and
57 /// for other target specific uses.
58 BitVector UsedPhysRegs;
60 /// LiveIns/LiveOuts - Keep track of the physical registers that are
61 /// livein/liveout of the function. Live in values are typically arguments in
62 /// registers, live out values are typically return values in registers.
63 /// LiveIn values are allowed to have virtual registers associated with them,
64 /// stored in the second element.
65 std::vector<std::pair<unsigned, unsigned> > LiveIns;
66 std::vector<unsigned> LiveOuts;
68 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
69 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT
71 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
72 ~MachineRegisterInfo();
74 //===--------------------------------------------------------------------===//
76 //===--------------------------------------------------------------------===//
78 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
79 /// and uses of a register within the MachineFunction that corresponds to this
80 /// MachineRegisterInfo object.
81 template<bool Uses, bool Defs, bool SkipDebug>
82 class defusechain_iterator;
84 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
86 typedef defusechain_iterator<true,true,false> reg_iterator;
87 reg_iterator reg_begin(unsigned RegNo) const {
88 return reg_iterator(getRegUseDefListHead(RegNo));
90 static reg_iterator reg_end() { return reg_iterator(0); }
92 /// reg_empty - Return true if there are no instructions using or defining the
93 /// specified register (it may be live-in).
94 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
96 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
97 typedef defusechain_iterator<false,true,false> def_iterator;
98 def_iterator def_begin(unsigned RegNo) const {
99 return def_iterator(getRegUseDefListHead(RegNo));
101 static def_iterator def_end() { return def_iterator(0); }
103 /// def_empty - Return true if there are no instructions defining the
104 /// specified register (it may be live-in).
105 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
107 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
108 typedef defusechain_iterator<true,false,false> use_iterator;
109 use_iterator use_begin(unsigned RegNo) const {
110 return use_iterator(getRegUseDefListHead(RegNo));
112 static use_iterator use_end() { return use_iterator(0); }
114 /// use_empty - Return true if there are no instructions using the specified
116 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
118 /// hasOneUse - Return true if there is exactly one instruction using the
119 /// specified register.
120 bool hasOneUse(unsigned RegNo) const;
122 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
123 /// specified register, skipping those marked as Debug.
124 typedef defusechain_iterator<true,false,true> use_nodbg_iterator;
125 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
126 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
128 static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); }
130 /// use_nodbg_empty - Return true if there are no non-Debug instructions
131 /// using the specified register.
132 bool use_nodbg_empty(unsigned RegNo) const {
133 return use_nodbg_begin(RegNo) == use_nodbg_end();
136 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
137 /// instruction using the specified register.
138 bool hasOneNonDBGUse(unsigned RegNo) const;
140 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
141 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
142 /// except that it also changes any definitions of the register as well.
143 void replaceRegWith(unsigned FromReg, unsigned ToReg);
145 /// getRegUseDefListHead - Return the head pointer for the register use/def
146 /// list for the specified virtual or physical register.
147 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
148 if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
149 return PhysRegUseDefLists[RegNo];
150 RegNo -= TargetRegisterInfo::FirstVirtualRegister;
151 return VRegInfo[RegNo].second;
154 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
155 if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
156 return PhysRegUseDefLists[RegNo];
157 RegNo -= TargetRegisterInfo::FirstVirtualRegister;
158 return VRegInfo[RegNo].second;
161 /// getVRegDef - Return the machine instr that defines the specified virtual
162 /// register or null if none is found. This assumes that the code is in SSA
163 /// form, so there should only be one definition.
164 MachineInstr *getVRegDef(unsigned Reg) const;
167 void dumpUses(unsigned RegNo) const;
170 //===--------------------------------------------------------------------===//
171 // Virtual Register Info
172 //===--------------------------------------------------------------------===//
174 /// getRegClass - Return the register class of the specified virtual register.
176 const TargetRegisterClass *getRegClass(unsigned Reg) const {
177 Reg -= TargetRegisterInfo::FirstVirtualRegister;
178 assert(Reg < VRegInfo.size() && "Invalid vreg!");
179 return VRegInfo[Reg].first;
182 /// setRegClass - Set the register class of the specified virtual register.
184 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
186 /// createVirtualRegister - Create and return a new virtual register in the
187 /// function with the specified register class.
189 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
191 /// getLastVirtReg - Return the highest currently assigned virtual register.
193 unsigned getLastVirtReg() const {
194 return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1;
197 /// getRegClassVirtRegs - Return the list of virtual registers of the given
198 /// target register class.
199 std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) {
200 return RegClass2VRegMap[RC->getID()];
203 /// setRegAllocationHint - Specify a register allocation hint for the
204 /// specified virtual register.
205 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
206 Reg -= TargetRegisterInfo::FirstVirtualRegister;
207 assert(Reg < VRegInfo.size() && "Invalid vreg!");
208 RegAllocHints[Reg].first = Type;
209 RegAllocHints[Reg].second = PrefReg;
212 /// getRegAllocationHint - Return the register allocation hint for the
213 /// specified virtual register.
214 std::pair<unsigned, unsigned>
215 getRegAllocationHint(unsigned Reg) const {
216 Reg -= TargetRegisterInfo::FirstVirtualRegister;
217 assert(Reg < VRegInfo.size() && "Invalid vreg!");
218 return RegAllocHints[Reg];
221 //===--------------------------------------------------------------------===//
222 // Physical Register Use Info
223 //===--------------------------------------------------------------------===//
225 /// isPhysRegUsed - Return true if the specified register is used in this
226 /// function. This only works after register allocation.
227 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; }
229 /// setPhysRegUsed - Mark the specified register used in this function.
230 /// This should only be called during and after register allocation.
231 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }
233 /// setPhysRegUnused - Mark the specified register unused in this function.
234 /// This should only be called during and after register allocation.
235 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }
238 //===--------------------------------------------------------------------===//
239 // LiveIn/LiveOut Management
240 //===--------------------------------------------------------------------===//
242 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it
243 /// is an error to add the same register to the same set more than once.
244 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
245 LiveIns.push_back(std::make_pair(Reg, vreg));
247 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
249 // Iteration support for live in/out sets. These sets are kept in sorted
250 // order by their register number.
251 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
253 typedef std::vector<unsigned>::const_iterator liveout_iterator;
254 livein_iterator livein_begin() const { return LiveIns.begin(); }
255 livein_iterator livein_end() const { return LiveIns.end(); }
256 bool livein_empty() const { return LiveIns.empty(); }
257 liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
258 liveout_iterator liveout_end() const { return LiveOuts.end(); }
259 bool liveout_empty() const { return LiveOuts.empty(); }
261 bool isLiveIn(unsigned Reg) const;
262 bool isLiveOut(unsigned Reg) const;
264 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
265 /// corresponding live-in physical register.
266 unsigned getLiveInPhysReg(unsigned VReg) const;
268 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
269 /// into the given entry block.
270 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
271 const TargetRegisterInfo &TRI,
272 const TargetInstrInfo &TII);
275 void HandleVRegListReallocation();
278 /// defusechain_iterator - This class provides iterator support for machine
279 /// operands in the function that use or define a specific register. If
280 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
281 /// returns defs. If neither are true then you are silly and it always
282 /// returns end(). If SkipDebug is true it skips uses marked Debug
283 /// when incrementing.
284 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug>
285 class defusechain_iterator
286 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
288 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
289 // If the first node isn't one we're interested in, advance to one that
290 // we are interested in.
292 if ((!ReturnUses && op->isUse()) ||
293 (!ReturnDefs && op->isDef()) ||
294 (SkipDebug && op->isDebug()))
298 friend class MachineRegisterInfo;
300 typedef std::iterator<std::forward_iterator_tag,
301 MachineInstr, ptrdiff_t>::reference reference;
302 typedef std::iterator<std::forward_iterator_tag,
303 MachineInstr, ptrdiff_t>::pointer pointer;
305 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
306 defusechain_iterator() : Op(0) {}
308 bool operator==(const defusechain_iterator &x) const {
311 bool operator!=(const defusechain_iterator &x) const {
312 return !operator==(x);
315 /// atEnd - return true if this iterator is equal to reg_end() on the value.
316 bool atEnd() const { return Op == 0; }
318 // Iterator traversal: forward iteration only
319 defusechain_iterator &operator++() { // Preincrement
320 assert(Op && "Cannot increment end iterator!");
321 Op = Op->getNextOperandForReg();
323 // If this is an operand we don't care about, skip it.
324 while (Op && ((!ReturnUses && Op->isUse()) ||
325 (!ReturnDefs && Op->isDef()) ||
326 (SkipDebug && Op->isDebug())))
327 Op = Op->getNextOperandForReg();
331 defusechain_iterator operator++(int) { // Postincrement
332 defusechain_iterator tmp = *this; ++*this; return tmp;
335 MachineOperand &getOperand() const {
336 assert(Op && "Cannot dereference end iterator!");
340 /// getOperandNo - Return the operand # of this MachineOperand in its
342 unsigned getOperandNo() const {
343 assert(Op && "Cannot dereference end iterator!");
344 return Op - &Op->getParent()->getOperand(0);
347 // Retrieve a reference to the current operand.
348 MachineInstr &operator*() const {
349 assert(Op && "Cannot dereference end iterator!");
350 return *Op->getParent();
353 MachineInstr *operator->() const {
354 assert(Op && "Cannot dereference end iterator!");
355 return Op->getParent();
361 } // End llvm namespace