1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/IndexedMap.h"
19 #include "llvm/CodeGen/MachineInstrBundle.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetRegisterInfo.h"
27 /// MachineRegisterInfo - Keep track of information for virtual and physical
28 /// registers, including vreg register classes, use/def chains for registers,
30 class MachineRegisterInfo {
34 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) {}
36 virtual ~Delegate() {}
40 const TargetMachine &TM;
41 Delegate *TheDelegate;
43 /// IsSSA - True when the machine function is in SSA form and virtual
44 /// registers have a single def.
47 /// TracksLiveness - True while register liveness is being tracked accurately.
48 /// Basic block live-in lists, kill flags, and implicit defs may not be
49 /// accurate when after this flag is cleared.
52 /// VRegInfo - Information we keep for each virtual register.
54 /// Each element in this list contains the register class of the vreg and the
55 /// start of the use/def list for the register.
56 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
57 VirtReg2IndexFunctor> VRegInfo;
59 /// RegAllocHints - This vector records register allocation hints for virtual
60 /// registers. For each virtual register, it keeps a register and hint type
61 /// pair making up the allocation hint. Hint type is target specific except
62 /// for the value 0 which means the second value of the pair is the preferred
63 /// register for allocation. For example, if the hint is <0, 1024>, it means
64 /// the allocator should prefer the physical register allocated to the virtual
65 /// register of the hint.
66 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
68 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
69 /// physical registers.
70 MachineOperand **PhysRegUseDefLists;
72 /// getRegUseDefListHead - Return the head pointer for the register use/def
73 /// list for the specified virtual or physical register.
74 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
75 if (TargetRegisterInfo::isVirtualRegister(RegNo))
76 return VRegInfo[RegNo].second;
77 return PhysRegUseDefLists[RegNo];
80 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
81 if (TargetRegisterInfo::isVirtualRegister(RegNo))
82 return VRegInfo[RegNo].second;
83 return PhysRegUseDefLists[RegNo];
86 /// Get the next element in the use-def chain.
87 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
88 assert(MO && MO->isReg() && "This is not a register operand!");
89 return MO->Contents.Reg.Next;
92 /// UsedRegUnits - This is a bit vector that is computed and set by the
93 /// register allocator, and must be kept up to date by passes that run after
94 /// register allocation (though most don't modify this). This is used
95 /// so that the code generator knows which callee save registers to save and
96 /// for other target specific uses.
97 /// This vector has bits set for register units that are modified in the
98 /// current function. It doesn't include registers clobbered by function
99 /// calls with register mask operands.
100 BitVector UsedRegUnits;
102 /// UsedPhysRegMask - Additional used physregs including aliases.
103 /// This bit vector represents all the registers clobbered by function calls.
104 /// It can model things that UsedRegUnits can't, such as function calls that
105 /// clobber ymm7 but preserve the low half in xmm7.
106 BitVector UsedPhysRegMask;
108 /// ReservedRegs - This is a bit vector of reserved registers. The target
109 /// may change its mind about which registers should be reserved. This
110 /// vector is the frozen set of reserved registers when register allocation
112 BitVector ReservedRegs;
114 /// Keep track of the physical registers that are live in to the function.
115 /// Live in values are typically arguments in registers. LiveIn values are
116 /// allowed to have virtual registers associated with them, stored in the
118 std::vector<std::pair<unsigned, unsigned> > LiveIns;
120 MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
121 void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
123 explicit MachineRegisterInfo(const TargetMachine &TM);
124 ~MachineRegisterInfo();
126 const TargetRegisterInfo *getTargetRegisterInfo() const {
127 return TM.getRegisterInfo();
130 void resetDelegate(Delegate *delegate) {
131 // Ensure another delegate does not take over unless the current
132 // delegate first unattaches itself. If we ever need to multicast
133 // notifications, we will need to change to using a list.
134 assert(TheDelegate == delegate &&
135 "Only the current delegate can perform reset!");
139 void setDelegate(Delegate *delegate) {
140 assert(delegate && !TheDelegate &&
141 "Attempted to set delegate to null, or to change it without "
142 "first resetting it!");
144 TheDelegate = delegate;
147 //===--------------------------------------------------------------------===//
149 //===--------------------------------------------------------------------===//
151 // isSSA - Returns true when the machine function is in SSA form. Early
152 // passes require the machine function to be in SSA form where every virtual
153 // register has a single defining instruction.
155 // The TwoAddressInstructionPass and PHIElimination passes take the machine
156 // function out of SSA form when they introduce multiple defs per virtual
158 bool isSSA() const { return IsSSA; }
160 // leaveSSA - Indicates that the machine function is no longer in SSA form.
161 void leaveSSA() { IsSSA = false; }
163 /// tracksLiveness - Returns true when tracking register liveness accurately.
165 /// While this flag is true, register liveness information in basic block
166 /// live-in lists and machine instruction operands is accurate. This means it
167 /// can be used to change the code in ways that affect the values in
168 /// registers, for example by the register scavenger.
170 /// When this flag is false, liveness is no longer reliable.
171 bool tracksLiveness() const { return TracksLiveness; }
173 /// invalidateLiveness - Indicates that register liveness is no longer being
174 /// tracked accurately.
176 /// This should be called by late passes that invalidate the liveness
178 void invalidateLiveness() { TracksLiveness = false; }
180 //===--------------------------------------------------------------------===//
182 //===--------------------------------------------------------------------===//
184 // Strictly for use by MachineInstr.cpp.
185 void addRegOperandToUseList(MachineOperand *MO);
187 // Strictly for use by MachineInstr.cpp.
188 void removeRegOperandFromUseList(MachineOperand *MO);
190 // Strictly for use by MachineInstr.cpp.
191 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
193 /// Verify the sanity of the use list for Reg.
194 void verifyUseList(unsigned Reg) const;
196 /// Verify the use list of all registers.
197 void verifyUseLists() const;
199 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
200 /// and uses of a register within the MachineFunction that corresponds to this
201 /// MachineRegisterInfo object.
202 template<bool Uses, bool Defs, bool SkipDebug>
203 class defusechain_iterator;
205 // Make it a friend so it can access getNextOperandForReg().
206 template<bool, bool, bool> friend class defusechain_iterator;
208 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
210 typedef defusechain_iterator<true,true,false> reg_iterator;
211 reg_iterator reg_begin(unsigned RegNo) const {
212 return reg_iterator(getRegUseDefListHead(RegNo));
214 static reg_iterator reg_end() { return reg_iterator(0); }
216 /// reg_empty - Return true if there are no instructions using or defining the
217 /// specified register (it may be live-in).
218 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
220 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
221 /// of the specified register, skipping those marked as Debug.
222 typedef defusechain_iterator<true,true,true> reg_nodbg_iterator;
223 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
224 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
226 static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); }
228 /// reg_nodbg_empty - Return true if the only instructions using or defining
229 /// Reg are Debug instructions.
230 bool reg_nodbg_empty(unsigned RegNo) const {
231 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
234 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
235 typedef defusechain_iterator<false,true,false> def_iterator;
236 def_iterator def_begin(unsigned RegNo) const {
237 return def_iterator(getRegUseDefListHead(RegNo));
239 static def_iterator def_end() { return def_iterator(0); }
241 /// def_empty - Return true if there are no instructions defining the
242 /// specified register (it may be live-in).
243 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
245 /// hasOneDef - Return true if there is exactly one instruction defining the
246 /// specified register.
247 bool hasOneDef(unsigned RegNo) const {
248 def_iterator DI = def_begin(RegNo);
251 return ++DI == def_end();
254 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
255 typedef defusechain_iterator<true,false,false> use_iterator;
256 use_iterator use_begin(unsigned RegNo) const {
257 return use_iterator(getRegUseDefListHead(RegNo));
259 static use_iterator use_end() { return use_iterator(0); }
261 /// use_empty - Return true if there are no instructions using the specified
263 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
265 /// hasOneUse - Return true if there is exactly one instruction using the
266 /// specified register.
267 bool hasOneUse(unsigned RegNo) const {
268 use_iterator UI = use_begin(RegNo);
271 return ++UI == use_end();
274 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
275 /// specified register, skipping those marked as Debug.
276 typedef defusechain_iterator<true,false,true> use_nodbg_iterator;
277 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
278 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
280 static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); }
282 /// use_nodbg_empty - Return true if there are no non-Debug instructions
283 /// using the specified register.
284 bool use_nodbg_empty(unsigned RegNo) const {
285 return use_nodbg_begin(RegNo) == use_nodbg_end();
288 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
289 /// instruction using the specified register.
290 bool hasOneNonDBGUse(unsigned RegNo) const;
292 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
293 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
294 /// except that it also changes any definitions of the register as well.
296 /// Note that it is usually necessary to first constrain ToReg's register
297 /// class to match the FromReg constraints using:
299 /// constrainRegClass(ToReg, getRegClass(FromReg))
301 /// That function will return NULL if the virtual registers have incompatible
303 void replaceRegWith(unsigned FromReg, unsigned ToReg);
305 /// getVRegDef - Return the machine instr that defines the specified virtual
306 /// register or null if none is found. This assumes that the code is in SSA
307 /// form, so there should only be one definition.
308 MachineInstr *getVRegDef(unsigned Reg) const;
310 /// getUniqueVRegDef - Return the unique machine instr that defines the
311 /// specified virtual register or null if none is found. If there are
312 /// multiple definitions or no definition, return null.
313 MachineInstr *getUniqueVRegDef(unsigned Reg) const;
315 /// clearKillFlags - Iterate over all the uses of the given register and
316 /// clear the kill flag from the MachineOperand. This function is used by
317 /// optimization passes which extend register lifetimes and need only
318 /// preserve conservative kill flag information.
319 void clearKillFlags(unsigned Reg) const;
322 void dumpUses(unsigned RegNo) const;
325 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
326 /// throughout the function. It is safe to move instructions that read such
328 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
330 /// Get an iterator over the pressure sets affected by the given physical or
331 /// virtual register. If RegUnit is physical, it must be a register unit (from
332 /// MCRegUnitIterator).
333 PSetIterator getPressureSets(unsigned RegUnit) const;
335 //===--------------------------------------------------------------------===//
336 // Virtual Register Info
337 //===--------------------------------------------------------------------===//
339 /// getRegClass - Return the register class of the specified virtual register.
341 const TargetRegisterClass *getRegClass(unsigned Reg) const {
342 return VRegInfo[Reg].first;
345 /// setRegClass - Set the register class of the specified virtual register.
347 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
349 /// constrainRegClass - Constrain the register class of the specified virtual
350 /// register to be a common subclass of RC and the current register class,
351 /// but only if the new class has at least MinNumRegs registers. Return the
352 /// new register class, or NULL if no such class exists.
353 /// This should only be used when the constraint is known to be trivial, like
354 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
356 const TargetRegisterClass *constrainRegClass(unsigned Reg,
357 const TargetRegisterClass *RC,
358 unsigned MinNumRegs = 0);
360 /// recomputeRegClass - Try to find a legal super-class of Reg's register
361 /// class that still satisfies the constraints from the instructions using
362 /// Reg. Returns true if Reg was upgraded.
364 /// This method can be used after constraints have been removed from a
365 /// virtual register, for example after removing instructions or splitting
368 bool recomputeRegClass(unsigned Reg, const TargetMachine&);
370 /// createVirtualRegister - Create and return a new virtual register in the
371 /// function with the specified register class.
373 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
375 /// getNumVirtRegs - Return the number of virtual registers created.
377 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
379 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
380 void clearVirtRegs();
382 /// setRegAllocationHint - Specify a register allocation hint for the
383 /// specified virtual register.
384 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
385 RegAllocHints[Reg].first = Type;
386 RegAllocHints[Reg].second = PrefReg;
389 /// getRegAllocationHint - Return the register allocation hint for the
390 /// specified virtual register.
391 std::pair<unsigned, unsigned>
392 getRegAllocationHint(unsigned Reg) const {
393 return RegAllocHints[Reg];
396 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
397 /// standard simple hint (Type == 0) is not set.
398 unsigned getSimpleHint(unsigned Reg) const {
399 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);
400 return Hint.first ? 0 : Hint.second;
404 //===--------------------------------------------------------------------===//
405 // Physical Register Use Info
406 //===--------------------------------------------------------------------===//
408 /// isPhysRegUsed - Return true if the specified register is used in this
409 /// function. Also check for clobbered aliases and registers clobbered by
410 /// function calls with register mask operands.
412 /// This only works after register allocation. It is primarily used by
413 /// PrologEpilogInserter to determine which callee-saved registers need
415 bool isPhysRegUsed(unsigned Reg) const {
416 if (UsedPhysRegMask.test(Reg))
418 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
419 Units.isValid(); ++Units)
420 if (UsedRegUnits.test(*Units))
425 /// Mark the specified register unit as used in this function.
426 /// This should only be called during and after register allocation.
427 void setRegUnitUsed(unsigned RegUnit) {
428 UsedRegUnits.set(RegUnit);
431 /// setPhysRegUsed - Mark the specified register used in this function.
432 /// This should only be called during and after register allocation.
433 void setPhysRegUsed(unsigned Reg) {
434 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
435 Units.isValid(); ++Units)
436 UsedRegUnits.set(*Units);
439 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
440 /// This corresponds to the bit mask attached to register mask operands.
441 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
442 UsedPhysRegMask.setBitsNotInMask(RegMask);
445 /// setPhysRegUnused - Mark the specified register unused in this function.
446 /// This should only be called during and after register allocation.
447 void setPhysRegUnused(unsigned Reg) {
448 UsedPhysRegMask.reset(Reg);
449 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
450 Units.isValid(); ++Units)
451 UsedRegUnits.reset(*Units);
455 //===--------------------------------------------------------------------===//
456 // Reserved Register Info
457 //===--------------------------------------------------------------------===//
459 // The set of reserved registers must be invariant during register
460 // allocation. For example, the target cannot suddenly decide it needs a
461 // frame pointer when the register allocator has already used the frame
462 // pointer register for something else.
464 // These methods can be used by target hooks like hasFP() to avoid changing
465 // the reserved register set during register allocation.
467 /// freezeReservedRegs - Called by the register allocator to freeze the set
468 /// of reserved registers before allocation begins.
469 void freezeReservedRegs(const MachineFunction&);
471 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
472 /// to ensure the set of reserved registers stays constant.
473 bool reservedRegsFrozen() const {
474 return !ReservedRegs.empty();
477 /// canReserveReg - Returns true if PhysReg can be used as a reserved
478 /// register. Any register can be reserved before freezeReservedRegs() is
480 bool canReserveReg(unsigned PhysReg) const {
481 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
484 /// getReservedRegs - Returns a reference to the frozen set of reserved
485 /// registers. This method should always be preferred to calling
486 /// TRI::getReservedRegs() when possible.
487 const BitVector &getReservedRegs() const {
488 assert(reservedRegsFrozen() &&
489 "Reserved registers haven't been frozen yet. "
490 "Use TRI::getReservedRegs().");
494 /// isReserved - Returns true when PhysReg is a reserved register.
496 /// Reserved registers may belong to an allocatable register class, but the
497 /// target has explicitly requested that they are not used.
499 bool isReserved(unsigned PhysReg) const {
500 return getReservedRegs().test(PhysReg);
503 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
504 /// register class and it hasn't been reserved.
506 /// Allocatable registers may show up in the allocation order of some virtual
507 /// register, so a register allocator needs to track its liveness and
509 bool isAllocatable(unsigned PhysReg) const {
510 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
511 !isReserved(PhysReg);
514 //===--------------------------------------------------------------------===//
516 //===--------------------------------------------------------------------===//
518 /// addLiveIn - Add the specified register as a live-in. Note that it
519 /// is an error to add the same register to the same set more than once.
520 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
521 LiveIns.push_back(std::make_pair(Reg, vreg));
524 // Iteration support for the live-ins set. It's kept in sorted order
525 // by register number.
526 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
528 livein_iterator livein_begin() const { return LiveIns.begin(); }
529 livein_iterator livein_end() const { return LiveIns.end(); }
530 bool livein_empty() const { return LiveIns.empty(); }
532 bool isLiveIn(unsigned Reg) const;
534 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
535 /// corresponding live-in physical register.
536 unsigned getLiveInPhysReg(unsigned VReg) const;
538 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
539 /// corresponding live-in physical register.
540 unsigned getLiveInVirtReg(unsigned PReg) const;
542 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
543 /// into the given entry block.
544 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
545 const TargetRegisterInfo &TRI,
546 const TargetInstrInfo &TII);
548 /// defusechain_iterator - This class provides iterator support for machine
549 /// operands in the function that use or define a specific register. If
550 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
551 /// returns defs. If neither are true then you are silly and it always
552 /// returns end(). If SkipDebug is true it skips uses marked Debug
553 /// when incrementing.
554 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug>
555 class defusechain_iterator
556 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
558 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
559 // If the first node isn't one we're interested in, advance to one that
560 // we are interested in.
562 if ((!ReturnUses && op->isUse()) ||
563 (!ReturnDefs && op->isDef()) ||
564 (SkipDebug && op->isDebug()))
568 friend class MachineRegisterInfo;
570 typedef std::iterator<std::forward_iterator_tag,
571 MachineInstr, ptrdiff_t>::reference reference;
572 typedef std::iterator<std::forward_iterator_tag,
573 MachineInstr, ptrdiff_t>::pointer pointer;
575 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
576 defusechain_iterator() : Op(0) {}
578 bool operator==(const defusechain_iterator &x) const {
581 bool operator!=(const defusechain_iterator &x) const {
582 return !operator==(x);
585 /// atEnd - return true if this iterator is equal to reg_end() on the value.
586 bool atEnd() const { return Op == 0; }
588 // Iterator traversal: forward iteration only
589 defusechain_iterator &operator++() { // Preincrement
590 assert(Op && "Cannot increment end iterator!");
591 Op = getNextOperandForReg(Op);
593 // All defs come before the uses, so stop def_iterator early.
599 assert(!Op->isDebug() && "Can't have debug defs");
602 // If this is an operand we don't care about, skip it.
603 while (Op && ((!ReturnDefs && Op->isDef()) ||
604 (SkipDebug && Op->isDebug())))
605 Op = getNextOperandForReg(Op);
610 defusechain_iterator operator++(int) { // Postincrement
611 defusechain_iterator tmp = *this; ++*this; return tmp;
614 /// skipInstruction - move forward until reaching a different instruction.
615 /// Return the skipped instruction that is no longer pointed to, or NULL if
616 /// already pointing to end().
617 MachineInstr *skipInstruction() {
619 MachineInstr *MI = Op->getParent();
621 while (Op && Op->getParent() == MI);
625 MachineInstr *skipBundle() {
627 MachineInstr *MI = getBundleStart(Op->getParent());
629 while (Op && getBundleStart(Op->getParent()) == MI);
633 MachineOperand &getOperand() const {
634 assert(Op && "Cannot dereference end iterator!");
638 /// getOperandNo - Return the operand # of this MachineOperand in its
640 unsigned getOperandNo() const {
641 assert(Op && "Cannot dereference end iterator!");
642 return Op - &Op->getParent()->getOperand(0);
645 // Retrieve a reference to the current operand.
646 MachineInstr &operator*() const {
647 assert(Op && "Cannot dereference end iterator!");
648 return *Op->getParent();
651 MachineInstr *operator->() const {
652 assert(Op && "Cannot dereference end iterator!");
653 return Op->getParent();
658 /// Iterate over the pressure sets affected by the given physical or virtual
659 /// register. If Reg is physical, it must be a register unit (from
660 /// MCRegUnitIterator).
665 PSetIterator(): PSet(0), Weight(0) {}
666 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
667 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
668 if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
669 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
670 PSet = TRI->getRegClassPressureSets(RC);
671 Weight = TRI->getRegClassWeight(RC).RegWeight;
674 PSet = TRI->getRegUnitPressureSets(RegUnit);
675 Weight = TRI->getRegUnitWeight(RegUnit);
680 bool isValid() const { return PSet; }
682 unsigned getWeight() const { return Weight; }
684 unsigned operator*() const { return *PSet; }
687 assert(isValid() && "Invalid PSetIterator.");
694 inline PSetIterator MachineRegisterInfo::
695 getPressureSets(unsigned RegUnit) const {
696 return PSetIterator(RegUnit, this);
699 } // End llvm namespace