1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/IndexedMap.h"
19 #include "llvm/ADT/iterator_range.h"
20 #include "llvm/CodeGen/MachineInstrBundle.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
28 /// MachineRegisterInfo - Keep track of information for virtual and physical
29 /// registers, including vreg register classes, use/def chains for registers,
31 class MachineRegisterInfo {
34 virtual void anchor();
36 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
38 virtual ~Delegate() {}
42 const TargetMachine &TM;
43 Delegate *TheDelegate;
45 /// IsSSA - True when the machine function is in SSA form and virtual
46 /// registers have a single def.
49 /// TracksLiveness - True while register liveness is being tracked accurately.
50 /// Basic block live-in lists, kill flags, and implicit defs may not be
51 /// accurate when after this flag is cleared.
54 /// VRegInfo - Information we keep for each virtual register.
56 /// Each element in this list contains the register class of the vreg and the
57 /// start of the use/def list for the register.
58 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
59 VirtReg2IndexFunctor> VRegInfo;
61 /// RegAllocHints - This vector records register allocation hints for virtual
62 /// registers. For each virtual register, it keeps a register and hint type
63 /// pair making up the allocation hint. Hint type is target specific except
64 /// for the value 0 which means the second value of the pair is the preferred
65 /// register for allocation. For example, if the hint is <0, 1024>, it means
66 /// the allocator should prefer the physical register allocated to the virtual
67 /// register of the hint.
68 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
70 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
71 /// physical registers.
72 MachineOperand **PhysRegUseDefLists;
74 /// getRegUseDefListHead - Return the head pointer for the register use/def
75 /// list for the specified virtual or physical register.
76 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
77 if (TargetRegisterInfo::isVirtualRegister(RegNo))
78 return VRegInfo[RegNo].second;
79 return PhysRegUseDefLists[RegNo];
82 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
83 if (TargetRegisterInfo::isVirtualRegister(RegNo))
84 return VRegInfo[RegNo].second;
85 return PhysRegUseDefLists[RegNo];
88 /// Get the next element in the use-def chain.
89 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
90 assert(MO && MO->isReg() && "This is not a register operand!");
91 return MO->Contents.Reg.Next;
94 /// UsedRegUnits - This is a bit vector that is computed and set by the
95 /// register allocator, and must be kept up to date by passes that run after
96 /// register allocation (though most don't modify this). This is used
97 /// so that the code generator knows which callee save registers to save and
98 /// for other target specific uses.
99 /// This vector has bits set for register units that are modified in the
100 /// current function. It doesn't include registers clobbered by function
101 /// calls with register mask operands.
102 BitVector UsedRegUnits;
104 /// UsedPhysRegMask - Additional used physregs including aliases.
105 /// This bit vector represents all the registers clobbered by function calls.
106 /// It can model things that UsedRegUnits can't, such as function calls that
107 /// clobber ymm7 but preserve the low half in xmm7.
108 BitVector UsedPhysRegMask;
110 /// ReservedRegs - This is a bit vector of reserved registers. The target
111 /// may change its mind about which registers should be reserved. This
112 /// vector is the frozen set of reserved registers when register allocation
114 BitVector ReservedRegs;
116 /// Keep track of the physical registers that are live in to the function.
117 /// Live in values are typically arguments in registers. LiveIn values are
118 /// allowed to have virtual registers associated with them, stored in the
120 std::vector<std::pair<unsigned, unsigned> > LiveIns;
122 MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
123 void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
125 explicit MachineRegisterInfo(const TargetMachine &TM);
126 ~MachineRegisterInfo();
128 const TargetRegisterInfo *getTargetRegisterInfo() const {
129 return TM.getRegisterInfo();
132 void resetDelegate(Delegate *delegate) {
133 // Ensure another delegate does not take over unless the current
134 // delegate first unattaches itself. If we ever need to multicast
135 // notifications, we will need to change to using a list.
136 assert(TheDelegate == delegate &&
137 "Only the current delegate can perform reset!");
138 TheDelegate = nullptr;
141 void setDelegate(Delegate *delegate) {
142 assert(delegate && !TheDelegate &&
143 "Attempted to set delegate to null, or to change it without "
144 "first resetting it!");
146 TheDelegate = delegate;
149 //===--------------------------------------------------------------------===//
151 //===--------------------------------------------------------------------===//
153 // isSSA - Returns true when the machine function is in SSA form. Early
154 // passes require the machine function to be in SSA form where every virtual
155 // register has a single defining instruction.
157 // The TwoAddressInstructionPass and PHIElimination passes take the machine
158 // function out of SSA form when they introduce multiple defs per virtual
160 bool isSSA() const { return IsSSA; }
162 // leaveSSA - Indicates that the machine function is no longer in SSA form.
163 void leaveSSA() { IsSSA = false; }
165 /// tracksLiveness - Returns true when tracking register liveness accurately.
167 /// While this flag is true, register liveness information in basic block
168 /// live-in lists and machine instruction operands is accurate. This means it
169 /// can be used to change the code in ways that affect the values in
170 /// registers, for example by the register scavenger.
172 /// When this flag is false, liveness is no longer reliable.
173 bool tracksLiveness() const { return TracksLiveness; }
175 /// invalidateLiveness - Indicates that register liveness is no longer being
176 /// tracked accurately.
178 /// This should be called by late passes that invalidate the liveness
180 void invalidateLiveness() { TracksLiveness = false; }
182 //===--------------------------------------------------------------------===//
184 //===--------------------------------------------------------------------===//
186 // Strictly for use by MachineInstr.cpp.
187 void addRegOperandToUseList(MachineOperand *MO);
189 // Strictly for use by MachineInstr.cpp.
190 void removeRegOperandFromUseList(MachineOperand *MO);
192 // Strictly for use by MachineInstr.cpp.
193 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
195 /// Verify the sanity of the use list for Reg.
196 void verifyUseList(unsigned Reg) const;
198 /// Verify the use list of all registers.
199 void verifyUseLists() const;
201 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
202 /// and uses of a register within the MachineFunction that corresponds to this
203 /// MachineRegisterInfo object.
204 template<bool Uses, bool Defs, bool SkipDebug,
205 bool ByOperand, bool ByInstr, bool ByBundle>
206 class defusechain_iterator;
207 template<bool Uses, bool Defs, bool SkipDebug,
208 bool ByOperand, bool ByInstr, bool ByBundle>
209 class defusechain_instr_iterator;
211 // Make it a friend so it can access getNextOperandForReg().
212 template<bool, bool, bool, bool, bool, bool>
213 friend class defusechain_iterator;
214 template<bool, bool, bool, bool, bool, bool>
215 friend class defusechain_instr_iterator;
219 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
221 typedef defusechain_iterator<true,true,false,true,false,false>
223 reg_iterator reg_begin(unsigned RegNo) const {
224 return reg_iterator(getRegUseDefListHead(RegNo));
226 static reg_iterator reg_end() { return reg_iterator(nullptr); }
228 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const {
229 return iterator_range<reg_iterator>(reg_begin(Reg), reg_end());
232 /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
233 /// of the specified register, stepping by MachineInstr.
234 typedef defusechain_instr_iterator<true,true,false,false,true,false>
236 reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
237 return reg_instr_iterator(getRegUseDefListHead(RegNo));
239 static reg_instr_iterator reg_instr_end() {
240 return reg_instr_iterator(nullptr);
243 inline iterator_range<reg_instr_iterator>
244 reg_instructions(unsigned Reg) const {
245 return iterator_range<reg_instr_iterator>(reg_instr_begin(Reg),
249 /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
250 /// of the specified register, stepping by bundle.
251 typedef defusechain_instr_iterator<true,true,false,false,false,true>
253 reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
254 return reg_bundle_iterator(getRegUseDefListHead(RegNo));
256 static reg_bundle_iterator reg_bundle_end() {
257 return reg_bundle_iterator(nullptr);
260 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
261 return iterator_range<reg_bundle_iterator>(reg_bundle_begin(Reg),
265 /// reg_empty - Return true if there are no instructions using or defining the
266 /// specified register (it may be live-in).
267 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
269 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
270 /// of the specified register, skipping those marked as Debug.
271 typedef defusechain_iterator<true,true,true,true,false,false>
273 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
274 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
276 static reg_nodbg_iterator reg_nodbg_end() {
277 return reg_nodbg_iterator(nullptr);
280 inline iterator_range<reg_nodbg_iterator>
281 reg_nodbg_operands(unsigned Reg) const {
282 return iterator_range<reg_nodbg_iterator>(reg_nodbg_begin(Reg),
286 /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
287 /// all defs and uses of the specified register, stepping by MachineInstr,
288 /// skipping those marked as Debug.
289 typedef defusechain_instr_iterator<true,true,true,false,true,false>
290 reg_instr_nodbg_iterator;
291 reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const {
292 return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
294 static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
295 return reg_instr_nodbg_iterator(nullptr);
298 inline iterator_range<reg_instr_nodbg_iterator>
299 reg_nodbg_instructions(unsigned Reg) const {
300 return iterator_range<reg_instr_nodbg_iterator>(reg_instr_nodbg_begin(Reg),
301 reg_instr_nodbg_end());
304 /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
305 /// all defs and uses of the specified register, stepping by bundle,
306 /// skipping those marked as Debug.
307 typedef defusechain_instr_iterator<true,true,true,false,false,true>
308 reg_bundle_nodbg_iterator;
309 reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const {
310 return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
312 static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
313 return reg_bundle_nodbg_iterator(nullptr);
316 inline iterator_range<reg_bundle_nodbg_iterator>
317 reg_nodbg_bundles(unsigned Reg) const {
318 return iterator_range<reg_bundle_nodbg_iterator>(reg_bundle_nodbg_begin(Reg),
319 reg_bundle_nodbg_end());
322 /// reg_nodbg_empty - Return true if the only instructions using or defining
323 /// Reg are Debug instructions.
324 bool reg_nodbg_empty(unsigned RegNo) const {
325 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
328 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
329 typedef defusechain_iterator<false,true,false,true,false,false>
331 def_iterator def_begin(unsigned RegNo) const {
332 return def_iterator(getRegUseDefListHead(RegNo));
334 static def_iterator def_end() { return def_iterator(nullptr); }
336 inline iterator_range<def_iterator> def_operands(unsigned Reg) const {
337 return iterator_range<def_iterator>(def_begin(Reg), def_end());
340 /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
341 /// specified register, stepping by MachineInst.
342 typedef defusechain_instr_iterator<false,true,false,false,true,false>
344 def_instr_iterator def_instr_begin(unsigned RegNo) const {
345 return def_instr_iterator(getRegUseDefListHead(RegNo));
347 static def_instr_iterator def_instr_end() {
348 return def_instr_iterator(nullptr);
351 inline iterator_range<def_instr_iterator>
352 def_instructions(unsigned Reg) const {
353 return iterator_range<def_instr_iterator>(def_instr_begin(Reg),
357 /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
358 /// specified register, stepping by bundle.
359 typedef defusechain_instr_iterator<false,true,false,false,false,true>
361 def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
362 return def_bundle_iterator(getRegUseDefListHead(RegNo));
364 static def_bundle_iterator def_bundle_end() {
365 return def_bundle_iterator(nullptr);
368 inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const {
369 return iterator_range<def_bundle_iterator>(def_bundle_begin(Reg),
373 /// def_empty - Return true if there are no instructions defining the
374 /// specified register (it may be live-in).
375 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
377 /// hasOneDef - Return true if there is exactly one instruction defining the
378 /// specified register.
379 bool hasOneDef(unsigned RegNo) const {
380 def_iterator DI = def_begin(RegNo);
383 return ++DI == def_end();
386 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
387 typedef defusechain_iterator<true,false,false,true,false,false>
389 use_iterator use_begin(unsigned RegNo) const {
390 return use_iterator(getRegUseDefListHead(RegNo));
392 static use_iterator use_end() { return use_iterator(nullptr); }
394 inline iterator_range<use_iterator> use_operands(unsigned Reg) const {
395 return iterator_range<use_iterator>(use_begin(Reg), use_end());
398 /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
399 /// specified register, stepping by MachineInstr.
400 typedef defusechain_instr_iterator<true,false,false,false,true,false>
402 use_instr_iterator use_instr_begin(unsigned RegNo) const {
403 return use_instr_iterator(getRegUseDefListHead(RegNo));
405 static use_instr_iterator use_instr_end() {
406 return use_instr_iterator(nullptr);
409 inline iterator_range<use_instr_iterator>
410 use_instructions(unsigned Reg) const {
411 return iterator_range<use_instr_iterator>(use_instr_begin(Reg),
415 /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
416 /// specified register, stepping by bundle.
417 typedef defusechain_instr_iterator<true,false,false,false,false,true>
419 use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
420 return use_bundle_iterator(getRegUseDefListHead(RegNo));
422 static use_bundle_iterator use_bundle_end() {
423 return use_bundle_iterator(nullptr);
426 inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const {
427 return iterator_range<use_bundle_iterator>(use_bundle_begin(Reg),
431 /// use_empty - Return true if there are no instructions using the specified
433 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
435 /// hasOneUse - Return true if there is exactly one instruction using the
436 /// specified register.
437 bool hasOneUse(unsigned RegNo) const {
438 use_iterator UI = use_begin(RegNo);
441 return ++UI == use_end();
444 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
445 /// specified register, skipping those marked as Debug.
446 typedef defusechain_iterator<true,false,true,true,false,false>
448 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
449 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
451 static use_nodbg_iterator use_nodbg_end() {
452 return use_nodbg_iterator(nullptr);
455 inline iterator_range<use_nodbg_iterator>
456 use_nodbg_operands(unsigned Reg) const {
457 return iterator_range<use_nodbg_iterator>(use_nodbg_begin(Reg),
461 /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
462 /// all uses of the specified register, stepping by MachineInstr, skipping
463 /// those marked as Debug.
464 typedef defusechain_instr_iterator<true,false,true,false,true,false>
465 use_instr_nodbg_iterator;
466 use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const {
467 return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
469 static use_instr_nodbg_iterator use_instr_nodbg_end() {
470 return use_instr_nodbg_iterator(nullptr);
473 inline iterator_range<use_instr_nodbg_iterator>
474 use_nodbg_instructions(unsigned Reg) const {
475 return iterator_range<use_instr_nodbg_iterator>(use_instr_nodbg_begin(Reg),
476 use_instr_nodbg_end());
479 /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
480 /// all uses of the specified register, stepping by bundle, skipping
481 /// those marked as Debug.
482 typedef defusechain_instr_iterator<true,false,true,false,false,true>
483 use_bundle_nodbg_iterator;
484 use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const {
485 return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
487 static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
488 return use_bundle_nodbg_iterator(nullptr);
491 inline iterator_range<use_bundle_nodbg_iterator>
492 use_nodbg_bundles(unsigned Reg) const {
493 return iterator_range<use_bundle_nodbg_iterator>(use_bundle_nodbg_begin(Reg),
494 use_bundle_nodbg_end());
497 /// use_nodbg_empty - Return true if there are no non-Debug instructions
498 /// using the specified register.
499 bool use_nodbg_empty(unsigned RegNo) const {
500 return use_nodbg_begin(RegNo) == use_nodbg_end();
503 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
504 /// instruction using the specified register.
505 bool hasOneNonDBGUse(unsigned RegNo) const;
507 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
508 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
509 /// except that it also changes any definitions of the register as well.
511 /// Note that it is usually necessary to first constrain ToReg's register
512 /// class to match the FromReg constraints using:
514 /// constrainRegClass(ToReg, getRegClass(FromReg))
516 /// That function will return NULL if the virtual registers have incompatible
518 void replaceRegWith(unsigned FromReg, unsigned ToReg);
520 /// getVRegDef - Return the machine instr that defines the specified virtual
521 /// register or null if none is found. This assumes that the code is in SSA
522 /// form, so there should only be one definition.
523 MachineInstr *getVRegDef(unsigned Reg) const;
525 /// getUniqueVRegDef - Return the unique machine instr that defines the
526 /// specified virtual register or null if none is found. If there are
527 /// multiple definitions or no definition, return null.
528 MachineInstr *getUniqueVRegDef(unsigned Reg) const;
530 /// clearKillFlags - Iterate over all the uses of the given register and
531 /// clear the kill flag from the MachineOperand. This function is used by
532 /// optimization passes which extend register lifetimes and need only
533 /// preserve conservative kill flag information.
534 void clearKillFlags(unsigned Reg) const;
537 void dumpUses(unsigned RegNo) const;
540 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
541 /// throughout the function. It is safe to move instructions that read such
543 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
545 /// Get an iterator over the pressure sets affected by the given physical or
546 /// virtual register. If RegUnit is physical, it must be a register unit (from
547 /// MCRegUnitIterator).
548 PSetIterator getPressureSets(unsigned RegUnit) const;
550 //===--------------------------------------------------------------------===//
551 // Virtual Register Info
552 //===--------------------------------------------------------------------===//
554 /// getRegClass - Return the register class of the specified virtual register.
556 const TargetRegisterClass *getRegClass(unsigned Reg) const {
557 return VRegInfo[Reg].first;
560 /// setRegClass - Set the register class of the specified virtual register.
562 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
564 /// constrainRegClass - Constrain the register class of the specified virtual
565 /// register to be a common subclass of RC and the current register class,
566 /// but only if the new class has at least MinNumRegs registers. Return the
567 /// new register class, or NULL if no such class exists.
568 /// This should only be used when the constraint is known to be trivial, like
569 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
571 const TargetRegisterClass *constrainRegClass(unsigned Reg,
572 const TargetRegisterClass *RC,
573 unsigned MinNumRegs = 0);
575 /// recomputeRegClass - Try to find a legal super-class of Reg's register
576 /// class that still satisfies the constraints from the instructions using
577 /// Reg. Returns true if Reg was upgraded.
579 /// This method can be used after constraints have been removed from a
580 /// virtual register, for example after removing instructions or splitting
583 bool recomputeRegClass(unsigned Reg, const TargetMachine&);
585 /// createVirtualRegister - Create and return a new virtual register in the
586 /// function with the specified register class.
588 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
590 /// getNumVirtRegs - Return the number of virtual registers created.
592 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
594 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
595 void clearVirtRegs();
597 /// setRegAllocationHint - Specify a register allocation hint for the
598 /// specified virtual register.
599 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
600 RegAllocHints[Reg].first = Type;
601 RegAllocHints[Reg].second = PrefReg;
604 /// getRegAllocationHint - Return the register allocation hint for the
605 /// specified virtual register.
606 std::pair<unsigned, unsigned>
607 getRegAllocationHint(unsigned Reg) const {
608 return RegAllocHints[Reg];
611 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
612 /// standard simple hint (Type == 0) is not set.
613 unsigned getSimpleHint(unsigned Reg) const {
614 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);
615 return Hint.first ? 0 : Hint.second;
618 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
619 /// specified register as undefined which causes the DBG_VALUE to be
620 /// deleted during LiveDebugVariables analysis.
621 void markUsesInDebugValueAsUndef(unsigned Reg) const;
623 //===--------------------------------------------------------------------===//
624 // Physical Register Use Info
625 //===--------------------------------------------------------------------===//
627 /// isPhysRegUsed - Return true if the specified register is used in this
628 /// function. Also check for clobbered aliases and registers clobbered by
629 /// function calls with register mask operands.
631 /// This only works after register allocation. It is primarily used by
632 /// PrologEpilogInserter to determine which callee-saved registers need
634 bool isPhysRegUsed(unsigned Reg) const {
635 if (UsedPhysRegMask.test(Reg))
637 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
638 Units.isValid(); ++Units)
639 if (UsedRegUnits.test(*Units))
644 /// Mark the specified register unit as used in this function.
645 /// This should only be called during and after register allocation.
646 void setRegUnitUsed(unsigned RegUnit) {
647 UsedRegUnits.set(RegUnit);
650 /// setPhysRegUsed - Mark the specified register used in this function.
651 /// This should only be called during and after register allocation.
652 void setPhysRegUsed(unsigned Reg) {
653 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
654 Units.isValid(); ++Units)
655 UsedRegUnits.set(*Units);
658 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
659 /// This corresponds to the bit mask attached to register mask operands.
660 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
661 UsedPhysRegMask.setBitsNotInMask(RegMask);
664 /// setPhysRegUnused - Mark the specified register unused in this function.
665 /// This should only be called during and after register allocation.
666 void setPhysRegUnused(unsigned Reg) {
667 UsedPhysRegMask.reset(Reg);
668 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
669 Units.isValid(); ++Units)
670 UsedRegUnits.reset(*Units);
674 //===--------------------------------------------------------------------===//
675 // Reserved Register Info
676 //===--------------------------------------------------------------------===//
678 // The set of reserved registers must be invariant during register
679 // allocation. For example, the target cannot suddenly decide it needs a
680 // frame pointer when the register allocator has already used the frame
681 // pointer register for something else.
683 // These methods can be used by target hooks like hasFP() to avoid changing
684 // the reserved register set during register allocation.
686 /// freezeReservedRegs - Called by the register allocator to freeze the set
687 /// of reserved registers before allocation begins.
688 void freezeReservedRegs(const MachineFunction&);
690 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
691 /// to ensure the set of reserved registers stays constant.
692 bool reservedRegsFrozen() const {
693 return !ReservedRegs.empty();
696 /// canReserveReg - Returns true if PhysReg can be used as a reserved
697 /// register. Any register can be reserved before freezeReservedRegs() is
699 bool canReserveReg(unsigned PhysReg) const {
700 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
703 /// getReservedRegs - Returns a reference to the frozen set of reserved
704 /// registers. This method should always be preferred to calling
705 /// TRI::getReservedRegs() when possible.
706 const BitVector &getReservedRegs() const {
707 assert(reservedRegsFrozen() &&
708 "Reserved registers haven't been frozen yet. "
709 "Use TRI::getReservedRegs().");
713 /// isReserved - Returns true when PhysReg is a reserved register.
715 /// Reserved registers may belong to an allocatable register class, but the
716 /// target has explicitly requested that they are not used.
718 bool isReserved(unsigned PhysReg) const {
719 return getReservedRegs().test(PhysReg);
722 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
723 /// register class and it hasn't been reserved.
725 /// Allocatable registers may show up in the allocation order of some virtual
726 /// register, so a register allocator needs to track its liveness and
728 bool isAllocatable(unsigned PhysReg) const {
729 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
730 !isReserved(PhysReg);
733 //===--------------------------------------------------------------------===//
735 //===--------------------------------------------------------------------===//
737 /// addLiveIn - Add the specified register as a live-in. Note that it
738 /// is an error to add the same register to the same set more than once.
739 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
740 LiveIns.push_back(std::make_pair(Reg, vreg));
743 // Iteration support for the live-ins set. It's kept in sorted order
744 // by register number.
745 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
747 livein_iterator livein_begin() const { return LiveIns.begin(); }
748 livein_iterator livein_end() const { return LiveIns.end(); }
749 bool livein_empty() const { return LiveIns.empty(); }
751 bool isLiveIn(unsigned Reg) const;
753 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
754 /// corresponding live-in physical register.
755 unsigned getLiveInPhysReg(unsigned VReg) const;
757 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
758 /// corresponding live-in physical register.
759 unsigned getLiveInVirtReg(unsigned PReg) const;
761 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
762 /// into the given entry block.
763 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
764 const TargetRegisterInfo &TRI,
765 const TargetInstrInfo &TII);
767 /// defusechain_iterator - This class provides iterator support for machine
768 /// operands in the function that use or define a specific register. If
769 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
770 /// returns defs. If neither are true then you are silly and it always
771 /// returns end(). If SkipDebug is true it skips uses marked Debug
772 /// when incrementing.
773 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
774 bool ByOperand, bool ByInstr, bool ByBundle>
775 class defusechain_iterator
776 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
778 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
779 // If the first node isn't one we're interested in, advance to one that
780 // we are interested in.
782 if ((!ReturnUses && op->isUse()) ||
783 (!ReturnDefs && op->isDef()) ||
784 (SkipDebug && op->isDebug()))
788 friend class MachineRegisterInfo;
791 assert(Op && "Cannot increment end iterator!");
792 Op = getNextOperandForReg(Op);
794 // All defs come before the uses, so stop def_iterator early.
800 assert(!Op->isDebug() && "Can't have debug defs");
803 // If this is an operand we don't care about, skip it.
804 while (Op && ((!ReturnDefs && Op->isDef()) ||
805 (SkipDebug && Op->isDebug())))
806 Op = getNextOperandForReg(Op);
810 typedef std::iterator<std::forward_iterator_tag,
811 MachineInstr, ptrdiff_t>::reference reference;
812 typedef std::iterator<std::forward_iterator_tag,
813 MachineInstr, ptrdiff_t>::pointer pointer;
815 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
816 defusechain_iterator() : Op(nullptr) {}
818 bool operator==(const defusechain_iterator &x) const {
821 bool operator!=(const defusechain_iterator &x) const {
822 return !operator==(x);
825 /// atEnd - return true if this iterator is equal to reg_end() on the value.
826 bool atEnd() const { return Op == nullptr; }
828 // Iterator traversal: forward iteration only
829 defusechain_iterator &operator++() { // Preincrement
830 assert(Op && "Cannot increment end iterator!");
834 MachineInstr *P = Op->getParent();
837 } while (Op && Op->getParent() == P);
838 } else if (ByBundle) {
839 MachineInstr *P = getBundleStart(Op->getParent());
842 } while (Op && getBundleStart(Op->getParent()) == P);
847 defusechain_iterator operator++(int) { // Postincrement
848 defusechain_iterator tmp = *this; ++*this; return tmp;
851 /// getOperandNo - Return the operand # of this MachineOperand in its
853 unsigned getOperandNo() const {
854 assert(Op && "Cannot dereference end iterator!");
855 return Op - &Op->getParent()->getOperand(0);
858 // Retrieve a reference to the current operand.
859 MachineOperand &operator*() const {
860 assert(Op && "Cannot dereference end iterator!");
864 MachineOperand *operator->() const {
865 assert(Op && "Cannot dereference end iterator!");
870 /// defusechain_iterator - This class provides iterator support for machine
871 /// operands in the function that use or define a specific register. If
872 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
873 /// returns defs. If neither are true then you are silly and it always
874 /// returns end(). If SkipDebug is true it skips uses marked Debug
875 /// when incrementing.
876 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
877 bool ByOperand, bool ByInstr, bool ByBundle>
878 class defusechain_instr_iterator
879 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
881 explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
882 // If the first node isn't one we're interested in, advance to one that
883 // we are interested in.
885 if ((!ReturnUses && op->isUse()) ||
886 (!ReturnDefs && op->isDef()) ||
887 (SkipDebug && op->isDebug()))
891 friend class MachineRegisterInfo;
894 assert(Op && "Cannot increment end iterator!");
895 Op = getNextOperandForReg(Op);
897 // All defs come before the uses, so stop def_iterator early.
903 assert(!Op->isDebug() && "Can't have debug defs");
906 // If this is an operand we don't care about, skip it.
907 while (Op && ((!ReturnDefs && Op->isDef()) ||
908 (SkipDebug && Op->isDebug())))
909 Op = getNextOperandForReg(Op);
913 typedef std::iterator<std::forward_iterator_tag,
914 MachineInstr, ptrdiff_t>::reference reference;
915 typedef std::iterator<std::forward_iterator_tag,
916 MachineInstr, ptrdiff_t>::pointer pointer;
918 defusechain_instr_iterator(const defusechain_instr_iterator &I) : Op(I.Op){}
919 defusechain_instr_iterator() : Op(nullptr) {}
921 bool operator==(const defusechain_instr_iterator &x) const {
924 bool operator!=(const defusechain_instr_iterator &x) const {
925 return !operator==(x);
928 /// atEnd - return true if this iterator is equal to reg_end() on the value.
929 bool atEnd() const { return Op == nullptr; }
931 // Iterator traversal: forward iteration only
932 defusechain_instr_iterator &operator++() { // Preincrement
933 assert(Op && "Cannot increment end iterator!");
937 MachineInstr *P = Op->getParent();
940 } while (Op && Op->getParent() == P);
941 } else if (ByBundle) {
942 MachineInstr *P = getBundleStart(Op->getParent());
945 } while (Op && getBundleStart(Op->getParent()) == P);
950 defusechain_instr_iterator operator++(int) { // Postincrement
951 defusechain_instr_iterator tmp = *this; ++*this; return tmp;
954 // Retrieve a reference to the current operand.
955 MachineInstr &operator*() const {
956 assert(Op && "Cannot dereference end iterator!");
957 if (ByBundle) return *(getBundleStart(Op->getParent()));
958 return *Op->getParent();
961 MachineInstr *operator->() const {
962 assert(Op && "Cannot dereference end iterator!");
963 if (ByBundle) return getBundleStart(Op->getParent());
964 return Op->getParent();
969 /// Iterate over the pressure sets affected by the given physical or virtual
970 /// register. If Reg is physical, it must be a register unit (from
971 /// MCRegUnitIterator).
976 PSetIterator(): PSet(nullptr), Weight(0) {}
977 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
978 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
979 if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
980 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
981 PSet = TRI->getRegClassPressureSets(RC);
982 Weight = TRI->getRegClassWeight(RC).RegWeight;
985 PSet = TRI->getRegUnitPressureSets(RegUnit);
986 Weight = TRI->getRegUnitWeight(RegUnit);
991 bool isValid() const { return PSet; }
993 unsigned getWeight() const { return Weight; }
995 unsigned operator*() const { return *PSet; }
998 assert(isValid() && "Invalid PSetIterator.");
1005 inline PSetIterator MachineRegisterInfo::
1006 getPressureSets(unsigned RegUnit) const {
1007 return PSetIterator(RegUnit, this);
1010 } // End llvm namespace