1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/Target/MRegisterInfo.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/iterator"
24 /// MachineRegisterInfo - Keep track of information for each virtual register,
25 /// including its register class.
26 class MachineRegisterInfo {
27 /// VRegInfo - Information we keep for each virtual register. The entries in
28 /// this vector are actually converted to vreg numbers by adding the
29 /// MRegisterInfo::FirstVirtualRegister delta to their index.
31 /// Each element in this list contains the register class of the vreg and the
32 /// start of the use/def list for the register.
33 std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo;
35 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
36 /// physical registers.
37 MachineOperand **PhysRegUseDefLists;
39 /// UsedPhysRegs - This is a bit vector that is computed and set by the
40 /// register allocator, and must be kept up to date by passes that run after
41 /// register allocation (though most don't modify this). This is used
42 /// so that the code generator knows which callee save registers to save and
43 /// for other target specific uses.
44 BitVector UsedPhysRegs;
46 /// LiveIns/LiveOuts - Keep track of the physical registers that are
47 /// livein/liveout of the function. Live in values are typically arguments in
48 /// registers, live out values are typically return values in registers.
49 /// LiveIn values are allowed to have virtual registers associated with them,
50 /// stored in the second element.
51 std::vector<std::pair<unsigned, unsigned> > LiveIns;
52 std::vector<unsigned> LiveOuts;
54 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
55 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT
57 MachineRegisterInfo(const MRegisterInfo &MRI);
58 ~MachineRegisterInfo();
60 //===--------------------------------------------------------------------===//
62 //===--------------------------------------------------------------------===//
64 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
65 /// and uses of a register within the MachineFunction that corresponds to this
66 /// MachineRegisterInfo object.
67 template<bool Uses, bool Defs>
68 class defusechain_iterator;
70 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
72 typedef defusechain_iterator<true,true> reg_iterator;
73 reg_iterator reg_begin(unsigned RegNo) const {
74 return reg_iterator(getRegUseDefListHead(RegNo));
76 static reg_iterator reg_end() { return reg_iterator(0); }
78 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
79 typedef defusechain_iterator<false,true> def_iterator;
80 def_iterator def_begin(unsigned RegNo) const {
81 return def_iterator(getRegUseDefListHead(RegNo));
83 static def_iterator def_end() { return def_iterator(0); }
85 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
86 typedef defusechain_iterator<true,false> use_iterator;
87 use_iterator use_begin(unsigned RegNo) const {
88 return use_iterator(getRegUseDefListHead(RegNo));
90 static use_iterator use_end() { return use_iterator(0); }
93 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
94 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
95 /// except that it also changes any definitions of the register as well.
96 void replaceRegWith(unsigned FromReg, unsigned ToReg);
98 /// getRegUseDefListHead - Return the head pointer for the register use/def
99 /// list for the specified virtual or physical register.
100 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
101 if (RegNo < MRegisterInfo::FirstVirtualRegister)
102 return PhysRegUseDefLists[RegNo];
103 RegNo -= MRegisterInfo::FirstVirtualRegister;
104 return VRegInfo[RegNo].second;
107 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
108 if (RegNo < MRegisterInfo::FirstVirtualRegister)
109 return PhysRegUseDefLists[RegNo];
110 RegNo -= MRegisterInfo::FirstVirtualRegister;
111 return VRegInfo[RegNo].second;
114 //===--------------------------------------------------------------------===//
115 // Virtual Register Info
116 //===--------------------------------------------------------------------===//
118 /// getRegClass - Return the register class of the specified virtual register.
119 const TargetRegisterClass *getRegClass(unsigned Reg) {
120 Reg -= MRegisterInfo::FirstVirtualRegister;
121 assert(Reg < VRegInfo.size() && "Invalid vreg!");
122 return VRegInfo[Reg].first;
125 /// createVirtualRegister - Create and return a new virtual register in the
126 /// function with the specified register class.
128 unsigned createVirtualRegister(const TargetRegisterClass *RegClass) {
129 assert(RegClass && "Cannot create register without RegClass!");
130 // Add a reg, but keep track of whether the vector reallocated or not.
131 void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
132 VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
134 if (&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)
135 return getLastVirtReg();
137 // Otherwise, the vector reallocated, handle this now.
138 HandleVRegListReallocation();
139 return getLastVirtReg();
142 /// getLastVirtReg - Return the highest currently assigned virtual register.
144 unsigned getLastVirtReg() const {
145 return VRegInfo.size()+MRegisterInfo::FirstVirtualRegister-1;
148 /// getVRegDef - Return the machine instr that defines the specified virtual
149 /// register or null if none is found. This assumes that the code is in SSA
150 /// form, so there should only be one definition.
151 MachineInstr *getVRegDef(unsigned Reg) const;
154 //===--------------------------------------------------------------------===//
155 // Physical Register Use Info
156 //===--------------------------------------------------------------------===//
158 /// isPhysRegUsed - Return true if the specified register is used in this
159 /// function. This only works after register allocation.
160 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; }
162 /// setPhysRegUsed - Mark the specified register used in this function.
163 /// This should only be called during and after register allocation.
164 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }
166 /// setPhysRegUnused - Mark the specified register unused in this function.
167 /// This should only be called during and after register allocation.
168 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }
171 //===--------------------------------------------------------------------===//
172 // LiveIn/LiveOut Management
173 //===--------------------------------------------------------------------===//
175 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it
176 /// is an error to add the same register to the same set more than once.
177 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
178 LiveIns.push_back(std::make_pair(Reg, vreg));
180 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
182 // Iteration support for live in/out sets. These sets are kept in sorted
183 // order by their register number.
184 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
186 typedef std::vector<unsigned>::const_iterator liveout_iterator;
187 livein_iterator livein_begin() const { return LiveIns.begin(); }
188 livein_iterator livein_end() const { return LiveIns.end(); }
189 bool livein_empty() const { return LiveIns.empty(); }
190 liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
191 liveout_iterator liveout_end() const { return LiveOuts.end(); }
192 bool liveout_empty() const { return LiveOuts.empty(); }
194 void HandleVRegListReallocation();
197 /// defusechain_iterator - This class provides iterator support for machine
198 /// operands in the function that use or define a specific register. If
199 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
200 /// returns defs. If neither are true then you are silly and it always
202 template<bool ReturnUses, bool ReturnDefs>
203 class defusechain_iterator
204 : public forward_iterator<MachineInstr, ptrdiff_t> {
206 defusechain_iterator(MachineOperand *op) : Op(op) {
207 // If the first node isn't one we're interested in, advance to one that
208 // we are interested in.
210 if (!ReturnUses && op->isUse() ||
211 !ReturnDefs && op->isDef())
215 friend class MachineRegisterInfo;
217 typedef forward_iterator<MachineInstr, ptrdiff_t>::reference reference;
218 typedef forward_iterator<MachineInstr, ptrdiff_t>::pointer pointer;
220 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
221 defusechain_iterator() : Op(0) {}
223 bool operator==(const defusechain_iterator &x) const {
226 bool operator!=(const defusechain_iterator &x) const {
227 return !operator==(x);
230 /// atEnd - return true if this iterator is equal to reg_end() on the value.
231 bool atEnd() const { return Op == 0; }
233 // Iterator traversal: forward iteration only
234 defusechain_iterator &operator++() { // Preincrement
235 assert(Op && "Cannot increment end iterator!");
236 Op = Op->getNextOperandForReg();
238 // If this is an operand we don't care about, skip it.
239 while (Op && (!ReturnUses && Op->isUse() ||
240 !ReturnDefs && Op->isDef()))
241 Op = Op->getNextOperandForReg();
245 defusechain_iterator operator++(int) { // Postincrement
246 defusechain_iterator tmp = *this; ++*this; return tmp;
249 MachineOperand &getOperand() const {
250 assert(Op && "Cannot dereference end iterator!");
254 /// getOperandNo - Return the operand # of this MachineOperand in its
256 unsigned getOperandNo() const {
257 assert(Op && "Cannot dereference end iterator!");
258 return Op - &Op->getParent()->getOperand(0);
261 // Retrieve a reference to the current operand.
262 MachineInstr &operator*() const {
263 assert(Op && "Cannot dereference end iterator!");
264 return *Op->getParent();
267 MachineInstr *operator->() const {
268 assert(Op && "Cannot dereference end iterator!");
269 return Op->getParent();
275 } // End llvm namespace