1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/DenseMapInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/ilist.h"
24 #include "llvm/ADT/ilist_node.h"
25 #include "llvm/ADT/iterator_range.h"
26 #include "llvm/CodeGen/MachineOperand.h"
27 #include "llvm/IR/DebugInfo.h"
28 #include "llvm/IR/DebugLoc.h"
29 #include "llvm/IR/InlineAsm.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/Support/ArrayRecycler.h"
32 #include "llvm/Target/TargetOpcodes.h"
36 template <typename T> class SmallVectorImpl;
38 class TargetInstrInfo;
39 class TargetRegisterClass;
40 class TargetRegisterInfo;
41 class MachineFunction;
42 class MachineMemOperand;
44 //===----------------------------------------------------------------------===//
45 /// Representation of each machine instruction.
47 /// This class isn't a POD type, but it must have a trivial destructor. When a
48 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
49 /// without having their destructor called.
51 class MachineInstr : public ilist_node<MachineInstr> {
53 typedef MachineMemOperand **mmo_iterator;
55 /// Flags to specify different kinds of comments to output in
56 /// assembly code. These flags carry semantic information not
57 /// otherwise easily derivable from the IR text.
65 FrameSetup = 1 << 0, // Instruction is used as a part of
66 // function frame setup code.
67 BundledPred = 1 << 1, // Instruction has bundled predecessors.
68 BundledSucc = 1 << 2 // Instruction has bundled successors.
71 const MCInstrDesc *MCID; // Instruction descriptor.
72 MachineBasicBlock *Parent; // Pointer to the owning basic block.
74 // Operands are allocated by an ArrayRecycler.
75 MachineOperand *Operands; // Pointer to the first operand.
76 unsigned NumOperands; // Number of operands on instruction.
77 typedef ArrayRecycler<MachineOperand>::Capacity OperandCapacity;
78 OperandCapacity CapOperands; // Capacity of the Operands array.
80 uint8_t Flags; // Various bits of additional
81 // information about machine
84 uint8_t AsmPrinterFlags; // Various bits of information used by
85 // the AsmPrinter to emit helpful
86 // comments. This is *not* semantic
87 // information. Do not use this for
88 // anything other than to convey comment
89 // information to AsmPrinter.
91 uint8_t NumMemRefs; // Information on memory references.
94 DebugLoc debugLoc; // Source line information.
96 MachineInstr(const MachineInstr&) = delete;
97 void operator=(const MachineInstr&) = delete;
98 // Use MachineFunction::DeleteMachineInstr() instead.
99 ~MachineInstr() = delete;
101 // Intrusive list support
102 friend struct ilist_traits<MachineInstr>;
103 friend struct ilist_traits<MachineBasicBlock>;
104 void setParent(MachineBasicBlock *P) { Parent = P; }
106 /// This constructor creates a copy of the given
107 /// MachineInstr in the given MachineFunction.
108 MachineInstr(MachineFunction &, const MachineInstr &);
110 /// This constructor create a MachineInstr and add the implicit operands.
111 /// It reserves space for number of operands specified by
112 /// MCInstrDesc. An explicit DebugLoc is supplied.
113 MachineInstr(MachineFunction &, const MCInstrDesc &MCID, DebugLoc dl,
116 // MachineInstrs are pool-allocated and owned by MachineFunction.
117 friend class MachineFunction;
120 const MachineBasicBlock* getParent() const { return Parent; }
121 MachineBasicBlock* getParent() { return Parent; }
123 /// Return the asm printer flags bitvector.
124 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
126 /// Clear the AsmPrinter bitvector.
127 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
129 /// Return whether an AsmPrinter flag is set.
130 bool getAsmPrinterFlag(CommentFlag Flag) const {
131 return AsmPrinterFlags & Flag;
134 /// Set a flag for the AsmPrinter.
135 void setAsmPrinterFlag(CommentFlag Flag) {
136 AsmPrinterFlags |= (uint8_t)Flag;
139 /// Clear specific AsmPrinter flags.
140 void clearAsmPrinterFlag(CommentFlag Flag) {
141 AsmPrinterFlags &= ~Flag;
144 /// Return the MI flags bitvector.
145 uint8_t getFlags() const {
149 /// Return whether an MI flag is set.
150 bool getFlag(MIFlag Flag) const {
155 void setFlag(MIFlag Flag) {
156 Flags |= (uint8_t)Flag;
159 void setFlags(unsigned flags) {
160 // Filter out the automatically maintained flags.
161 unsigned Mask = BundledPred | BundledSucc;
162 Flags = (Flags & Mask) | (flags & ~Mask);
165 /// clearFlag - Clear a MI flag.
166 void clearFlag(MIFlag Flag) {
167 Flags &= ~((uint8_t)Flag);
170 /// Return true if MI is in a bundle (but not the first MI in a bundle).
172 /// A bundle looks like this before it's finalized:
184 /// In this case, the first MI starts a bundle but is not inside a bundle, the
185 /// next 2 MIs are considered "inside" the bundle.
187 /// After a bundle is finalized, it looks like this:
203 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
204 /// a bundle, but the next three MIs are.
205 bool isInsideBundle() const {
206 return getFlag(BundledPred);
209 /// Return true if this instruction part of a bundle. This is true
210 /// if either itself or its following instruction is marked "InsideBundle".
211 bool isBundled() const {
212 return isBundledWithPred() || isBundledWithSucc();
215 /// Return true if this instruction is part of a bundle, and it is not the
216 /// first instruction in the bundle.
217 bool isBundledWithPred() const { return getFlag(BundledPred); }
219 /// Return true if this instruction is part of a bundle, and it is not the
220 /// last instruction in the bundle.
221 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
223 /// Bundle this instruction with its predecessor. This can be an unbundled
224 /// instruction, or it can be the first instruction in a bundle.
225 void bundleWithPred();
227 /// Bundle this instruction with its successor. This can be an unbundled
228 /// instruction, or it can be the last instruction in a bundle.
229 void bundleWithSucc();
231 /// Break bundle above this instruction.
232 void unbundleFromPred();
234 /// Break bundle below this instruction.
235 void unbundleFromSucc();
237 /// Returns the debug location id of this MachineInstr.
238 const DebugLoc &getDebugLoc() const { return debugLoc; }
240 /// Return the debug variable referenced by
241 /// this DBG_VALUE instruction.
242 const DILocalVariable *getDebugVariable() const {
243 assert(isDebugValue() && "not a DBG_VALUE");
244 return cast<DILocalVariable>(getOperand(2).getMetadata());
247 /// Return the complex address expression referenced by
248 /// this DBG_VALUE instruction.
249 const DIExpression *getDebugExpression() const {
250 assert(isDebugValue() && "not a DBG_VALUE");
251 return cast<DIExpression>(getOperand(3).getMetadata());
254 /// Emit an error referring to the source location of this instruction.
255 /// This should only be used for inline assembly that is somehow
256 /// impossible to compile. Other errors should have been handled much
259 /// If this method returns, the caller should try to recover from the error.
261 void emitError(StringRef Msg) const;
263 /// Returns the target instruction descriptor of this MachineInstr.
264 const MCInstrDesc &getDesc() const { return *MCID; }
266 /// Returns the opcode of this MachineInstr.
267 unsigned getOpcode() const { return MCID->Opcode; }
269 /// Access to explicit operands of the instruction.
271 unsigned getNumOperands() const { return NumOperands; }
273 const MachineOperand& getOperand(unsigned i) const {
274 assert(i < getNumOperands() && "getOperand() out of range!");
277 MachineOperand& getOperand(unsigned i) {
278 assert(i < getNumOperands() && "getOperand() out of range!");
282 /// Returns the number of non-implicit operands.
283 unsigned getNumExplicitOperands() const;
285 /// iterator/begin/end - Iterate over all operands of a machine instruction.
286 typedef MachineOperand *mop_iterator;
287 typedef const MachineOperand *const_mop_iterator;
289 mop_iterator operands_begin() { return Operands; }
290 mop_iterator operands_end() { return Operands + NumOperands; }
292 const_mop_iterator operands_begin() const { return Operands; }
293 const_mop_iterator operands_end() const { return Operands + NumOperands; }
295 iterator_range<mop_iterator> operands() {
296 return iterator_range<mop_iterator>(operands_begin(), operands_end());
298 iterator_range<const_mop_iterator> operands() const {
299 return iterator_range<const_mop_iterator>(operands_begin(), operands_end());
301 iterator_range<mop_iterator> explicit_operands() {
302 return iterator_range<mop_iterator>(
303 operands_begin(), operands_begin() + getNumExplicitOperands());
305 iterator_range<const_mop_iterator> explicit_operands() const {
306 return iterator_range<const_mop_iterator>(
307 operands_begin(), operands_begin() + getNumExplicitOperands());
309 iterator_range<mop_iterator> implicit_operands() {
310 return iterator_range<mop_iterator>(explicit_operands().end(),
313 iterator_range<const_mop_iterator> implicit_operands() const {
314 return iterator_range<const_mop_iterator>(explicit_operands().end(),
317 iterator_range<mop_iterator> defs() {
318 return iterator_range<mop_iterator>(
319 operands_begin(), operands_begin() + getDesc().getNumDefs());
321 iterator_range<const_mop_iterator> defs() const {
322 return iterator_range<const_mop_iterator>(
323 operands_begin(), operands_begin() + getDesc().getNumDefs());
325 iterator_range<mop_iterator> uses() {
326 return iterator_range<mop_iterator>(
327 operands_begin() + getDesc().getNumDefs(), operands_end());
329 iterator_range<const_mop_iterator> uses() const {
330 return iterator_range<const_mop_iterator>(
331 operands_begin() + getDesc().getNumDefs(), operands_end());
334 /// Returns the number of the operand iterator \p I points to.
335 unsigned getOperandNo(const_mop_iterator I) const {
336 return I - operands_begin();
339 /// Access to memory operands of the instruction
340 mmo_iterator memoperands_begin() const { return MemRefs; }
341 mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
342 bool memoperands_empty() const { return NumMemRefs == 0; }
344 iterator_range<mmo_iterator> memoperands() {
345 return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end());
347 iterator_range<mmo_iterator> memoperands() const {
348 return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end());
351 /// Return true if this instruction has exactly one MachineMemOperand.
352 bool hasOneMemOperand() const {
353 return NumMemRefs == 1;
356 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
357 /// queries but they are bundle aware.
360 IgnoreBundle, // Ignore bundles
361 AnyInBundle, // Return true if any instruction in bundle has property
362 AllInBundle // Return true if all instructions in bundle have property
365 /// Return true if the instruction (or in the case of a bundle,
366 /// the instructions inside the bundle) has the specified property.
367 /// The first argument is the property being queried.
368 /// The second argument indicates whether the query should look inside
369 /// instruction bundles.
370 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
371 // Inline the fast path for unbundled or bundle-internal instructions.
372 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
373 return getDesc().getFlags() & (1 << MCFlag);
375 // If this is the first instruction in a bundle, take the slow path.
376 return hasPropertyInBundle(1 << MCFlag, Type);
379 /// Return true if this instruction can have a variable number of operands.
380 /// In this case, the variable operands will be after the normal
381 /// operands but before the implicit definitions and uses (if any are
383 bool isVariadic(QueryType Type = IgnoreBundle) const {
384 return hasProperty(MCID::Variadic, Type);
387 /// Set if this instruction has an optional definition, e.g.
388 /// ARM instructions which can set condition code if 's' bit is set.
389 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
390 return hasProperty(MCID::HasOptionalDef, Type);
393 /// Return true if this is a pseudo instruction that doesn't
394 /// correspond to a real machine instruction.
395 bool isPseudo(QueryType Type = IgnoreBundle) const {
396 return hasProperty(MCID::Pseudo, Type);
399 bool isReturn(QueryType Type = AnyInBundle) const {
400 return hasProperty(MCID::Return, Type);
403 bool isCall(QueryType Type = AnyInBundle) const {
404 return hasProperty(MCID::Call, Type);
407 /// Returns true if the specified instruction stops control flow
408 /// from executing the instruction immediately following it. Examples include
409 /// unconditional branches and return instructions.
410 bool isBarrier(QueryType Type = AnyInBundle) const {
411 return hasProperty(MCID::Barrier, Type);
414 /// Returns true if this instruction part of the terminator for a basic block.
415 /// Typically this is things like return and branch instructions.
417 /// Various passes use this to insert code into the bottom of a basic block,
418 /// but before control flow occurs.
419 bool isTerminator(QueryType Type = AnyInBundle) const {
420 return hasProperty(MCID::Terminator, Type);
423 /// Returns true if this is a conditional, unconditional, or indirect branch.
424 /// Predicates below can be used to discriminate between
425 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
426 /// get more information.
427 bool isBranch(QueryType Type = AnyInBundle) const {
428 return hasProperty(MCID::Branch, Type);
431 /// Return true if this is an indirect branch, such as a
432 /// branch through a register.
433 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
434 return hasProperty(MCID::IndirectBranch, Type);
437 /// Return true if this is a branch which may fall
438 /// through to the next instruction or may transfer control flow to some other
439 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
440 /// information about this branch.
441 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
442 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
445 /// Return true if this is a branch which always
446 /// transfers control flow to some other block. The
447 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
448 /// about this branch.
449 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
450 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
453 /// Return true if this instruction has a predicate operand that
454 /// controls execution. It may be set to 'always', or may be set to other
455 /// values. There are various methods in TargetInstrInfo that can be used to
456 /// control and modify the predicate in this instruction.
457 bool isPredicable(QueryType Type = AllInBundle) const {
458 // If it's a bundle than all bundled instructions must be predicable for this
460 return hasProperty(MCID::Predicable, Type);
463 /// Return true if this instruction is a comparison.
464 bool isCompare(QueryType Type = IgnoreBundle) const {
465 return hasProperty(MCID::Compare, Type);
468 /// Return true if this instruction is a move immediate
469 /// (including conditional moves) instruction.
470 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
471 return hasProperty(MCID::MoveImm, Type);
474 /// Return true if this instruction is a bitcast instruction.
475 bool isBitcast(QueryType Type = IgnoreBundle) const {
476 return hasProperty(MCID::Bitcast, Type);
479 /// Return true if this instruction is a select instruction.
480 bool isSelect(QueryType Type = IgnoreBundle) const {
481 return hasProperty(MCID::Select, Type);
484 /// Return true if this instruction cannot be safely duplicated.
485 /// For example, if the instruction has a unique labels attached
486 /// to it, duplicating it would cause multiple definition errors.
487 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
488 return hasProperty(MCID::NotDuplicable, Type);
491 /// Return true if this instruction is convergent.
492 /// Convergent instructions can only be moved to locations that are
493 /// control-equivalent to their initial position.
494 bool isConvergent(QueryType Type = AnyInBundle) const {
495 return hasProperty(MCID::Convergent, Type);
498 /// Returns true if the specified instruction has a delay slot
499 /// which must be filled by the code generator.
500 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
501 return hasProperty(MCID::DelaySlot, Type);
504 /// Return true for instructions that can be folded as
505 /// memory operands in other instructions. The most common use for this
506 /// is instructions that are simple loads from memory that don't modify
507 /// the loaded value in any way, but it can also be used for instructions
508 /// that can be expressed as constant-pool loads, such as V_SETALLONES
509 /// on x86, to allow them to be folded when it is beneficial.
510 /// This should only be set on instructions that return a value in their
511 /// only virtual register definition.
512 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
513 return hasProperty(MCID::FoldableAsLoad, Type);
516 /// \brief Return true if this instruction behaves
517 /// the same way as the generic REG_SEQUENCE instructions.
519 /// dX VMOVDRR rY, rZ
521 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
523 /// Note that for the optimizers to be able to take advantage of
524 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
525 /// override accordingly.
526 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
527 return hasProperty(MCID::RegSequence, Type);
530 /// \brief Return true if this instruction behaves
531 /// the same way as the generic EXTRACT_SUBREG instructions.
533 /// rX, rY VMOVRRD dZ
534 /// is equivalent to two EXTRACT_SUBREG:
535 /// rX = EXTRACT_SUBREG dZ, ssub_0
536 /// rY = EXTRACT_SUBREG dZ, ssub_1
538 /// Note that for the optimizers to be able to take advantage of
539 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
540 /// override accordingly.
541 bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
542 return hasProperty(MCID::ExtractSubreg, Type);
545 /// \brief Return true if this instruction behaves
546 /// the same way as the generic INSERT_SUBREG instructions.
548 /// dX = VSETLNi32 dY, rZ, Imm
549 /// is equivalent to a INSERT_SUBREG:
550 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
552 /// Note that for the optimizers to be able to take advantage of
553 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
554 /// override accordingly.
555 bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
556 return hasProperty(MCID::InsertSubreg, Type);
559 //===--------------------------------------------------------------------===//
560 // Side Effect Analysis
561 //===--------------------------------------------------------------------===//
563 /// Return true if this instruction could possibly read memory.
564 /// Instructions with this flag set are not necessarily simple load
565 /// instructions, they may load a value and modify it, for example.
566 bool mayLoad(QueryType Type = AnyInBundle) const {
568 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
569 if (ExtraInfo & InlineAsm::Extra_MayLoad)
572 return hasProperty(MCID::MayLoad, Type);
575 /// Return true if this instruction could possibly modify memory.
576 /// Instructions with this flag set are not necessarily simple store
577 /// instructions, they may store a modified value based on their operands, or
578 /// may not actually modify anything, for example.
579 bool mayStore(QueryType Type = AnyInBundle) const {
581 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
582 if (ExtraInfo & InlineAsm::Extra_MayStore)
585 return hasProperty(MCID::MayStore, Type);
588 /// Return true if this instruction could possibly read or modify memory.
589 bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
590 return mayLoad(Type) || mayStore(Type);
593 //===--------------------------------------------------------------------===//
594 // Flags that indicate whether an instruction can be modified by a method.
595 //===--------------------------------------------------------------------===//
597 /// Return true if this may be a 2- or 3-address
598 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
599 /// result if Y and Z are exchanged. If this flag is set, then the
600 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
603 /// Note that this flag may be set on instructions that are only commutable
604 /// sometimes. In these cases, the call to commuteInstruction will fail.
605 /// Also note that some instructions require non-trivial modification to
607 bool isCommutable(QueryType Type = IgnoreBundle) const {
608 return hasProperty(MCID::Commutable, Type);
611 /// Return true if this is a 2-address instruction
612 /// which can be changed into a 3-address instruction if needed. Doing this
613 /// transformation can be profitable in the register allocator, because it
614 /// means that the instruction can use a 2-address form if possible, but
615 /// degrade into a less efficient form if the source and dest register cannot
616 /// be assigned to the same register. For example, this allows the x86
617 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
618 /// is the same speed as the shift but has bigger code size.
620 /// If this returns true, then the target must implement the
621 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
622 /// is allowed to fail if the transformation isn't valid for this specific
623 /// instruction (e.g. shl reg, 4 on x86).
625 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
626 return hasProperty(MCID::ConvertibleTo3Addr, Type);
629 /// Return true if this instruction requires
630 /// custom insertion support when the DAG scheduler is inserting it into a
631 /// machine basic block. If this is true for the instruction, it basically
632 /// means that it is a pseudo instruction used at SelectionDAG time that is
633 /// expanded out into magic code by the target when MachineInstrs are formed.
635 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
636 /// is used to insert this into the MachineBasicBlock.
637 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
638 return hasProperty(MCID::UsesCustomInserter, Type);
641 /// Return true if this instruction requires *adjustment*
642 /// after instruction selection by calling a target hook. For example, this
643 /// can be used to fill in ARM 's' optional operand depending on whether
644 /// the conditional flag register is used.
645 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
646 return hasProperty(MCID::HasPostISelHook, Type);
649 /// Returns true if this instruction is a candidate for remat.
650 /// This flag is deprecated, please don't use it anymore. If this
651 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
652 /// verify the instruction is really rematable.
653 bool isRematerializable(QueryType Type = AllInBundle) const {
654 // It's only possible to re-mat a bundle if all bundled instructions are
655 // re-materializable.
656 return hasProperty(MCID::Rematerializable, Type);
659 /// Returns true if this instruction has the same cost (or less) than a move
660 /// instruction. This is useful during certain types of optimizations
661 /// (e.g., remat during two-address conversion or machine licm)
662 /// where we would like to remat or hoist the instruction, but not if it costs
663 /// more than moving the instruction into the appropriate register. Note, we
664 /// are not marking copies from and to the same register class with this flag.
665 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
666 // Only returns true for a bundle if all bundled instructions are cheap.
667 return hasProperty(MCID::CheapAsAMove, Type);
670 /// Returns true if this instruction source operands
671 /// have special register allocation requirements that are not captured by the
672 /// operand register classes. e.g. ARM::STRD's two source registers must be an
673 /// even / odd pair, ARM::STM registers have to be in ascending order.
674 /// Post-register allocation passes should not attempt to change allocations
675 /// for sources of instructions with this flag.
676 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
677 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
680 /// Returns true if this instruction def operands
681 /// have special register allocation requirements that are not captured by the
682 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
683 /// even / odd pair, ARM::LDM registers have to be in ascending order.
684 /// Post-register allocation passes should not attempt to change allocations
685 /// for definitions of instructions with this flag.
686 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
687 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
692 CheckDefs, // Check all operands for equality
693 CheckKillDead, // Check all operands including kill / dead markers
694 IgnoreDefs, // Ignore all definitions
695 IgnoreVRegDefs // Ignore virtual register definitions
698 /// Return true if this instruction is identical to (same
699 /// opcode and same operands as) the specified instruction.
700 bool isIdenticalTo(const MachineInstr *Other,
701 MICheckType Check = CheckDefs) const;
703 /// Unlink 'this' from the containing basic block, and return it without
706 /// This function can not be used on bundled instructions, use
707 /// removeFromBundle() to remove individual instructions from a bundle.
708 MachineInstr *removeFromParent();
710 /// Unlink this instruction from its basic block and return it without
713 /// If the instruction is part of a bundle, the other instructions in the
714 /// bundle remain bundled.
715 MachineInstr *removeFromBundle();
717 /// Unlink 'this' from the containing basic block and delete it.
719 /// If this instruction is the header of a bundle, the whole bundle is erased.
720 /// This function can not be used for instructions inside a bundle, use
721 /// eraseFromBundle() to erase individual bundled instructions.
722 void eraseFromParent();
724 /// Unlink 'this' from the containing basic block and delete it.
726 /// For all definitions mark their uses in DBG_VALUE nodes
727 /// as undefined. Otherwise like eraseFromParent().
728 void eraseFromParentAndMarkDBGValuesForRemoval();
730 /// Unlink 'this' form its basic block and delete it.
732 /// If the instruction is part of a bundle, the other instructions in the
733 /// bundle remain bundled.
734 void eraseFromBundle();
736 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
737 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
739 /// Returns true if the MachineInstr represents a label.
740 bool isLabel() const { return isEHLabel() || isGCLabel(); }
741 bool isCFIInstruction() const {
742 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
745 // True if the instruction represents a position in the function.
746 bool isPosition() const { return isLabel() || isCFIInstruction(); }
748 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
749 /// A DBG_VALUE is indirect iff the first operand is a register and
750 /// the second operand is an immediate.
751 bool isIndirectDebugValue() const {
752 return isDebugValue()
753 && getOperand(0).isReg()
754 && getOperand(1).isImm();
757 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
758 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
759 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
760 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
761 bool isMSInlineAsm() const {
762 return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
764 bool isStackAligningInlineAsm() const;
765 InlineAsm::AsmDialect getInlineAsmDialect() const;
766 bool isInsertSubreg() const {
767 return getOpcode() == TargetOpcode::INSERT_SUBREG;
769 bool isSubregToReg() const {
770 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
772 bool isRegSequence() const {
773 return getOpcode() == TargetOpcode::REG_SEQUENCE;
775 bool isBundle() const {
776 return getOpcode() == TargetOpcode::BUNDLE;
778 bool isCopy() const {
779 return getOpcode() == TargetOpcode::COPY;
781 bool isFullCopy() const {
782 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
784 bool isExtractSubreg() const {
785 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
788 /// Return true if the instruction behaves like a copy.
789 /// This does not include native copy instructions.
790 bool isCopyLike() const {
791 return isCopy() || isSubregToReg();
794 /// Return true is the instruction is an identity copy.
795 bool isIdentityCopy() const {
796 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
797 getOperand(0).getSubReg() == getOperand(1).getSubReg();
800 /// Return true if this is a transient instruction that is
801 /// either very likely to be eliminated during register allocation (such as
802 /// copy-like instructions), or if this instruction doesn't have an
803 /// execution-time cost.
804 bool isTransient() const {
805 switch(getOpcode()) {
806 default: return false;
807 // Copy-like instructions are usually eliminated during register allocation.
808 case TargetOpcode::PHI:
809 case TargetOpcode::COPY:
810 case TargetOpcode::INSERT_SUBREG:
811 case TargetOpcode::SUBREG_TO_REG:
812 case TargetOpcode::REG_SEQUENCE:
813 // Pseudo-instructions that don't produce any real output.
814 case TargetOpcode::IMPLICIT_DEF:
815 case TargetOpcode::KILL:
816 case TargetOpcode::CFI_INSTRUCTION:
817 case TargetOpcode::EH_LABEL:
818 case TargetOpcode::GC_LABEL:
819 case TargetOpcode::DBG_VALUE:
824 /// Return the number of instructions inside the MI bundle, excluding the
827 /// This is the number of instructions that MachineBasicBlock::iterator
828 /// skips, 0 for unbundled instructions.
829 unsigned getBundleSize() const;
831 /// Return true if the MachineInstr reads the specified register.
832 /// If TargetRegisterInfo is passed, then it also checks if there
833 /// is a read of a super-register.
834 /// This does not count partial redefines of virtual registers as reads:
836 bool readsRegister(unsigned Reg,
837 const TargetRegisterInfo *TRI = nullptr) const {
838 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
841 /// Return true if the MachineInstr reads the specified virtual register.
842 /// Take into account that a partial define is a
843 /// read-modify-write operation.
844 bool readsVirtualRegister(unsigned Reg) const {
845 return readsWritesVirtualRegister(Reg).first;
848 /// Return a pair of bools (reads, writes) indicating if this instruction
849 /// reads or writes Reg. This also considers partial defines.
850 /// If Ops is not null, all operand indices for Reg are added.
851 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
852 SmallVectorImpl<unsigned> *Ops = nullptr) const;
854 /// Return true if the MachineInstr kills the specified register.
855 /// If TargetRegisterInfo is passed, then it also checks if there is
856 /// a kill of a super-register.
857 bool killsRegister(unsigned Reg,
858 const TargetRegisterInfo *TRI = nullptr) const {
859 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
862 /// Return true if the MachineInstr fully defines the specified register.
863 /// If TargetRegisterInfo is passed, then it also checks
864 /// if there is a def of a super-register.
865 /// NOTE: It's ignoring subreg indices on virtual registers.
866 bool definesRegister(unsigned Reg,
867 const TargetRegisterInfo *TRI = nullptr) const {
868 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
871 /// Return true if the MachineInstr modifies (fully define or partially
872 /// define) the specified register.
873 /// NOTE: It's ignoring subreg indices on virtual registers.
874 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
875 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
878 /// Returns true if the register is dead in this machine instruction.
879 /// If TargetRegisterInfo is passed, then it also checks
880 /// if there is a dead def of a super-register.
881 bool registerDefIsDead(unsigned Reg,
882 const TargetRegisterInfo *TRI = nullptr) const {
883 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
886 /// Returns the operand index that is a use of the specific register or -1
887 /// if it is not found. It further tightens the search criteria to a use
888 /// that kills the register if isKill is true.
889 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
890 const TargetRegisterInfo *TRI = nullptr) const;
892 /// Wrapper for findRegisterUseOperandIdx, it returns
893 /// a pointer to the MachineOperand rather than an index.
894 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
895 const TargetRegisterInfo *TRI = nullptr) {
896 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
897 return (Idx == -1) ? nullptr : &getOperand(Idx);
900 /// Returns the operand index that is a def of the specified register or
901 /// -1 if it is not found. If isDead is true, defs that are not dead are
902 /// skipped. If Overlap is true, then it also looks for defs that merely
903 /// overlap the specified register. If TargetRegisterInfo is non-null,
904 /// then it also checks if there is a def of a super-register.
905 /// This may also return a register mask operand when Overlap is true.
906 int findRegisterDefOperandIdx(unsigned Reg,
907 bool isDead = false, bool Overlap = false,
908 const TargetRegisterInfo *TRI = nullptr) const;
910 /// Wrapper for findRegisterDefOperandIdx, it returns
911 /// a pointer to the MachineOperand rather than an index.
912 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
913 const TargetRegisterInfo *TRI = nullptr) {
914 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
915 return (Idx == -1) ? nullptr : &getOperand(Idx);
918 /// Find the index of the first operand in the
919 /// operand list that is used to represent the predicate. It returns -1 if
921 int findFirstPredOperandIdx() const;
923 /// Find the index of the flag word operand that
924 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
925 /// getOperand(OpIdx) does not belong to an inline asm operand group.
927 /// If GroupNo is not NULL, it will receive the number of the operand group
928 /// containing OpIdx.
930 /// The flag operand is an immediate that can be decoded with methods like
931 /// InlineAsm::hasRegClassConstraint().
933 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
935 /// Compute the static register class constraint for operand OpIdx.
936 /// For normal instructions, this is derived from the MCInstrDesc.
937 /// For inline assembly it is derived from the flag words.
939 /// Returns NULL if the static register class constraint cannot be
942 const TargetRegisterClass*
943 getRegClassConstraint(unsigned OpIdx,
944 const TargetInstrInfo *TII,
945 const TargetRegisterInfo *TRI) const;
947 /// \brief Applies the constraints (def/use) implied by this MI on \p Reg to
948 /// the given \p CurRC.
949 /// If \p ExploreBundle is set and MI is part of a bundle, all the
950 /// instructions inside the bundle will be taken into account. In other words,
951 /// this method accumulates all the constraints of the operand of this MI and
952 /// the related bundle if MI is a bundle or inside a bundle.
954 /// Returns the register class that satisfies both \p CurRC and the
955 /// constraints set by MI. Returns NULL if such a register class does not
958 /// \pre CurRC must not be NULL.
959 const TargetRegisterClass *getRegClassConstraintEffectForVReg(
960 unsigned Reg, const TargetRegisterClass *CurRC,
961 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
962 bool ExploreBundle = false) const;
964 /// \brief Applies the constraints (def/use) implied by the \p OpIdx operand
965 /// to the given \p CurRC.
967 /// Returns the register class that satisfies both \p CurRC and the
968 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
971 /// \pre CurRC must not be NULL.
972 /// \pre The operand at \p OpIdx must be a register.
973 const TargetRegisterClass *
974 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
975 const TargetInstrInfo *TII,
976 const TargetRegisterInfo *TRI) const;
978 /// Add a tie between the register operands at DefIdx and UseIdx.
979 /// The tie will cause the register allocator to ensure that the two
980 /// operands are assigned the same physical register.
982 /// Tied operands are managed automatically for explicit operands in the
983 /// MCInstrDesc. This method is for exceptional cases like inline asm.
984 void tieOperands(unsigned DefIdx, unsigned UseIdx);
986 /// Given the index of a tied register operand, find the
987 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
988 /// index of the tied operand which must exist.
989 unsigned findTiedOperandIdx(unsigned OpIdx) const;
991 /// Given the index of a register def operand,
992 /// check if the register def is tied to a source operand, due to either
993 /// two-address elimination or inline assembly constraints. Returns the
994 /// first tied use operand index by reference if UseOpIdx is not null.
995 bool isRegTiedToUseOperand(unsigned DefOpIdx,
996 unsigned *UseOpIdx = nullptr) const {
997 const MachineOperand &MO = getOperand(DefOpIdx);
998 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1001 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1005 /// Return true if the use operand of the specified index is tied to a def
1006 /// operand. It also returns the def operand index by reference if DefOpIdx
1008 bool isRegTiedToDefOperand(unsigned UseOpIdx,
1009 unsigned *DefOpIdx = nullptr) const {
1010 const MachineOperand &MO = getOperand(UseOpIdx);
1011 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1014 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1018 /// Clears kill flags on all operands.
1019 void clearKillInfo();
1021 /// Replace all occurrences of FromReg with ToReg:SubIdx,
1022 /// properly composing subreg indices where necessary.
1023 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
1024 const TargetRegisterInfo &RegInfo);
1026 /// We have determined MI kills a register. Look for the
1027 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1028 /// add a implicit operand if it's not found. Returns true if the operand
1029 /// exists / is added.
1030 bool addRegisterKilled(unsigned IncomingReg,
1031 const TargetRegisterInfo *RegInfo,
1032 bool AddIfNotFound = false);
1034 /// Clear all kill flags affecting Reg. If RegInfo is
1035 /// provided, this includes super-register kills.
1036 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
1038 /// We have determined MI defined a register without a use.
1039 /// Look for the operand that defines it and mark it as IsDead. If
1040 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1041 /// true if the operand exists / is added.
1042 bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
1043 bool AddIfNotFound = false);
1045 /// Clear all dead flags on operands defining register @p Reg.
1046 void clearRegisterDeads(unsigned Reg);
1048 /// Mark all subregister defs of register @p Reg with the undef flag.
1049 /// This function is used when we determined to have a subregister def in an
1050 /// otherwise undefined super register.
1051 void addRegisterDefReadUndef(unsigned Reg);
1053 /// We have determined MI defines a register. Make sure there is an operand
1055 void addRegisterDefined(unsigned Reg,
1056 const TargetRegisterInfo *RegInfo = nullptr);
1058 /// Mark every physreg used by this instruction as
1059 /// dead except those in the UsedRegs list.
1061 /// On instructions with register mask operands, also add implicit-def
1062 /// operands for all registers in UsedRegs.
1063 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1064 const TargetRegisterInfo &TRI);
1066 /// Return true if it is safe to move this instruction. If
1067 /// SawStore is set to true, it means that there is a store (or call) between
1068 /// the instruction's location and its intended destination.
1069 bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const;
1071 /// Return true if this instruction may have an ordered
1072 /// or volatile memory reference, or if the information describing the memory
1073 /// reference is not available. Return false if it is known to have no
1074 /// ordered or volatile memory references.
1075 bool hasOrderedMemoryRef() const;
1077 /// Return true if this instruction is loading from a
1078 /// location whose value is invariant across the function. For example,
1079 /// loading a value from the constant pool or from the argument area of
1080 /// a function if it does not change. This should only return true of *all*
1081 /// loads the instruction does are invariant (if it does multiple loads).
1082 bool isInvariantLoad(AliasAnalysis *AA) const;
1084 /// If the specified instruction is a PHI that always merges together the
1085 /// same virtual register, return the register, otherwise return 0.
1086 unsigned isConstantValuePHI() const;
1088 /// Return true if this instruction has side effects that are not modeled
1089 /// by mayLoad / mayStore, etc.
1090 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1091 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1092 /// INLINEASM instruction, in which case the side effect property is encoded
1093 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1095 bool hasUnmodeledSideEffects() const;
1097 /// Return true if all the defs of this instruction are dead.
1098 bool allDefsAreDead() const;
1100 /// Copy implicit register operands from specified
1101 /// instruction to this instruction.
1102 void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI);
1105 // Debugging support
1107 void print(raw_ostream &OS, bool SkipOpers = false) const;
1108 void print(raw_ostream &OS, ModuleSlotTracker &MST,
1109 bool SkipOpers = false) const;
1112 //===--------------------------------------------------------------------===//
1113 // Accessors used to build up machine instructions.
1115 /// Add the specified operand to the instruction. If it is an implicit
1116 /// operand, it is added to the end of the operand list. If it is an
1117 /// explicit operand it is added at the end of the explicit operand list
1118 /// (before the first implicit operand).
1120 /// MF must be the machine function that was used to allocate this
1123 /// MachineInstrBuilder provides a more convenient interface for creating
1124 /// instructions and adding operands.
1125 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1127 /// Add an operand without providing an MF reference. This only works for
1128 /// instructions that are inserted in a basic block.
1130 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1132 void addOperand(const MachineOperand &Op);
1134 /// Replace the instruction descriptor (thus opcode) of
1135 /// the current instruction with a new one.
1136 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1138 /// Replace current source information with new such.
1139 /// Avoid using this, the constructor argument is preferable.
1140 void setDebugLoc(DebugLoc dl) {
1141 debugLoc = std::move(dl);
1142 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
1145 /// Erase an operand from an instruction, leaving it with one
1146 /// fewer operand than it started with.
1147 void RemoveOperand(unsigned i);
1149 /// Add a MachineMemOperand to the machine instruction.
1150 /// This function should be used only occasionally. The setMemRefs function
1151 /// is the primary method for setting up a MachineInstr's MemRefs list.
1152 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1154 /// Assign this MachineInstr's memory reference descriptor list.
1155 /// This does not transfer ownership.
1156 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
1157 MemRefs = NewMemRefs;
1158 NumMemRefs = uint8_t(NewMemRefsEnd - NewMemRefs);
1159 assert(NumMemRefs == NewMemRefsEnd - NewMemRefs && "Too many memrefs");
1162 /// Clear this MachineInstr's memory reference descriptor list.
1163 void clearMemRefs() {
1168 /// Break any tie involving OpIdx.
1169 void untieRegOperand(unsigned OpIdx) {
1170 MachineOperand &MO = getOperand(OpIdx);
1171 if (MO.isReg() && MO.isTied()) {
1172 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1179 /// If this instruction is embedded into a MachineFunction, return the
1180 /// MachineRegisterInfo object for the current function, otherwise
1182 MachineRegisterInfo *getRegInfo();
1184 /// Add all implicit def and use operands to this instruction.
1185 void addImplicitDefUseOperands(MachineFunction &MF);
1187 /// Unlink all of the register operands in this instruction from their
1188 /// respective use lists. This requires that the operands already be on their
1190 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1192 /// Add all of the register operands in this instruction from their
1193 /// respective use lists. This requires that the operands not be on their
1195 void AddRegOperandsToUseLists(MachineRegisterInfo&);
1197 /// Slow path for hasProperty when we're dealing with a bundle.
1198 bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
1200 /// \brief Implements the logic of getRegClassConstraintEffectForVReg for the
1201 /// this MI and the given operand index \p OpIdx.
1202 /// If the related operand does not constrained Reg, this returns CurRC.
1203 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1204 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1205 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1208 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1209 /// instruction rather than by pointer value.
1210 /// The hashing and equality testing functions ignore definitions so this is
1211 /// useful for CSE, etc.
1212 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1213 static inline MachineInstr *getEmptyKey() {
1217 static inline MachineInstr *getTombstoneKey() {
1218 return reinterpret_cast<MachineInstr*>(-1);
1221 static unsigned getHashValue(const MachineInstr* const &MI);
1223 static bool isEqual(const MachineInstr* const &LHS,
1224 const MachineInstr* const &RHS) {
1225 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1226 LHS == getEmptyKey() || LHS == getTombstoneKey())
1228 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
1232 //===----------------------------------------------------------------------===//
1233 // Debugging Support
1235 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1240 } // End llvm namespace