1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Target/MachineInstrInfo.h"
13 #include "llvm/Annotation.h"
14 #include <Support/iterator>
17 //---------------------------------------------------------------------------
18 // class MachineOperand
21 // Representation of each machine instruction operand.
22 // This class is designed so that you can allocate a vector of operands
23 // first and initialize each one later.
25 // E.g, for this VM instruction:
26 // ptr = alloca type, numElements
27 // we generate 2 machine instructions on the SPARC:
29 // mul Constant, Numelements -> Reg
30 // add %sp, Reg -> Ptr
32 // Each instruction has 3 operands, listed above. Of those:
33 // - Reg, NumElements, and Ptr are of operand type MO_Register.
34 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
36 // For the register operands, the virtual register type is as follows:
38 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
39 // MachineInstr* minstr will point to the instruction that computes reg.
41 // - %sp will be of virtual register type MO_MachineReg.
42 // The field regNum identifies the machine register.
44 // - NumElements will be of virtual register type MO_VirtualReg.
45 // The field Value* value identifies the value.
47 // - Ptr will also be of virtual register type MO_VirtualReg.
48 // Again, the field Value* value identifies the value.
50 //---------------------------------------------------------------------------
53 class MachineOperand {
55 enum MachineOperandType {
56 MO_VirtualRegister, // virtual register for *value
57 MO_MachineRegister, // pre-assigned machine register `regNum'
65 // Bit fields of the flags variable used for different operand properties
66 static const char DEFFLAG = 0x1; // this is a def of the operand
67 static const char DEFUSEFLAG = 0x2; // this is both a def and a use
68 static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
69 static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
70 static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
71 static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
75 Value* value; // BasicBlockVal for a label operand.
76 // ConstantVal for a non-address immediate.
77 // Virtual register for an SSA operand,
78 // including hidden operands required for
79 // the generated machine code.
80 int64_t immedVal; // constant value for an explicit constant
83 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
84 char flags; // see bit field definitions above
85 int regNum; // register number for an explicit register
86 // will be set for a value after reg allocation
88 /*ctor*/ MachineOperand ();
89 /*ctor*/ MachineOperand (MachineOperandType operandType,
91 /*copy ctor*/ MachineOperand (const MachineOperand&);
92 /*dtor*/ ~MachineOperand () {}
94 // Accessor methods. Caller is responsible for checking the
95 // operand type before invoking the corresponding accessor.
97 inline MachineOperandType getOperandType() const {
100 inline Value* getVRegValue () const {
101 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
102 opType == MO_PCRelativeDisp);
105 inline Value* getVRegValueOrNull() const {
106 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
107 opType == MO_PCRelativeDisp)? value : NULL;
109 inline int getMachineRegNum() const {
110 assert(opType == MO_MachineRegister);
113 inline int64_t getImmedValue () const {
114 assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
117 inline bool opIsDef () const {
118 return flags & DEFFLAG;
120 inline bool opIsDefAndUse () const {
121 return flags & DEFUSEFLAG;
123 inline bool opHiBits32 () const {
124 return flags & HIFLAG32;
126 inline bool opLoBits32 () const {
127 return flags & LOFLAG32;
129 inline bool opHiBits64 () const {
130 return flags & HIFLAG64;
132 inline bool opLoBits64 () const {
133 return flags & LOFLAG64;
136 // used to check if a machine register has been allocated to this operand
137 inline bool hasAllocatedReg() const {
138 return (regNum >= 0 &&
139 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
140 opType == MO_MachineRegister));
143 // used to get the reg number if when one is allocated
144 inline int getAllocatedRegNum() const {
145 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
146 opType == MO_MachineRegister);
152 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
155 // These functions are provided so that a vector of operands can be
156 // statically allocated and individual ones can be initialized later.
157 // Give class MachineInstr access to these functions.
159 void Initialize (MachineOperandType operandType,
161 void InitializeConst (MachineOperandType operandType,
163 void InitializeReg (int regNum,
166 // Construction methods needed for fine-grain control.
167 // These must be accessed via coresponding methods in MachineInstr.
168 void markDef() { flags |= DEFFLAG; }
169 void markDefAndUse() { flags |= DEFUSEFLAG; }
170 void markHi32() { flags |= HIFLAG32; }
171 void markLo32() { flags |= LOFLAG32; }
172 void markHi64() { flags |= HIFLAG64; }
173 void markLo64() { flags |= LOFLAG64; }
175 // Replaces the Value with its corresponding physical register after
176 // register allocation is complete
177 void setRegForValue(int reg) {
178 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
179 opType == MO_MachineRegister);
183 friend class MachineInstr;
188 MachineOperand::MachineOperand()
189 : immedVal(0), opType(MO_VirtualRegister), flags(0), regNum(-1)
193 MachineOperand::MachineOperand(MachineOperandType operandType,
195 : immedVal(0), opType(operandType), flags(0), regNum(-1)
199 MachineOperand::MachineOperand(const MachineOperand& mo)
200 : opType(mo.opType), flags(mo.flags)
203 case MO_VirtualRegister:
204 case MO_CCRegister: value = mo.value; break;
205 case MO_MachineRegister: regNum = mo.regNum; break;
206 case MO_SignExtendedImmed:
207 case MO_UnextendedImmed:
208 case MO_PCRelativeDisp: immedVal = mo.immedVal; break;
214 MachineOperand::Initialize(MachineOperandType operandType,
217 opType = operandType;
224 MachineOperand::InitializeConst(MachineOperandType operandType,
227 opType = operandType;
235 MachineOperand::InitializeReg(int _regNum, bool isCCReg)
237 opType = isCCReg? MO_CCRegister : MO_MachineRegister;
239 regNum = (int) _regNum;
244 //---------------------------------------------------------------------------
245 // class MachineInstr
248 // Representation of each machine instruction.
250 // MachineOpCode must be an enum, defined separately for each target.
251 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
253 // opCodeMask is used to record variants of an instruction.
254 // E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
255 // ANNUL: if 1: Annul delay slot instruction.
256 // PREDICT-NOT-TAKEN: if 1: predict branch not taken.
257 // Instead of creating 4 different opcodes for BNZ, we create a single
258 // opcode and set bits in opCodeMask for each of these flags.
260 // There are 2 kinds of operands:
262 // (1) Explicit operands of the machine instruction in vector operands[]
264 // (2) "Implicit operands" are values implicitly used or defined by the
265 // machine instruction, such as arguments to a CALL, return value of
266 // a CALL (if any), and return value of a RETURN.
267 //---------------------------------------------------------------------------
269 class MachineInstr : public Annotable, // MachineInstrs are annotable
270 public NonCopyable { // Disable copy operations
271 MachineOpCode opCode; // the opcode
272 OpCodeMask opCodeMask; // extra bits for variants of an opcode
273 std::vector<MachineOperand> operands; // the operands
277 bool isDef, isDefAndUse;
279 ImplicitRef(Value *V, bool D, bool DU) : Val(V), isDef(D), isDefAndUse(DU){}
282 // implicitRefs - Values implicitly referenced by this machine instruction
284 std::vector<ImplicitRef> implicitRefs;
286 // regsUsed - all machine registers used for this instruction, including regs
287 // used to save values across the instruction. This is a bitset of registers.
288 std::vector<bool> regsUsed;
290 /*ctor*/ MachineInstr (MachineOpCode _opCode,
291 OpCodeMask _opCodeMask = 0x0);
292 /*ctor*/ MachineInstr (MachineOpCode _opCode,
293 unsigned numOperands,
294 OpCodeMask _opCodeMask = 0x0);
295 inline ~MachineInstr () {}
298 // Support to rewrite a machine instruction in place: for now, simply
299 // replace() and then set new operands with Set.*Operand methods below.
301 void replace (MachineOpCode _opCode,
302 unsigned numOperands,
303 OpCodeMask _opCodeMask = 0x0);
306 // The op code. Note that MachineOpCode is a target-specific type.
308 const MachineOpCode getOpCode () const { return opCode; }
311 // Information about explicit operands of the instruction
313 unsigned int getNumOperands () const { return operands.size(); }
315 bool operandIsDefined(unsigned i) const;
316 bool operandIsDefinedAndUsed(unsigned i) const;
318 const MachineOperand& getOperand (unsigned i) const;
319 MachineOperand& getOperand (unsigned i);
322 // Information about implicit operands of the instruction
324 unsigned getNumImplicitRefs() const{ return implicitRefs.size();}
326 bool implicitRefIsDefined(unsigned i) const;
327 bool implicitRefIsDefinedAndUsed(unsigned i) const;
329 const Value* getImplicitRef (unsigned i) const;
330 Value* getImplicitRef (unsigned i);
333 // Information about registers used in this instruction
335 const std::vector<bool> &getRegsUsed () const { return regsUsed; }
337 // insertUsedReg - Add a register to the Used registers set...
338 void insertUsedReg(unsigned Reg) {
339 if (Reg >= regsUsed.size())
340 regsUsed.resize(Reg+1);
341 regsUsed[Reg] = true;
348 friend std::ostream& operator<< (std::ostream& os,
349 const MachineInstr& minstr);
352 // Define iterators to access the Value operands of the Machine Instruction.
353 // begin() and end() are defined to produce these iterators...
355 template<class _MI, class _V> class ValOpIterator;
356 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
357 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
360 // Access to set the operands when building the machine instruction
362 void SetMachineOperandVal(unsigned i,
363 MachineOperand::MachineOperandType
367 bool isDefAndUse=false);
368 void SetMachineOperandConst(unsigned i,
369 MachineOperand::MachineOperandType
372 void SetMachineOperandReg(unsigned i, int regNum,
374 bool isDefAndUse=false,
377 void addImplicitRef (Value* val,
379 bool isDefAndUse=false);
381 void setImplicitRef (unsigned i,
384 bool isDefAndUse=false);
386 unsigned substituteValue (const Value* oldVal,
388 bool defsOnly = true);
390 void setOperandHi32 (unsigned i);
391 void setOperandLo32 (unsigned i);
392 void setOperandHi64 (unsigned i);
393 void setOperandLo64 (unsigned i);
396 // Replaces the Value for the operand with its allocated
397 // physical register after register allocation is complete.
399 void SetRegForOperand(unsigned i, int regNum);
402 // Iterator to enumerate machine operands.
404 template<class MITy, class VTy>
405 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
409 inline void skipToNextVal() {
410 while (i < MI->getNumOperands() &&
411 !((MI->getOperand(i).getOperandType() == MachineOperand::MO_VirtualRegister ||
412 MI->getOperand(i).getOperandType() == MachineOperand::MO_CCRegister)
413 && MI->getOperand(i).getVRegValue() != 0))
417 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
422 typedef ValOpIterator<MITy, VTy> _Self;
424 inline VTy operator*() const {
425 return MI->getOperand(i).getVRegValue();
428 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
429 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
431 inline VTy operator->() const { return operator*(); }
433 inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
434 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
436 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
437 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
439 inline bool operator==(const _Self &y) const {
442 inline bool operator!=(const _Self &y) const {
443 return !operator==(y);
446 static _Self begin(MITy MI) {
449 static _Self end(MITy MI) {
450 return _Self(MI, MI->getNumOperands());
454 // define begin() and end()
455 val_op_iterator begin() { return val_op_iterator::begin(this); }
456 val_op_iterator end() { return val_op_iterator::end(this); }
458 const_val_op_iterator begin() const {
459 return const_val_op_iterator::begin(this);
461 const_val_op_iterator end() const {
462 return const_val_op_iterator::end(this);
467 inline MachineOperand&
468 MachineInstr::getOperand(unsigned int i)
470 assert(i < operands.size() && "getOperand() out of range!");
474 inline const MachineOperand&
475 MachineInstr::getOperand(unsigned int i) const
477 assert(i < operands.size() && "getOperand() out of range!");
482 MachineInstr::operandIsDefined(unsigned int i) const
484 return getOperand(i).opIsDef();
488 MachineInstr::operandIsDefinedAndUsed(unsigned int i) const
490 return getOperand(i).opIsDefAndUse();
494 MachineInstr::implicitRefIsDefined(unsigned i) const
496 assert(i < implicitRefs.size() && "operand out of range!");
497 return implicitRefs[i].isDef;
501 MachineInstr::implicitRefIsDefinedAndUsed(unsigned i) const
503 assert(i < implicitRefs.size() && "operand out of range!");
504 return implicitRefs[i].isDefAndUse;
508 MachineInstr::getImplicitRef(unsigned i) const
510 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
511 return implicitRefs[i].Val;
515 MachineInstr::getImplicitRef(unsigned i)
517 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
518 return implicitRefs[i].Val;
522 MachineInstr::addImplicitRef(Value* val,
525 implicitRefs.push_back(ImplicitRef(val, isDef, isDefAndUse));
529 MachineInstr::setImplicitRef(unsigned int i,
534 assert(i < implicitRefs.size() && "setImplicitRef() out of range!");
535 implicitRefs[i].Val = val;
536 implicitRefs[i].isDef = isDef;
537 implicitRefs[i].isDefAndUse = isDefAndUse;
541 MachineInstr::setOperandHi32(unsigned i)
543 operands[i].markHi32();
547 MachineInstr::setOperandLo32(unsigned i)
549 operands[i].markLo32();
553 MachineInstr::setOperandHi64(unsigned i)
555 operands[i].markHi64();
559 MachineInstr::setOperandLo64(unsigned i)
561 operands[i].markLo64();
565 //---------------------------------------------------------------------------
567 //---------------------------------------------------------------------------
569 std::ostream& operator<< (std::ostream& os, const MachineInstr& minstr);
571 std::ostream& operator<< (std::ostream& os, const MachineOperand& mop);
573 void PrintMachineInstructions(const Function *F);