1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Target/MachineInstrInfo.h"
13 #include "llvm/Annotation.h"
14 #include <Support/iterator>
15 #include <Support/hash_set>
18 //---------------------------------------------------------------------------
19 // class MachineOperand
22 // Representation of each machine instruction operand.
23 // This class is designed so that you can allocate a vector of operands
24 // first and initialize each one later.
26 // E.g, for this VM instruction:
27 // ptr = alloca type, numElements
28 // we generate 2 machine instructions on the SPARC:
30 // mul Constant, Numelements -> Reg
31 // add %sp, Reg -> Ptr
33 // Each instruction has 3 operands, listed above. Of those:
34 // - Reg, NumElements, and Ptr are of operand type MO_Register.
35 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
37 // For the register operands, the virtual register type is as follows:
39 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
40 // MachineInstr* minstr will point to the instruction that computes reg.
42 // - %sp will be of virtual register type MO_MachineReg.
43 // The field regNum identifies the machine register.
45 // - NumElements will be of virtual register type MO_VirtualReg.
46 // The field Value* value identifies the value.
48 // - Ptr will also be of virtual register type MO_VirtualReg.
49 // Again, the field Value* value identifies the value.
51 //---------------------------------------------------------------------------
54 class MachineOperand {
56 enum MachineOperandType {
57 MO_VirtualRegister, // virtual register for *value
58 MO_MachineRegister, // pre-assigned machine register `regNum'
66 // Bit fields of the flags variable used for different operand properties
67 static const char DEFFLAG = 0x1; // this is a def of the operand
68 static const char DEFUSEFLAG = 0x2; // this is both a def and a use
69 static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
70 static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
71 static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
72 static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
75 MachineOperandType opType;
78 Value* value; // BasicBlockVal for a label operand.
79 // ConstantVal for a non-address immediate.
80 // Virtual register for an SSA operand,
81 // including hidden operands required for
82 // the generated machine code.
83 int64_t immedVal; // constant value for an explicit constant
86 int regNum; // register number for an explicit register
87 // will be set for a value after reg allocation
88 char flags; // see bit field definitions above
91 /*ctor*/ MachineOperand ();
92 /*ctor*/ MachineOperand (MachineOperandType operandType,
94 /*copy ctor*/ MachineOperand (const MachineOperand&);
95 /*dtor*/ ~MachineOperand () {}
97 // Accessor methods. Caller is responsible for checking the
98 // operand type before invoking the corresponding accessor.
100 inline MachineOperandType getOperandType() const {
103 inline Value* getVRegValue () const {
104 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
105 opType == MO_PCRelativeDisp);
108 inline Value* getVRegValueOrNull() const {
109 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
110 opType == MO_PCRelativeDisp)? value : NULL;
112 inline int getMachineRegNum() const {
113 assert(opType == MO_MachineRegister);
116 inline int64_t getImmedValue () const {
117 assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
120 inline bool opIsDef () const {
121 return flags & DEFFLAG;
123 inline bool opIsDefAndUse () const {
124 return flags & DEFUSEFLAG;
126 inline bool opHiBits32 () const {
127 return flags & HIFLAG32;
129 inline bool opLoBits32 () const {
130 return flags & LOFLAG32;
132 inline bool opHiBits64 () const {
133 return flags & HIFLAG64;
135 inline bool opLoBits64 () const {
136 return flags & LOFLAG64;
139 // used to check if a machine register has been allocated to this operand
140 inline bool hasAllocatedReg() const {
141 return (regNum >= 0 &&
142 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
143 opType == MO_MachineRegister));
146 // used to get the reg number if when one is allocated
147 inline int getAllocatedRegNum() const {
148 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
149 opType == MO_MachineRegister);
155 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
158 // These functions are provided so that a vector of operands can be
159 // statically allocated and individual ones can be initialized later.
160 // Give class MachineInstr access to these functions.
162 void Initialize (MachineOperandType operandType,
164 void InitializeConst (MachineOperandType operandType,
166 void InitializeReg (int regNum,
169 // Construction methods needed for fine-grain control.
170 // These must be accessed via coresponding methods in MachineInstr.
171 void markDef() { flags |= DEFFLAG; }
172 void markDefAndUse() { flags |= DEFUSEFLAG; }
173 void markHi32() { flags |= HIFLAG32; }
174 void markLo32() { flags |= LOFLAG32; }
175 void markHi64() { flags |= HIFLAG64; }
176 void markLo64() { flags |= LOFLAG64; }
178 // Replaces the Value with its corresponding physical register after
179 // register allocation is complete
180 void setRegForValue(int reg) {
181 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
182 opType == MO_MachineRegister);
186 friend class MachineInstr;
191 MachineOperand::MachineOperand()
192 : opType(MO_VirtualRegister),
199 MachineOperand::MachineOperand(MachineOperandType operandType,
201 : opType(operandType),
208 MachineOperand::MachineOperand(const MachineOperand& mo)
213 case MO_VirtualRegister:
214 case MO_CCRegister: value = mo.value; break;
215 case MO_MachineRegister: regNum = mo.regNum; break;
216 case MO_SignExtendedImmed:
217 case MO_UnextendedImmed:
218 case MO_PCRelativeDisp: immedVal = mo.immedVal; break;
224 MachineOperand::Initialize(MachineOperandType operandType,
227 opType = operandType;
234 MachineOperand::InitializeConst(MachineOperandType operandType,
237 opType = operandType;
245 MachineOperand::InitializeReg(int _regNum, bool isCCReg)
247 opType = isCCReg? MO_CCRegister : MO_MachineRegister;
249 regNum = (int) _regNum;
254 //---------------------------------------------------------------------------
255 // class MachineInstr
258 // Representation of each machine instruction.
260 // MachineOpCode must be an enum, defined separately for each target.
261 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
263 // opCodeMask is used to record variants of an instruction.
264 // E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
265 // ANNUL: if 1: Annul delay slot instruction.
266 // PREDICT-NOT-TAKEN: if 1: predict branch not taken.
267 // Instead of creating 4 different opcodes for BNZ, we create a single
268 // opcode and set bits in opCodeMask for each of these flags.
270 // There are 2 kinds of operands:
272 // (1) Explicit operands of the machine instruction in vector operands[]
274 // (2) "Implicit operands" are values implicitly used or defined by the
275 // machine instruction, such as arguments to a CALL, return value of
276 // a CALL (if any), and return value of a RETURN.
277 //---------------------------------------------------------------------------
279 class MachineInstr : public Annotable, // Values are annotable
280 public NonCopyable { // Disable copy operations
281 MachineOpCode opCode; // the opcode
282 OpCodeMask opCodeMask; // extra bits for variants of an opcode
283 std::vector<MachineOperand> operands; // the operands
284 std::vector<Value*> implicitRefs; // values implicitly referenced by this
285 std::vector<bool> implicitIsDef; // machine instruction (eg, call args)
286 std::vector<bool> implicitIsDefAndUse;
287 hash_set<int> regsUsed; // all machine registers used for this
288 // instruction, including regs used
289 // to save values across the instr.
291 /*ctor*/ MachineInstr (MachineOpCode _opCode,
292 OpCodeMask _opCodeMask = 0x0);
293 /*ctor*/ MachineInstr (MachineOpCode _opCode,
294 unsigned numOperands,
295 OpCodeMask _opCodeMask = 0x0);
296 inline ~MachineInstr () {}
299 // Support to rewrite a machine instruction in place: for now, simply
300 // replace() and then set new operands with Set.*Operand methods below.
302 void replace (MachineOpCode _opCode,
303 unsigned numOperands,
304 OpCodeMask _opCodeMask = 0x0);
307 // The op code. Note that MachineOpCode is a target-specific type.
309 const MachineOpCode getOpCode () const { return opCode; }
312 // Information about explicit operands of the instruction
314 unsigned int getNumOperands () const { return operands.size(); }
316 bool operandIsDefined(unsigned i) const;
317 bool operandIsDefinedAndUsed(unsigned i) const;
319 const MachineOperand& getOperand (unsigned i) const;
320 MachineOperand& getOperand (unsigned i);
323 // Information about implicit operands of the instruction
325 unsigned getNumImplicitRefs() const{return implicitRefs.size();}
327 bool implicitRefIsDefined(unsigned i) const;
328 bool implicitRefIsDefinedAndUsed(unsigned i) const;
330 const Value* getImplicitRef (unsigned i) const;
331 Value* getImplicitRef (unsigned i);
334 // Information about registers used in this instruction
336 const hash_set<int>& getRegsUsed () const { return regsUsed; }
337 hash_set<int>& getRegsUsed () { return regsUsed; }
343 friend std::ostream& operator<< (std::ostream& os,
344 const MachineInstr& minstr);
347 // Define iterators to access the Value operands of the Machine Instruction.
348 // begin() and end() are defined to produce these iterators...
350 template<class _MI, class _V> class ValOpIterator;
351 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
352 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
355 // Access to set the operands when building the machine instruction
357 void SetMachineOperandVal(unsigned i,
358 MachineOperand::MachineOperandType
362 bool isDefAndUse=false);
363 void SetMachineOperandConst(unsigned i,
364 MachineOperand::MachineOperandType
367 void SetMachineOperandReg(unsigned i, int regNum,
369 bool isDefAndUse=false,
372 void addImplicitRef (Value* val,
374 bool isDefAndUse=false);
376 void setImplicitRef (unsigned i,
379 bool isDefAndUse=false);
381 unsigned substituteValue (const Value* oldVal,
383 bool defsOnly = true);
385 void setOperandHi32 (unsigned i);
386 void setOperandLo32 (unsigned i);
387 void setOperandHi64 (unsigned i);
388 void setOperandLo64 (unsigned i);
391 // Replaces the Value for the operand with its allocated
392 // physical register after register allocation is complete.
394 void SetRegForOperand(unsigned i, int regNum);
397 // Iterator to enumerate machine operands.
399 template<class MITy, class VTy>
400 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
404 inline void skipToNextVal() {
405 while (i < MI->getNumOperands() &&
406 !((MI->getOperand(i).getOperandType() == MachineOperand::MO_VirtualRegister ||
407 MI->getOperand(i).getOperandType() == MachineOperand::MO_CCRegister)
408 && MI->getOperand(i).getVRegValue() != 0))
412 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
417 typedef ValOpIterator<MITy, VTy> _Self;
419 inline VTy operator*() const {
420 return MI->getOperand(i).getVRegValue();
423 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
424 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
426 inline VTy operator->() const { return operator*(); }
428 inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
429 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
431 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
432 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
434 inline bool operator==(const _Self &y) const {
437 inline bool operator!=(const _Self &y) const {
438 return !operator==(y);
441 static _Self begin(MITy MI) {
444 static _Self end(MITy MI) {
445 return _Self(MI, MI->getNumOperands());
449 // define begin() and end()
450 val_op_iterator begin() { return val_op_iterator::begin(this); }
451 val_op_iterator end() { return val_op_iterator::end(this); }
453 const_val_op_iterator begin() const {
454 return const_val_op_iterator::begin(this);
456 const_val_op_iterator end() const {
457 return const_val_op_iterator::end(this);
462 inline MachineOperand&
463 MachineInstr::getOperand(unsigned int i)
465 assert(i < operands.size() && "getOperand() out of range!");
469 inline const MachineOperand&
470 MachineInstr::getOperand(unsigned int i) const
472 assert(i < operands.size() && "getOperand() out of range!");
477 MachineInstr::operandIsDefined(unsigned int i) const
479 return getOperand(i).opIsDef();
483 MachineInstr::operandIsDefinedAndUsed(unsigned int i) const
485 return getOperand(i).opIsDefAndUse();
489 MachineInstr::implicitRefIsDefined(unsigned int i) const
491 assert(i < implicitIsDef.size() && "operand out of range!");
492 return implicitIsDef[i];
496 MachineInstr::implicitRefIsDefinedAndUsed(unsigned int i) const
498 assert(i < implicitIsDefAndUse.size() && "operand out of range!");
499 return implicitIsDefAndUse[i];
503 MachineInstr::getImplicitRef(unsigned int i) const
505 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
506 return implicitRefs[i];
510 MachineInstr::getImplicitRef(unsigned int i)
512 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
513 return implicitRefs[i];
517 MachineInstr::addImplicitRef(Value* val,
521 implicitRefs.push_back(val);
522 implicitIsDef.push_back(isDef);
523 implicitIsDefAndUse.push_back(isDefAndUse);
527 MachineInstr::setImplicitRef(unsigned int i,
532 assert(i < implicitRefs.size() && "setImplicitRef() out of range!");
533 implicitRefs[i] = val;
534 implicitIsDef[i] = isDef;
535 implicitIsDefAndUse[i] = isDefAndUse;
539 MachineInstr::setOperandHi32(unsigned i)
541 operands[i].markHi32();
545 MachineInstr::setOperandLo32(unsigned i)
547 operands[i].markLo32();
551 MachineInstr::setOperandHi64(unsigned i)
553 operands[i].markHi64();
557 MachineInstr::setOperandLo64(unsigned i)
559 operands[i].markLo64();
563 //---------------------------------------------------------------------------
565 //---------------------------------------------------------------------------
567 std::ostream& operator<< (std::ostream& os, const MachineInstr& minstr);
569 std::ostream& operator<< (std::ostream& os, const MachineOperand& mop);
571 void PrintMachineInstructions(const Function *F);